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Journal articles on the topic 'UMOSFET'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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1

Hung, Chia Lung, Yi Kai Hsiao, Chang Ching Tu, and Hao Chung Kuo. "Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications." Materials Science Forum 1088 (May 18, 2023): 41–49. http://dx.doi.org/10.4028/p-56sbi2.

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A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the

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2

Jiang, Jheng-Yi, Tian-Li Wu, Feng Zhao, and Chih-Fang Huang. "Numerical Study of 4H-SiC UMOSFETs with Split-Gate and P+ Shielding." Energies 13, no. 5 (2020): 1122. http://dx.doi.org/10.3390/en13051122.

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In this paper, performances of a 4H-SiC UMOSFET with split gate and P+ shielding in different configurations are simulated and compared, with an emphasis on the switching characteristics and short circuit capability. A novel structure with the split gate in touch with the P+ shielding is proposed. The key design issues for 4H-SiC UMOSFETs are trench gate dielectric protection and reverse transfer capacitance Crss reduction. Based on simulation results, it is concluded that a UMOSFET with a gate structure combining split gate grounded to the trench bottom protection P+ shielding layer and a cur

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3

Cheon, Jinhee, and Kwangsoo Kim. "Numerical Simulation Analysis of Switching Characteristics in the Source-Trench MOSFET’s." Electronics 9, no. 11 (2020): 1895. http://dx.doi.org/10.3390/electronics9111895.

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In this paper, we compare the static and switching characteristics of the 4H-SiC conventional UMOSFET (C-UMOSFET), double trench MOSFET (DT-MOSFET) and source trench MOSFET (ST-MOSFET) through TCAD simulation. In particular, the effect of the trenched source region and the gate trench bottom P+ shielding region on the capacitance is analyzed, and the dynamic characteristics of the three structures are compared. The input capacitance is almost identical in all three structures. On the other hand, the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is reduced by 44% and 24%, respectively

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4

Borca-Tasciuc, Giorgian, and Tat-Sing Paul Chow. "Comparative Performance Evaluation for GaN Bidirectional, 1.2–10kV, Conventional and Superjunction Current Aperture Vertical Electron Transistors (CAVETs) and UMOSFETs." ECS Meeting Abstracts MA2025-01, no. 35 (2025): 1700. https://doi.org/10.1149/ma2025-01351700mtgabs.

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The performance potentials and limits of bidirectional (BD) GaN current aperture vertical electron transistor (CAVET) and BD GaN UMOSFETs are evaluated for breakdown voltage (BV) ratings ranging from 1.2–10kV. Bidirectionality is achieved by connecting two transistors in either a common-source (CS) or common-drain (CD) configuration. For both CAVETs and UMOSFETs, the drift region design is varied among conventional, doped superjunction (DSJ), and polarized superjunction (PSJ) structures. In the case of CD designs with a conventional drift region, the monolithic approach involves sharing a comm

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5

Chen, Runze, Lixin Wang, Hongkai Zhang, Mengyao Cui, and Min Guo. "A New Split Gate Resurf Stepped Oxide UMOSFET Structure with High Doped Epitaxial Layer for Improving Figure of Merit (FOM)." Applied Sciences 10, no. 21 (2020): 7895. http://dx.doi.org/10.3390/app10217895.

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The split gate resurf stepped oxide with highly doped epitaxial layer (HDSGRSO) UMOSFET has been proposed. The epitaxial layer of HDSGRSO u-shape metal oxide semiconductor field effect transistor (UMOSFET) has been divided into three parts: the upper epitaxial layer, the lower epitaxial layer and the middle epitaxial layer with higher doping concentration. The research shows that the reduced SURface field (RESURF) active has been enhanced due to the high doped epitaxial layer, which can modulate the electric field distribution and reduce the internal high electric field. Therefore, the HDGRSO

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6

Chen, Runze, Lixin Wang, Naixia Jiu, Hongkai Zhang, and Min Guo. "Simulation and Result Analysis of Split Gate Resurf Stepped Oxide UMOFSET with Floating Electrode for Improved Performance." Electronics 8, no. 12 (2019): 1553. http://dx.doi.org/10.3390/electronics8121553.

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In this study, a split-gate resurf stepped oxide with a floating electrode (FSGRSO) UMOSFET has been proposed. The source in the trench is divided into two electrodes, namely: the upper electrode and the lower electrode. The upper one is the floating electrode, which redistributes the electric potential vertically, and improves the breakdown voltage and figure of merit (FOM). The breakdown (BV) and FOM of the FSGRSO UMOSFET have been improved up to 27.3% and 62.7%, respectively, compared with the SGRSO UMOSFET, according to the simulation results.

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7

Chen, Runze, Lixin Wang, Naixia Jiu, Hongkai Zhang, and Min Guo. "An Optimized Structure of Split-Gate Resurf Stepped Oxide UMOSFET." Electronics 9, no. 5 (2020): 745. http://dx.doi.org/10.3390/electronics9050745.

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In this paper, a split-gate resurf stepped oxide with double floating electrodes (DFSGRSO) U-shape metal oxide semiconductor field-effect transistor (UMOSFET) is proposed. The floating electrodes are symmetrically distributed on both sides of the source electrode in the trench. The performance of the DFSGRSO UMOSFET with different size of floating electrodes is simulated and analyzed. The simulation results reveal that the floating electrodes can modulate the distribution of the electric field in the drift area, improving the performance of the device significantly. The breakdown voltage (BV)

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8

Harada, Shinsuke, Sachiko Ito, Makoto Kato, et al. "Isotropic Channel Mobility in UMOSFETs on 4H-SiC C-Face with Vicinal Off-Angle." Materials Science Forum 645-648 (April 2010): 999–1004. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.999.

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UMOSFET is theoretically suitable to decrease the on-resistance of the MOSFET. In this study, in order to determine the cell structure of the SiC UMOSFET with extremely low on-resistance, influences of the orientation of the trench and the off-angle of the wafer on the MOS properties are investigated. The channel resistance, gate I-V curves and instability of threshold voltage are superior on the {11-20} planes as compared with other planes. On the vicinal off wafer, influence of the off-angle disappears and the properties on the equivalent planes are almost the same. The obtained results indi

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9

Alberton, S. G., A. C. V. Bôas, N. H. Medina, et al. "Neutron-Induced Radiation Effects in UMOS Transistor." Journal of Physics: Conference Series 2340, no. 1 (2022): 012046. http://dx.doi.org/10.1088/1742-6596/2340/1/012046.

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Abstract Ground level electronics and avionics systems may suffer from radiation effects induced by neutrons. Neutrons can induce radiation effects in electronic devices via fusion-evaporation nuclear reactions, but few studies have been reported for technologies such as UMOSFET. In this work, estimates and experimental studies on neutron-induced radiation effects via nuclear reactions in a Si-based UMOSFET are presented. Methods for probability estimates of neutron-induced Single-Event Effects (SEEs) in Si-based power transistors and neutron beam energy measurement is presented. The energy sp

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10

Harada, Shinsuke, Yusuke Kobayashi, A. Kinoshita, et al. "1200 V SiC IE-UMOSFET with Low On-Resistance and High Threshold Voltage." Materials Science Forum 897 (May 2017): 497–500. http://dx.doi.org/10.4028/www.scientific.net/msf.897.497.

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A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth o

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11

Akansha, Ephraim* Neelesh Agrawal Anil Kumar A.K. Jaiswal. "STUDY OF ELECTRICAL CHARACTERISTIC OF NEW P-TYPE TRENCHED UMOSFET." Global Journal of Engineering Science and Research Management 4, no. 8 (2017): 20–25. https://doi.org/10.5281/zenodo.841194.

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In this paper p-type trenched UMOSFET was designed without super junction and constructed like any other conventional MOSFET. Characteristic curve was studied between drain current verses drain voltage and drain current verses gate voltage. The trench was designed under TCAD simulation tool Silvaco software using etching process. The specific channel length of the p-type UMOSFET has been concentrated as 0.9 microns. The device structures are designed using Silvaco Athena and characteristics were examined using Silvaco Atlas.

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12

Na, Jaeyeop, Jinhee Cheon, and Kwangsoo Kim. "High performance 4H-SiC MOSFET with deep source trench." Semiconductor Science and Technology 37, no. 4 (2022): 045004. http://dx.doi.org/10.1088/1361-6641/ac5103.

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Abstract In this study, we investigated a 4H-SiC deep source trench metal-oxide semiconductor field-effect transistor (DST-MOSFET) using technology computer-aided design numerical simulations. The proposed DST-MOSFET comprises a P-pillar formed along with the DST and a side P+ shielding region (SPR), which replaces the gate trench bottom SPR. Owing to the superjunction generated by the P-pillar and N-drift region, the static characteristics of the DST-MOSFET were superior to those of the trench gate MOSFET (UMOSFET) and double-trench MOSFET (DT-MOSFET). The specific on-resistance and Baliga’s

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13

Chowdhury, Sauvik, Zachary Stum, Zhong Da Li, Katsunori Ueno, and T. Paul Chow. "Comparison of 600V Si, SiC and GaN Power Devices." Materials Science Forum 778-780 (February 2014): 971–74. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.971.

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In this paper the DC and switching performance of 600V Si, SiC and GaN power devices using device simulation. The devices compared are Si superjunction MOSFET, Si field stop IGBT, SiC UMOSFET and GaN HEMT.

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14

Tsengyou Syau, P. Venkatraman, and B. J. Baliga. "Comparison of ultralow specific on-resistance UMOSFET structures: the ACCUFET, EXTFET, INVFET, and conventional UMOSFET's." IEEE Transactions on Electron Devices 41, no. 5 (1994): 800–808. http://dx.doi.org/10.1109/16.285034.

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15

Ying Wang, Hai-Fan Hu, Wen-Li Jiao, and Chao Cheng. "Gate Enhanced Power UMOSFET With Ultralow On-Resistance." IEEE Electron Device Letters 31, no. 4 (2010): 338–40. http://dx.doi.org/10.1109/led.2010.2040576.

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16

Wang, Debo, Quanyuan Feng, Xiaopei Chen, and Tao Jin. "Failure analysis and improvement of 60V power UMOSFET." Microelectronics Reliability 54, no. 12 (2014): 2782–87. http://dx.doi.org/10.1016/j.microrel.2014.07.003.

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17

Syau, T., P. Venkatraman, and B. J. Baliga. "Comparison of ultralow specific on-resistance UMOSFET structures." IEEE Transactions on Electron Devices 39, no. 11 (1992): 2672–73. http://dx.doi.org/10.1109/16.163545.

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18

Zhou, Xuanze, Yongjian Ma, Guangwei Xu та ін. "Enhancement-mode β-Ga₂O₃ U-shaped gate trench vertical MOSFET realized by oxygen annealing". Applied Physics Letters 121, № 22 (2022): 223501. http://dx.doi.org/10.1063/5.0130292.

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Vertical metal–oxide–semiconductor field effect transistor (MOSFET) is essential to the future application of ultrawide bandgap β-Ga2O3. In this work, we demonstrated an enhancement-mode β-Ga2O3 U-shaped gate trench vertical metal–oxide–semiconductor field effect transistor (UMOSFET) featuring a current blocking layer (CBL). The CBL was realized by high-temperature annealing under oxygen ambient, which provided electrical isolation between the source and drain electrodes. The CBL thicknesses of different annealing temperatures were derived from C–V measurements and the Fermi level position of

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19

Chang, H. R., V. A. K. Temple, and B. J. Baliga. "Numerical and experimental comparison of vertical DMOSFET and UMOSFET." IEEE Transactions on Electron Devices 35, no. 12 (1988): 2459–60. http://dx.doi.org/10.1109/16.8904.

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20

Wang, Ying, Wen-Li Jiao, Hai-Fan Hu, Yun-Tao Liu, and Jing Gao. "Split-Gate-Enhanced Power UMOSFET With Soft Reverse Recovery." IEEE Transactions on Electron Devices 60, no. 6 (2013): 2084–89. http://dx.doi.org/10.1109/ted.2013.2257789.

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21

Wang, Ying, Cheng-Hao Yu, Meng-Shi Li, Fei Cao, and Yan-Juan Liu. "High-Performance Split-Gate-Enhanced UMOSFET With Dual Channels." IEEE Transactions on Electron Devices 64, no. 4 (2017): 1455–60. http://dx.doi.org/10.1109/ted.2017.2665589.

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22

Takenaka, Kensuke, Takeshi Tawara, Syunki Narita, and Shinsuke Harada. "Double-implanted 4H-SiC superjunction UMOSFET without bipolar degradation." Japanese Journal of Applied Physics 64, no. 2 (2025): 02SP43. https://doi.org/10.35848/1347-4065/adacf2.

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Abstract We demonstrated trench-gate 4H-SiC superjunction MOSFET (SJUMOS) without bipolar degradation using a double implantation process with a multi-epitaxial method. A conventional SJUMOS with a single implantation of aluminum ions can suppress bipolar degradation at the current stress below 1000 A cm−2 because the carrier lifetime of the 4H-SiC epitaxial film is shortened by the damage generated during aluminum ions implantation for p-column formation. To further suppress the bipolar degradation at above 1500 A cm−2, this study developed SJUMOS with the double implantation process. The n-c

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23

Jozi, Mohammad, Ali A. Orouji, and Morteza Fathipour. "Control of electric field in 4H-SiC UMOSFET: Physical investigation." Physica E: Low-dimensional Systems and Nanostructures 83 (September 2016): 107–13. http://dx.doi.org/10.1016/j.physe.2016.04.010.

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24

Wang, Ying, Hai-fan Hu, Cheng-hao Yu, and Hao Lan. "High-Performance Split-Gate Enhanced UMOSFET With p-Pillar Structure." IEEE Transactions on Electron Devices 60, no. 7 (2013): 2302–7. http://dx.doi.org/10.1109/ted.2013.2260547.

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25

Goh, Jinyoung, and Kwangsoo Kim. "Low on-resistance 4H-SiC UMOSFET with local floating superjunction." Journal of Computational Electronics 19, no. 1 (2019): 234–41. http://dx.doi.org/10.1007/s10825-019-01408-1.

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26

Wang, Ying, Hao Lan, Fei Cao, Yun-Tao Liu, and Lei Shao. "A novel power UMOSFET with a variable K dielectric layer." Chinese Physics B 21, no. 6 (2012): 068503. http://dx.doi.org/10.1088/1674-1056/21/6/068503.

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27

Harada, Shinsuke, Makoto Kato, Megumi Shinozaki, et al. "Low R_ons in 3kV 4H-SiC UMOSFET with MeV Implanted Buried P-Base Region." Materials Science Forum 821-823 (June 2015): 769–72. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.769.

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3kV UMOSFET with buried p-base regions was developed to realize the low on-resistance with low electric field in the gate oxide for off-state. The buried p-base region was formed simultaneously with the p-base region by utilizing MeV ion implantation. Influence by the structural parameter such as cell geometry and space between the buried p-base region and the trench gate was investigated. The hexagonal cell with high channel density exhibits an extremely low on-resistance of 6.8 mΩcm2 with threshold voltage of 5.0 V at room temperature.

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28

Suliman, S. A., N. Gollagunta, L. Trabzon, et al. "The dependence of UMOSFET characteristics and reliability on geometry and processing." Semiconductor Science and Technology 16, no. 6 (2001): 447–54. http://dx.doi.org/10.1088/0268-1242/16/6/305.

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29

Fang, Jun-Peng, Ying Wang, Yue Hao, Jun Liu, and Ling-Ling Sun. "Hardening of Split-Gate Power UMOSFET Against High-Power Microwave Radiation." IEEE Electron Device Letters 38, no. 8 (2017): 1067–70. http://dx.doi.org/10.1109/led.2017.2718538.

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30

Syau, T., P. Venkatraman, and B. J. Baliga. "Extended trench-gate power UMOSFET structure with ultralow specific on-resistance." Electronics Letters 28, no. 9 (1992): 865. http://dx.doi.org/10.1049/el:19920546.

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31

Cheng, You-Zhong, Ying Wang, Xue Wu, and Fei Cao. "4H-SiC UMOSFET With an Electric Field Modulation Region Below P-Body." IEEE Transactions on Electron Devices 67, no. 8 (2020): 3298–303. http://dx.doi.org/10.1109/ted.2020.3004777.

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32

Xu, Binyi, Yuhao Zhao, Yuan Wei, Kaifu Hu, Xiaodong Zhang, and Chong Shen. "Research on new structure of high voltage 4H-SiC power UMOSFET devices." Journal of Physics: Conference Series 2849, no. 1 (2024): 012011. http://dx.doi.org/10.1088/1742-6596/2849/1/012011.

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Abstract In this article, we investigate a novel optimized 4H-SiC U-shaped groove gate MOSFET (UMOSFET) structure, which is characterized by improving the gate to a stepped gate structure, adding an n-type wrapped p+region at the bottom of the gate, and finally adding an unevenly distributed superjunction p/n structure at the bottom. We improve the problem of the gate oxygen electric field at the corner by using a stepped gate structure. Next, we design an n-type doping encapsulation (nw) region that wraps around the p+gate oxygen protection zone with a higher concentration than the drift zone

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33

Ying, Wang, Hu Haifan, Wang Liguo, and Yu Chenghao. "Split gate resurf stepped oxide UMOSFET with P‐pillar for improved performance." IET Power Electronics 7, no. 4 (2014): 965–72. http://dx.doi.org/10.1049/iet-pel.2013.0363.

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34

Wang, Ying, Hai-Fan Hu, and Wen-li Jiao. "Split-Gate-Enhanced UMOSFET With an Optimized Layout of Trench Surrounding Mesa." IEEE Transactions on Electron Devices 59, no. 11 (2012): 3037–41. http://dx.doi.org/10.1109/ted.2012.2211601.

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35

Matsumoto, S., T. Ohno, H. Ishii, and H. Yoshino. "A high-performance self-aligned UMOSFET with a vertical trench contact structure." IEEE Transactions on Electron Devices 41, no. 5 (1994): 814–18. http://dx.doi.org/10.1109/16.285036.

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36

Wang, Ying, Ya-Chao Ma, Yue Hao, Yue Hu, Gaofeng Wang, and Fei Cao. "Simulation Study of 4H-SiC UMOSFET Structure With p+-polySi/SiC Shielded Region." IEEE Transactions on Electron Devices 64, no. 9 (2017): 3719–24. http://dx.doi.org/10.1109/ted.2017.2723502.

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37

Bharti, Deepshikha, and Aminul Islam. "Optimization of SiC UMOSFET Structure for Improvement of Breakdown Voltage and ON-Resistance." IEEE Transactions on Electron Devices 65, no. 2 (2018): 615–21. http://dx.doi.org/10.1109/ted.2017.2779482.

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38

Krishnamurthy, Saranya, Ramani Kannan та Fawnizu Azmadi Hussin. "Single event burnout hardening of trench shielded power UMOSFET using High-κ dielectrics". Materials Research Express 7, № 3 (2020): 035907. http://dx.doi.org/10.1088/2053-1591/ab816a.

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39

Hsing, Edward H. S., and Jeffery L. Gray. "Numerical analysis of relationship between blocking and driving capability in 6H-SiC UMOSFET." Microelectronics Journal 30, no. 1 (1999): 1–14. http://dx.doi.org/10.1016/s0026-2692(97)00050-5.

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40

Harada, Shinsuke, Yusuke Kobayashi, Keiko Ariyoshi, et al. "3.3-kV-Class 4H-SiC MeV-Implanted UMOSFET With Reduced Gate Oxide Field." IEEE Electron Device Letters 37, no. 3 (2016): 314–16. http://dx.doi.org/10.1109/led.2016.2520464.

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41

Hu, Xiarong, Yangjie Ou, Ruixue Mai, Mingyue Li, Yonggen Xu, and Dong Liu. "1.2 kV 4H–SiC Super Junction UMOSFET with a Low-K dielectric pillar." Micro and Nanostructures 176 (April 2023): 207526. http://dx.doi.org/10.1016/j.micrna.2023.207526.

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42

Kobayashi, Yusuke, Shinsuke Harada, Hiroshi Ishimori, et al. "3.3 kV-Class 4H-SiC UMOSFET by Double-Trench with Tilt Angle Ion Implantation." Materials Science Forum 858 (May 2016): 974–77. http://dx.doi.org/10.4028/www.scientific.net/msf.858.974.

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A 3.3 kV trench MOSFET with double-trench structure was demonstrated. The deep buried p-base regions were fabricated using tilt angle ion implantation into the sidewalls of the trench contacts. The distance between the trench gate and trench contact was determined through simulation, in order to optimize the trade-off between on-resistance (RonA) and the electrical field in the oxide (Eox). A tapered trench was located in the connective area between the edge termination and the active area, in order to maintain breakdown voltage. We achieved a RonA of 10.3 mWcm2 and a breakdown voltage of 3843

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43

Kim, Taehong, and Kwangsoo Kim. "High Breakdown Voltage and Low On-Resistance 4H-SiC UMOSFET with Source-Trench Optimization." ECS Journal of Solid State Science and Technology 8, no. 8 (2019): Q147—Q152. http://dx.doi.org/10.1149/2.0091908jss.

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44

Wang, Ying, Hai‐Fan Hu, Zheng Dou, and Cheng‐Hao Yu. "Way of operation to improve performance for advanced split‐gate resurf stepped oxide UMOSFET." IET Power Electronics 7, no. 12 (2014): 2964–68. http://dx.doi.org/10.1049/iet-pel.2013.0931.

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45

Orouji, Ali A., Mohammad Jozi, and Morteza Fathipour. "High-voltage and low specific on-resistance power UMOSFET using P and N type columns." Materials Science in Semiconductor Processing 39 (November 2015): 711–20. http://dx.doi.org/10.1016/j.mssp.2015.06.006.

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46

Kim, Tae-hong, and Kwang-soo Kim. "High Breakdown Voltage and Low On-resistance 4H-SiC UMOSFET with a Source-trench Oxide Structure." JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 20, no. 3 (2020): 225–30. http://dx.doi.org/10.5573/jsts.2020.20.3.225.

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47

Yu, Cheng-Hao, Ying Wang, Meng-Tian Bao, Xing-Ji Li, Jian-Qun Yang, and Fei Cao. "Impact of Heavy-Ion Irradiation in an 80-V Radiation-Hardened Split-Gate Trench Power UMOSFET." IEEE Transactions on Electron Devices 69, no. 2 (2022): 664–68. http://dx.doi.org/10.1109/ted.2021.3135369.

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48

Matsumoto, S., T. Ohno, and K. Izumi. "Ultralow specific on resistance UMOSFET with trench contacts for source and body regions realised by selfaligned process." Electronics Letters 27, no. 18 (1991): 1640. http://dx.doi.org/10.1049/el:19911025.

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49

Shen, Zhanwei, Feng Zhang, Guoguo Yan, et al. "High-Frequency Switching Properties and Low Oxide Electric Field and Energy Loss in a Reverse-Channel 4H-SiC UMOSFET." IEEE Transactions on Electron Devices 67, no. 10 (2020): 4046–53. http://dx.doi.org/10.1109/ted.2020.3005899.

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50

Kim, J., and K. Kim. "A Novel 4H-SiC Super Junction UMOSFET with Hetero-Junction Diode for Enhanced Reverse Recovery Characteristics and Low Switching Loss." Semiconductors 54, no. 5 (2020): 587–95. http://dx.doi.org/10.1134/s1063782620050061.

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