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Singh, Ashutosh Kumar. "Universal Asyncronous Receiver Transmitter." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (2024): 1054–56. http://dx.doi.org/10.22214/ijraset.2024.58997.
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Abstract: This project focuses on the Verilog-based design and implementation of a Universal Asynchronous ReceiverTransmitter (UART) communication module. The UART is a fundamental component in digital systems, facilitating serial data transmission between devices. Our objective is to develop a robust and efficient Verilog description of the UART module, emphasizing simplicity, modularity, and ease of integration. The baud rate generator allows for flexible communication speeds, accommodating diverse applications. The module ensures accurate framing of transmitted and received data through the proper generation of start and stop bits. Error-detection mechanisms are implemented to enhance data integrity. The project enhances the digital design field by delivering a Verilog implementation of a UART communication module that is both dependable and efficient.
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BINDU, MADDI. "Design and Implementation of High-Speed Universal Asynchronous Receiver and Transmitter (UART)." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–9. https://doi.org/10.55041/ijsrem40371.
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The Universal Asynchronous Receiver and Transmitter (UART) are described, which is essentially a serial data transfer protocol used in digital circuit applications. The UART transmitter architecture has a baud rate generator, a parity generator, a transmitter finite state machine (FSM), and a parallel in serial out (PISO) register. The UART receiver is composed of a baud rate generator, a negative edge detector, a parity checker, a receiver Finite State Machine (FSM), and a serial in parallel out (SIPO) register. The transmitter and the receiver have the same baud rate generator; therefore, the transmitter/receiver baud rate is the same. The baud rate generator is the same as the frequency divider circuit. A UART transmitter data frame has 1 start bit, 8 transmit data bits, 1 parity bit, and 1 stop bit. The transmission rate of the transmitter and receiver is 4 Mbps using a 64 MHz system clock. Implementation, simulation and synthesis are done using Xilinx Vivado version 2018.2. The design is verified using a simulated waveform and synthesized on an FPGA Zed board. Keywords: Finite State Machine (FSM), Parallel in Serial out (PISO), Serial in Parallel out (SIPO), FPGA
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Ms. Banti Kumari, Ms. Kanika Jindal, and Mr. Amit Bindal. "Design and Implementation of Verilog Based High Speed Low Power UART." International Research Journal on Advanced Engineering Hub (IRJAEH) 2, no. 05 (2024): 1468–77. http://dx.doi.org/10.47392/irjaeh.2024.0203.
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The most crucial component of serial communication is a microcircuit called a universal asynchronous receiver/transmitter (UART). Receive-transmitter asynchronous technology is known as UART, and it is widely used for device-to-device communication protocols. Using asynchronous serial communication at a speed that can be adjusted. A hardware communication technique called UART Asynchronous conditions occur when the output of the transmitting device and the receiving end are not in sync with a clock. In UART, receiving a signal is known as RxD, and transmitting a signal is known as TxD. In comparison to the existing conventional UART design, we were able to reduce delay by 29% and power usage by 33% using our approach. The effectiveness of the novel UART design is noticed with the reduction in delay and power consumption. Synthesis and simulation are done in Xilinx ISE and Modelsim and Verilog HDL is used to implement a unique UART design.
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Gong, Jiajun, Wenbo Guo, and Weijian Sun. "UART communication protocol frame format explanation and application." Applied and Computational Engineering 14, no. 1 (2023): 47–56. http://dx.doi.org/10.54254/2755-2721/14/20230757.
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Universal Asynchronous Transceiver (UART) is a Universal Serial Data Bus, hardware communication protocol using asynchronous serial communication in a configurable manner rate. In most embedded systems, microcontrollers and computers, UART plays an important communication role as a hardware communication protocol between devices to ensure the efficient transmission of communication data. The understanding and use of the UART protocol is crucial in our design process. In order to better understand. basic principle this protocol and realize the use of URAT, this paper introduces serial communication, UART frame format explanation, the working principle of UART, simulation of simple UART3. Depending on the source clock, also known as the Baud Clock, each heterogeneous device in a complete system may be able to create a distinct baud rate and connect with other devices over a UART interface. The fundamental tenet of the UART protocol stipulates that for proper communication, the transmitter and receiver must be set at the same baud rate. It also introduces several advanced designs and applications of UART with baud rate, namely UART with automatic frequency generator and frequency divider and Determination of UART Receiver Baud Rate Tolerance.
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Dong, Meiting. "A Comparative Analysis of Synchronous USART And Asynchronous UART Communication Protocols." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 567–74. http://dx.doi.org/10.54097/hm6hre11.
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In contemporary applications, the integration of the STM32F103ZET6 microcontroller with various peripherals is indispensable, emphasizing the critical role of serial communication in data transmission between the microcontroller and these peripherals. This study delineates the distinctions between Universal Synchronous Asynchronous Receiver-Transmitter (USART) and Universal Asynchronous Receiver-Transmitter (UART) within the context of USART synchronous communication. The superiority of USART is underscored by its utilization of a uniform clock and identical baud rate for simultaneous and synchronous transmission, enhancing data transfer efficiency significantly. This methodology facilitates the transmission of larger data quantities concurrently and mitigates data loss during prolonged transmission, a prevalent issue in UART asynchronous communication. Additionally, USART preserves essential functionalities such as the detection of data boundaries, automatically discerning the initiation and termination of individual data frames, which guarantees the uninterrupted reception and transmission of data. This analysis is pivotal for professionals seeking optimized communication protocols in microcontroller-based systems.
 In contemporary applications, the integration of the STM32F103ZET6 microcontroller with various peripherals is indispensable, emphasizing the critical role of serial communication in data transmission between the microcontroller and these peripherals. This study delineates the distinctions between Universal Synchronous Asynchronous Receiver-Transmitter (USART) and Universal Asynchronous Receiver-Transmitter (UART) within the context of USART synchronous communication. The superiority of USART is underscored by its utilization of a uniform clock and identical baud rate for simultaneous and synchronous transmission, enhancing data transfer efficiency significantly. This methodology facilitates the transmission of larger data quantities concurrently and mitigates data loss during prolonged transmission, a prevalent issue in UART asynchronous communication. Additionally, USART preserves essential functionalities such as the detection of data boundaries, automatically discerning the initiation and termination of individual data frames, which guarantees the uninterrupted reception and transmission of data. This analysis is pivotal for professionals seeking optimized communication protocols in microcontroller-based systems.
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Li, Zhangchi. "Design, refinement, and enhancement of FPGA-implemented UART circuitry." Applied and Computational Engineering 37, no. 1 (2024): 259–65. http://dx.doi.org/10.54254/2755-2721/37/20230520.
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This article provides an overview of the universal asynchronous receiver/transmitter, commonly referred to as Universal Asynchronous Receiver/Transmitter (UART). The UART stands as a noteworthy exemplar of a serial communication protocol, facilitating the exchange of data within a serial connection while accommodating full-duplex communication. The architecture of the UART hinges upon three principal constituents: the transmitter, the receiver, and the baud rate generator, the latter essentially a frequency divider. Each of these elements is meticulously crafted using the Verilog hardware description language, thereby ensuring distinct and efficient design. Furthermore, this discourse delves into refined iterations of these implementations. For instance, it introduces the concept of a baud rate self-adaptive function and expounds upon multibyte transmission techniques. In a concerted effort to streamline circuit design and curtail the electro circuit's footprint, a deliberate decision is made to forgo the integration of a parity check module. Consequently, the chosen data format is the widely adopted 8N1 (8 data bits, 1 stop bit and no parity bit) configuration.
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Govil, Anchal, Anmol Karnwal, Govinda Sindhu, Ayush Singh, and Dr Shubham Shukla. "Design and Implementation of UART Using FPGA Board." International Journal for Research in Applied Science and Engineering Technology 10, no. 4 (2022): 1187–90. http://dx.doi.org/10.22214/ijraset.2022.41478.
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Abstract: This paper introduces the implementation of the Universal Asynchronous Receiver- Transmitter Controller (UART) based on Microprogrammed Controller on Field Programmable Gate Array (FPGA. Our UART design is fully functional and built-in. Coded using the Verilog design from top to bottom and visible in Spartan-3E FPGA using Xilinx ISE Webpack 14.7. Use results show that the design can work Spartan-3E FPGA maximum clock frequency of 218.248 MHz. The maximum frequent use of the UART controller is 192.773 MHz. of bits and hence this is why with a small amount of storage. Keywords: Receiver, Transmitter, Microprogrammed Controller and Field Programmable Gate Array (FPGA).
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Gopal, P. Bala, and K. Hari Kishore. "An FPGA Implementation of On Chip UART Testing with BIST Techniques." International Journal of Reconfigurable and Embedded Systems (IJRES) 5, no. 3 (2016): 176. http://dx.doi.org/10.11591/ijres.v5.i3.pp176-182.
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A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.
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Sigit Prakosa Adhi Nugraha, Lilo Sunuharjo, and Muhammad 'Atiq. "Komunikasi Arduino I2C, SPI dan UART." Switch : Jurnal Sains dan Teknologi Informasi 2, no. 4 (2024): 80–85. http://dx.doi.org/10.62951/switch.v2i4.187.
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Communication between devices is an important aspect when developing an Arduino-based system. The three communication protocols commonly used with Arduino are I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), and UART (Universal Asynchronous Receiver/Transmitter). Each of these protocols has unique characteristics that make them suitable for different applications. These three communication protocols provide flexible options when developing systems that communicate with sensors, actuators, or other modules on the Arduino platform. Selecting the appropriate protocol depends on specific needs, such as speed, number of connected devices, and system complexity.
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Zhang, Hang. "A Systematic Analysis of The UART Transceiver Theory and Application." Highlights in Science, Engineering and Technology 61 (July 30, 2023): 172–79. http://dx.doi.org/10.54097/hset.v61i.10290.
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This article introduces the theoretical foundation and application of Universal Asynchronous Receiver/Transmitter (UART) in four chapters, including the history and structure of UART transceivers, and so on. UART is a kind of communication hardware using serial Asynchronous communication, which has the advantages of simple structure and good stability. It can convert serial data and parallel data to each other and transmit data between devices. It is widely used on various devices. In the 50 years since its invention, it has undergone many improvements and improvements. In the end, UART transceivers became one of the extremely important hardware in modern electronic technology. At present, UART transceivers are applied in many fields, including healthcare, the Internet of Things, and avionics. Its application in the fields of healthcare and the Internet of Things is of great significance, providing more possibilities for a more convenient life for humanity. Meanwhile, researchers are also attempting to continue improving the transmission speed of UART transceivers and reducing their power consumption.
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Dore, Ms Aruna. "Design and Implementation of UART using Verilog HDL and FPGA." INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 05 (2025): 1–9. https://doi.org/10.55041/ijsrem47124.
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Abstract - This study presents a hardware-based implementation of Universal Asynchronous Receiver Transmitter (UART) communication on the Nexys A7-100T Field Programmable Gate Array (FPGA) platform using Verilog HDL and Vivado Design Suite. UART serves as a fundamental serial communication protocol, widely adopted due to its simplicity and effectiveness. The work details the design methodology, including clock division, baud rate generation, and serial data transmission, while demonstrating successful communication between FPGA and PC. Experimental results confirm reliable and low-power serial data exchange, making this implementation ideal for embedded and communication systems. Keywords UART, FPGA, Serial Communication, Verilog HDL, Nexys A7-100T, Vivado, VLSI, Clock Gating
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Kamath, Akshatha, Tanya Mendez, S. Ramya, and Subramanya G. Nayak. "Design and Implementation of Power-Efficient FSM based UART." Journal of Physics: Conference Series 2161, no. 1 (2022): 012052. http://dx.doi.org/10.1088/1742-6596/2161/1/012052.
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Abstract The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.
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Kong, Lingxi, Qirui Niu, and Pai Yang. "Design And Implementation of UART Based on Verilog HDL." Highlights in Science, Engineering and Technology 38 (March 16, 2023): 949–55. http://dx.doi.org/10.54097/hset.v38i.5981.
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As a two-way transmission channel, Universal Asynchronous Receiver/Transmitter (UART) not only greatly improves the efficiency of information transmission between computers and external devices, but also ensures the accuracy and consistency of information by eliminating metastable state, setting baud rate and other means. In this paper, on the basis of fully understanding the definition and function of UART, based on Verilog HDL language to build UART, and through Modelsim simulation, image and data. The experimental results show that the receiving and sending module of this module works well and meets the requirements of full-duplex serial communication equipment. There is no doubt that the design of this paper has made a more detailed explanation of the basic operating principle of UART, which will contribute to its further development.
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Satyavathi, K. Akhila Naga, D. V. Sowjanya, and Sravya Akula. "High Speed UART Implementation Using VHDL." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (2022): 2109–12. http://dx.doi.org/10.22214/ijraset.2022.44238.
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Abstract: The Universal Asynchronous Receiver and Transmitter (UART) could be a custom designed circuit that allows serial communication between a laptop and a computer peripheral. The complex nature of combined circuit generation has made machine design time consuming at the gate and switch flop levels. As a results of this reality, the style designer made the choice to use hardware description language during the virtual machine layout process. VHDL could be a hardware description language that's accustomed model digital systems. It contains information that you just may find useful. It includes information which will be accustomed explain the virtual machine's behaviour shape, also because the ability to explicitly specify its timing. VHDL could be a difficult and verbose language with many complicated assembles that have complicated semantic meanings and is difficult to grasp initially. The language facilitates hierarchical machine modelling likewise as top don methodologies. It provides an easier method for checking the UART and assisting within the discovery of any discrepancies. It also allows for a more behavioural explanation of the module's characteristics. It makes the look implementation easier to read and understand, and it also provides the flexibility to simply describe dependencies among numerous procedures that arise in complex eventdriven systems. Thus, the layout employs VHDL as a layout language to reap the transmitter module. First, the running version of the transmitter is defined. Then, using VHDL, all of the transmitter's blocks are designed and defined.
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Chavan, Krushna K. "Design and Development of UART Protocol Using Verilog with UVM Testbench." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 05 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem34857.
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This paper's primary goal is to use Verilog (V) to design and validate a full duplex UART module. The Universal Asynchronous Receiver/Transmitter, or UART, is a two-way transmission channel that not only significantly increases the efficiency of information transfer between computers and external devices but also guarantees information accuracy and consistency through the use of baud rate settings, the elimination of metastable state, and other techniques. In this work, the definition and operation of UART are well understood, and the UART is constructed using the Verilog HDL language, EDA simulation, picture, and data. The findings of the experiment demonstrate that this module's sending and receiving module functions well and satisfies the specifications of full-duplex serial communication equipment. Without a doubt, the layout of this paper has made the fundamental working concept of UART more clearly explained, which will aid in its future. Key Words:- UART, EDA , BRG, IC, DUT, UVM
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Sarmad, K. Ibrahim, M. Hathal Hussein, and A. Abdulhussein Riyadh. "Baud rate variations effect on virtual channel based on PIC microcontroller." TELKOMNIKA Telecommunication, Computing, Electronics and Control 17, no. 6 (2019): 2755–63. https://doi.org/10.12928/TELKOMNIKA.v17i6.12828.
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Recent year in the world the real applications, usually needed only a few key features of Universal Asynchronous Receiver Transmitter (UART). It is a type of serial communication protocol, which improves the problem of parallel communication and develops effectively in several services. This paper presents a transceiver system based on PIC microcontroller. It also presents software designs to transmit and receive data through the virtual channel. The system is designed to study the effects of baud rate variations between transmitter and receiver for noise and noiseless AWGN channel. The system has been simulated by Proteus simulator version 8.1, and then tested successfully at baud rates (2400, 4800, 9600, and 19200) bps. Simulation results show that the error rate has zero values at the desired baud rate value, and also, at the adjacent values. Thus, the zero level of error rate is increased by increasing baud rate values, which fixed by the transmitter and vice versa.
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Gorabal, Amrutha, and Nayana D K. "FPGA Implementation of UART with Single Error Correction and Double Error Detection (UART-SEC-DED)." International Journal of Engineering & Technology 7, no. 3.12 (2018): 23. http://dx.doi.org/10.14419/ijet.v7i3.12.15856.
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The Universal Asynchronous Receiver Transmitter (UART) is the very simple and significant sequential communication protocol which is basically utilized for microprocessors & microcontroller systems. It is a shorter range communication protocol, which able to perform half-duplex and full-duplex type of communication at baud rates. Though, UART is a type of shorter range communication still they are not resistant to noisy channel which leads to communication errors by flipping or loosing of bits. These kinds of signal errors are named as forward-errors. The correction of forward errors is a mechanism to handle and rectify those errors (i.e. Burst errors and Random bits error). Thus in this methodology, have introduced a UART-SEC-DED communication module design which utilizes the Hamming encoder and decoders to achieve the forward error correction. Finally, the proposed system will simulated and implemented on FPGA board and experimental outcomes shows the better efficiency in single error correction and detection of double errors.
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Muhammad, Ramdhan MS, Ali Muhammad, Eberechukwu N. Paulson, Effiyana G. Nurzal, Ali Samura, and MY Kamaludin. "An Early Drowning Detection System for Internet of Things (IoT) Applications." TELKOMNIKA Telecommunication, Computing, Electronics and Control 16, no. 4 (2018): 1870–76. https://doi.org/10.12928/TELKOMNIKA.v16i4.9046.
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Drowning is the leading cause of injury or death for children and teenagers. Designing a drowning detection device by implementing an Internet of Thing (IoT) is needed. An Early Drowning Detection System (EDDS) is a system that gives an early alarm to the guardians (parents and lifeguard) if the detector triggered an abnormal heartbeat and the victims are submerged under the water for a long time. A microcontroller was used to control the signal received from a pulse sensor and time for the signal lost under the water before it is transmitted to the access point. The access point acts as a data forwarding to the database via an internet connection. Universal Asynchronous Receiver/Transmitter (UART) 433MHz radio frequency transceiver has been used to create the wireless communication between drowning detection device and monitoring hub. A triggered warning signal will be transmitted to the guardians via Android apps and web page.
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Huang, Yichen, Hao Lin, and Di Zhang. "Analysis of the baud rate of the UART to affects the data." Highlights in Science, Engineering and Technology 61 (July 30, 2023): 200–205. http://dx.doi.org/10.54097/hset.v61i.10295.
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This article explores the impact of different baud rates on Universal Asynchronous Receiver/Transmitter (UART) asynchronous serial communication. It discusses the frame format and calculation method of baud rate error, as well as the main reasons for error, such as clock error, sampling error, line noise, data bit error, and software delay. To ensure reliable communication, it is essential to test and debug the actual baud rate and adjust it accordingly. The study found that higher expected baud rates resulted in higher baud rate errors, affecting transmission distance, speed, reliability, and system complexity. The appropriate baud rate should be selected based on specific application scenarios and requirements. Higher baud rates are needed for high-speed transmissions, while lower baud rates are required for long transmission distances or high reliability requirements. However, further research is needed to determine the impact of unallocated baud rates on data. Overall, this article provides valuable insights into the development of UART.
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Talapala, Lakshmi Prasanna, Siddaiah Nalluri, Murali Krishna Boppana, and Rao Valluri Maheswara. "Implementation of the advanced encryption standard algorithm on an FPGA for image processing through the universal asynchronous receiver-transmitter protocol." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 6 (2022): 6114–22. https://doi.org/10.11591/ijece.v12i6.pp6114-6122.
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Communication among end users can be based either on wired or wireless technology. Cryptography plays a vital role in ensuring data exchange is secure among end users. Data can be encrypted and decrypted using symmetric or asymmetric key cryptographic techniques to provide confidentiality. In wireless technology, images are exchanged through low-cost wireless peripheral devices, such as radio frequency identification device (RFID), nRF, and ZigBee, that can interface with field programmable gate array (FPGA) among the end users. One of the issues is that data exchange through wireless devices does not offer confidentiality, and subsequently, data can be lost. In this paper, we propose a design and implementation of AES-128 cipher algorithm on an FPGA board for image processing through the universal asynchronous receiver transmitter (UART) protocol. In this process, the advanced encryption standard (AES) algorithm is used to encrypt and decrypt the image, while the transmitter and receiver designs are implemented on two Xilinx BASYS-3 circuits connected with a ZigBee RF module. The encrypted image uses less memory, such as LUTs (141), and also consumes less chip power (0.0291 w), I/O (0.003), block RAM (0.001 w), data, and logic to provide much higher efficiency than wired communication technology. We also observe that images can be exchanged through the UART protocol with different baud rates in run time.
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Zhang, Xiaowen. "Design and implementation of UART receiving module based on FPGA." Applied and Computational Engineering 14, no. 1 (2023): 81–85. http://dx.doi.org/10.54254/2755-2721/14/20230768.
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In modern electronic systems, data transmission is an essential requirement within and between boards, or between lower and upper computers. To ensure data transmission accuracy, communication protocols are established that must be followed by all parties involved. These protocols include UART (universal asynchronous transmitter and receiver), IIC (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), USB2.0/3.0(Universal Serial Bus), and Ethernet. Among these protocols, UART is the most basic one and is widely used in embedded devices due to its simple circuit structure and low cost. With the exponential growth of information technology, UART-based embedded devices can easily achieve wired and wireless communication through various communication interfaces and wireless modules. In this paper, the author presents an example of a receiving module for UART communication that converts parallel data into string data. The entire module is developed using the hardware description language Verilog HDL. Simulations are performed using ModelSim, and the results demonstrate that the simulation waveform is consistent with the expected receiving data. This approach facilitates the transformation of serial data to parallel data, improving the efficiency and accuracy of data transmission.
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Hung, San Shan, Hsing Cheng Chang, and Yu Hsuan Lin. "Applying Wireless Transmission for Aluminum Alloy Wheel Cornering Simulation and Testing." Advanced Materials Research 753-755 (August 2013): 2383–89. http://dx.doi.org/10.4028/www.scientific.net/amr.753-755.2383.
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This study adopted finite element analysis (FEA) to conduct tests and simulations on the bending moment of truck wheels. Based on the simulated analysis using ANSYS Workbench software, a three-axis strain gauge was attached to locations with substantial stress variations. The strain gauge was converted into voltage. Amplification and filtering circuits were adopted for signal processing, and the processed signals were subsequently entered into the microcontroller unit. Simultaneously, a universal asynchronous receiver/transmitter (UART) communications protocol was applied for communication with the Bluetooth wireless module. The accessed signal was then transmitted to the receiver end through wireless emission. The detection interface at the monitoring end was designed using LabVIEW software, enabling operators to observe the stress and strain for wheels under various test conditions. The acquired data were stored in a computer for future reviews and analysis.
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Shao, Ziyi. "An FPGA-Based Adaptive Solution for Synchronous Configuration in UART Communication." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 615–22. http://dx.doi.org/10.54097/hcjhsh19.
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To address the challenges associated with data reception failures, which arise due to abrupt alterations in the baud rate and the data format of the transmission signal in traditional Universal Asynchronous Receiver-Transmitter (UART) scenarios, this study presents an adaptive UART parameter solution underpinned by Field-Programmable Gate Array (FPGA) technology. Initially, this manuscript elucidates the underlying principles of UART communication and delineates the pivotal constituents of the UART protocol. Subsequently, it offers an in-depth analysis, from the transmission perspective, of how specific parameters influence the effectiveness of the UART protocol. Based on the software and hardware embodiments associated with the dual primary functions – baud rate adaptation and data format adaptation – this paper extensively details the flow chart for baud rate adaptation, the circuitry for edge detection, methodologies for baud rate computation, and the parameter eigenvalue approach. Following this, Verilog, a hardware description language, is employed for coding and subsequent simulation within the Quartus II environment. Empirical evidence corroborates the efficacy of the proposed design in achieving synchronous configuration between the baud rate and the data format. The findings of this research bear substantial implications for augmenting both the adaptability and dependability of UART communication systems.
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Zhao, Xue Mei. "Realization of Serial Port Expansion Circuit." Applied Mechanics and Materials 271-272 (December 2012): 1597–601. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.1597.
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This article describes the design of a interface chip with serial port expansion circuit of computer in industrial applications. It is used to connect with 422 and RS232 interfaces. Circuits involved several major chip such as the interface of 422 and RS232 and UART(Universal Asynchronous Receiver Transmitter)16C550 Inside the computer. Paper describes the composition of the hardware circuit, theory and implementation and initialization programming of URAT interface chip. We use interface chip with the FIFO to the circuit, It improves the efficiency of the application software, And it solves the problem of insufficient of computer serial port.
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Prasanna, Talapala Lakshmi, Nalluri Siddaiah, Boppana Murali Krishna, and Maheswara Rao Valluri. "Implementation of the advanced encryption standard algorithm on an FPGA for image processing through the universal asynchronous receiver-transmitter protocol." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 6 (2022): 6114. http://dx.doi.org/10.11591/ijece.v12i6.pp6114-6122.
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<span lang="EN-US">Communication among end users can be based either on wired or wireless technology. Cryptography plays a vital role in ensuring data exchange is secure among end users. Data can be encrypted and decrypted using symmetric or asymmetric key cryptographic techniques to provide confidentiality. In wireless technology, images are exchanged through low-cost wireless peripheral devices, such as radio frequency identification device (RFID), nRF, and ZigBee, that can interface with field programmable gate array (FPGA) among the end users. One of the issues is that data exchange through wireless devices does not offer confidentiality, and subsequently, data can be lost. In this paper, we propose a design and implementation of AES-128 cipher algorithm on an FPGA board for image processing through the <a name="_Hlk107307233"></a>universal asynchronous receiver transmitter (UART) protocol. In this process, the advanced encryption standard (AES) algorithm is used to encrypt and decrypt the image, while the transmitter and receiver designs are implemented on two Xilinx BASYS-3 circuits connected with a ZigBee RF module. The encrypted image uses less memory, such as LUTs (141), and also consumes less chip power (0.0291 w), I/O (0.003), block RAM (0.001 w), data, and logic to provide much higher efficiency than wired communication technology. We also observe that images can be exchanged through the UART protocol with different baud rates in run time.</span>
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Haripriya, D., Keshav Kumar, Anurag Shrivastava, Hamza Mohammed Ridha Al-Khafaji, Vishal Moyal, and Sitesh Kumar Singh. "Energy-Efficient UART Design on FPGA Using Dynamic Voltage Scaling for Green Communication in Industrial Sector." Wireless Communications and Mobile Computing 2022 (May 5, 2022): 1–9. http://dx.doi.org/10.1155/2022/4336647.
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In the present scheme of the world, the problem of shortage of power is seen across the world which can be a vulnerability to various communication securities. The scope of proposed research is that it is a step towards completing green communication technology concepts. In order to improve energy efficiency in communication networks, we designed UART using different nanometers of FPGA, which consumes the least amount of energy. This shortage is happening because of expanding of industries across the world and the rapid growth of the population. Therefore, to save the power for our upcoming generation, the globe is moving towards the concept and ideas of green communication and power-/energy-efficient gadget. In this work, a power-efficient universal asynchronous receiver transmitter (UART) is implemented on 28 nm Artix-7 field-programmable gate array (FPGA). The objective of this work is to reduce the power utilization of UART with the FPGA device in industries. To do this, the same authors have used voltage scaling techniques and compared the results with the existing FPGA works.
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Ann, Zenna Sajan, and R. Gnana King G. "Wireless Speed Control of Vehicles with Detection of Person & Zebra Crossing." International Journal of Recent Technology and Engineering (IJRTE) 10, no. 2 (2021): 61–67. https://doi.org/10.35940/ijrte.B6116.0710221.
Full textAbstract:
Pedestrians crossing zebra lines are one of the major concerns for road accidents. Nowadays, the number of road accidents increases due to careless driving and pedestrian motions at crosswalks. It is necessary to detect both person and zebra crossings properly and control vehicle speed accordingly. Here in this paper, a suitable solution that improves both detections can be introducing. Here used the TensorFlow Single Shot Detection (SSD) model is the best and most convenient trained model for Zebra line and person detection. A database is taking for the analysis. The input image could process as a crosswalk detection, which has more used for zebra crossing identification via the SSD model. Suppose detected the person and zebra crossings were at the same time. In that case, it will perform commands such as run, slow down, stop, horn, etc., with the help of wireless serial communication Universal Asynchronous Receiver-Transmitter. A Bluetooth command signal matches UART, which provides the vehicle with the necessary control inputs to execute the prescribed topology properly. Simultaneous detection of pedestrians at zebra crossings is a critical factor. It results most efficiently and to identify the person detection.
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Zhuang, Chenyu. "Comparison And Selection of Commonly Used Communication Protocols in Measurement and Control Instruments." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 540–46. http://dx.doi.org/10.54097/em4syb59.
Full textAbstract:
In the contemporary landscape of economic globalization, the salience of the field of measurement and control has progressively intensified. Simultaneously, the utilization of serial bus technology within instrumentation has witnessed a considerable proliferation. Consequently, the judicious selection of an appropriate serial bus protocol has assumed paramount importance. It is incumbent upon practitioners to consider diverse factors, including the communication principles, performance attributes, and interfacing requirements, when making their choice, to ensure the efficacious and stable operation of their systems. This investigation employs a methodology that amalgamates a comprehensive literature review with experimental comparative analyses to ascertain the optimal suitability of Universal Asynchronous Receiver/Transmitter (UART), Inter-Integrated Circuit (I2C), and Serial Peripheral Interface (SPI) communication protocols across distinct application scenarios. Subsequent to a thorough comparative scrutiny, this study ultimately elucidates the respective merits and demerits of the UART, I2C, and SPI communication protocols, in tandem with their most judicious application contexts. This research endeavor serves to furnish engineers with valuable insights for the judicious selection of serial bus protocols.
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Odubanjo, Oduwole Funmilade, Peter Babatunde, Tolulope Olaide Aluko, Oluwaseyi Emmanuel Jimoh, and Timileyin Philip Adebayo. "Embedded Communication System in a Local Meteorological Station in Lagos, Nigeria." European Journal of Engineering Research and Science 2, no. 11 (2017): 1. http://dx.doi.org/10.24018/ejers.2017.2.11.496.
Full textAbstract:
Effective communication among units of a system is very essential because it determines the reliability of such a system. A local meteorological station has a target of atmospheric data acquisition, processing and output hence it is an embedded system with different units. Embedded communication among these units was facilitated and made effective by ESP8266 microcontroller a 32-bit Tensilica L106 running at 80MHz system clock equipped with 802.11 IEEE standard Wi-Fi protocols such as TCP/IP stacks. Full duplex data communication was adopted between the Access point server (station mode) and the client mode. The ESP8266 (station) reads all the sensors attached to it identifies the MAC (Media Access Control) address of the clients before processing its request. The data transmission between the client and the server (station) is through HTTP application. Universal Asynchronous Receiver Transmitter (UART) communication was implemented on the ESP8266 client sending the received data to the user computer. The computer uses RS232 logic while the ESP8266 uses TTL logic. USB/UART Bridge, FTD232 IC was adopted to connect ESP8266 with the output device (computer). The data received was viewed on the personal computer. These embedded communication routes and connections were adopted in a local meteorological station in Lagos.
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Odubanjo, Oduwole Funmilade, Peter Babatunde, Tolulope Olaide Aluko, Oluwaseyi Emmanuel Jimoh, and Timileyin Philip Adebayo. "Embedded Communication System in a Local Meteorological Station in Lagos, Nigeria." European Journal of Engineering and Technology Research 2, no. 11 (2017): 1–4. http://dx.doi.org/10.24018/ejeng.2017.2.11.496.
Full textAbstract:
Effective communication among units of a system is very essential because it determines the reliability of such a system. A local meteorological station has a target of atmospheric data acquisition, processing and output hence it is an embedded system with different units. Embedded communication among these units was facilitated and made effective by ESP8266 microcontroller a 32-bit Tensilica L106 running at 80MHz system clock equipped with 802.11 IEEE standard Wi-Fi protocols such as TCP/IP stacks. Full duplex data communication was adopted between the Access point server (station mode) and the client mode. The ESP8266 (station) reads all the sensors attached to it identifies the MAC (Media Access Control) address of the clients before processing its request. The data transmission between the client and the server (station) is through HTTP application. Universal Asynchronous Receiver Transmitter (UART) communication was implemented on the ESP8266 client sending the received data to the user computer. The computer uses RS232 logic while the ESP8266 uses TTL logic. USB/UART Bridge, FTD232 IC was adopted to connect ESP8266 with the output device (computer). The data received was viewed on the personal computer. These embedded communication routes and connections were adopted in a local meteorological station in Lagos.
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Harouna Maloum, Abdoul Moumouni, Nicasio Maguu Muchuka, and Cosmas Raymond Mutugi Kiruki. "FPGA-base object tracking: integrating deep learning and sensor fusion with Kalman filter." Indonesian Journal of Electrical Engineering and Computer Science 34, no. 2 (2024): 888. http://dx.doi.org/10.11591/ijeecs.v34.i2.pp888-899.
Full textAbstract:
This research presents an integrated approach for object detection and tracking in autonomous perception systems, combining deep learning techniques for object detection with sensor fusion and field programmable gate array (FPGA-based) hardware implementation of the Kalman filter. This approach is suitable for applications like autonomous vehicles, robotics, and augmented reality. The study explores the seamless integration of pre-trained deep learning models, sensor data from a depth camera, real-sense D435, and FPGA-based Kalman filtering to achieve robust and accurate 3D position and 2D size estimation of tracked objects while maintaining low latency. The object detection and feature extraction are implemented on a central processing unit (CPU), and the Kalman filter sensor fusion with universal asynchronous receiver transmitter (UART) communication is implemented on a Basys 3 FPGA board that performs 8 times faster compared to the software approach. The experimental result provides the hardware resource utilization of about 29% of look-up tables, 6% of lookup table RAMs (LUTRAM), 15% of Flip-flops, 32% of Block-RAM, 38% of DSP blocks operating at 100 MHz, and 230400 baud rates for the UART. The whole FPGA design executes at 2.1 milliseconds, the Kalman filter executes at 240 microseconds, and the UART at 1.86 milliseconds.
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Maloum, Abdoul Moumouni Harouna, Nicasio Maguu Muchuka, and Cosmas Raymond Mutugi Kiruki. "FPGA-base object tracking: integrating deep learning and sensor fusion with Kalman filter." Indonesian Journal of Electrical Engineering and Computer Science 34, no. 2 (2024): 888–99. https://doi.org/10.11591/ijeecs.v34.i2.pp888-899.
Full textAbstract:
This research presents an integrated approach for object detection and tracking in autonomous perception systems, combining deep learning techniques for object detection with sensor fusion and field programmable gate array (FPGA-based) hardware implementation of the Kalman filter. This approach is suitable for applications like autonomous vehicles, robotics, and augmented reality. The study explores the seamless integration of pre-trained deep learning models, sensor data from a depth camera, real-sense D435, and FPGA-based Kalman filtering to achieve robust and accurate 3D position and 2D size estimation of tracked objects while maintaining low latency. The object detection and feature extraction are implemented on a central processing unit (CPU), and the Kalman filter sensor fusion with universal asynchronous receiver transmitter (UART) communication is implemented on a Basys 3 FPGA board that performs 8 times faster compared to the software approach. The experimental result provides the hardware resource utilization of about 29% of look-up tables, 6% of lookup table RAMs (LUTRAM), 15% of Flip-flops, 32% of Block-RAM, 38% of DSP blocks operating at 100 MHz, and 230400 baud rates for the UART. The whole FPGA design executes at 2.1 milliseconds, the Kalman filter executes at 240 microseconds, and the UART at 1.86 milliseconds.
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Lee, Sang Sik, Ki Young Shin, and Joung H. Mun. "Development of a Portable and Wireless Surface EMG." Key Engineering Materials 321-323 (October 2006): 1107–10. http://dx.doi.org/10.4028/www.scientific.net/kem.321-323.1107.
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The objective of this study was to develop a portable, wireless surface EMG of a noninvasive type. The limitations of the existing system include its large size and the necessity of a wire. Therefore, this study focused on the development of a portable and wireless type of EMG. The developed EMG, which has 10 channels, is composed of an electrode for the measurement of the EMG signal, a preamplifier for initial processing, a second amplifier, an A/D converter, and a Bluetooth module for wireless communication. The communication of the developed EMG used a UART (Universal Asynchronous serial Receiver and Transmitter) and Bluetooth protocols. The rate of serial communication was set to 723kbps. This system is able to obtain 2,000 Hz in each channel. The data transfer success rate of the developed EMG is 100%.
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Zhao, Xue Jin, Zhu Qing Liu, Tian Liang Hu, and Cheng Rui Zhang. "Design of a High-Speed Reconfigurable Serial Fieldbus with Reliable Communication Based on FPGA." Advanced Materials Research 490-495 (March 2012): 2125–30. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2125.
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This paper present a high-speed reconfigurable serial fieldbus (HRSFB) used for industry communication with baud rate up to 10Mbps and reliable communication. We developed this fieldbus based on UART (Universal Asynchronous Receiver/Transmitter) and practice it on FPGA. By using hardware programming on FPGA, we can get the high speed and make the bus reconfigurable easily. This fieldbus system includes one main node and up to 255 sub nodes, and all the nodes can automatically identified and configured at the beginning of the system which makes the field bus system shrink or expand easily. Also hardware CRC technology and ask/answer mode are used in the communication protocol to guarantee the security of the communication. This bus has been widely used in many fields, like PLC controller, CNC machine controller, data acquisition system and so on.
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Loose, Felipe, Juan Ramón Garcia-Meré, Adrion Andrei Rosanelli, et al. "A Case Study on the Integration of Powerline Communications and Visible Light Communications from a Power Electronics Perspective." Sensors 24, no. 20 (2024): 6627. http://dx.doi.org/10.3390/s24206627.
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This paper presents a dual-purpose LED driver system that functions as both a lighting source and a Visible Light Communication (VLC) transmitter integrated with a Powerline Communication (PLC) network under the PRIME G3 standard. The system decodes PLC messages from the powerline grid and transmits the information via LED light to an optical receiver under a binary phase shift keying (BPSK) modulation. The load design targets a light flux of 800 lumens, suitable for LED light bulb applications up to 10 watts, ensuring practicality and energy efficiency. The Universal Asynchronous Receiver-Transmitter (UART) module enables communication between the PLC and VLC systems, allowing for an LED driver with dynamic control and real-time operation. Key signal processing stages are commented and developed, including a hybrid buck converter with modulation capabilities and a nonlinear optical receiver to regenerate the BPSK reference signal for VLC. Results show a successful prototype working under a laboratory environment. Experimental validation shows successful transmission of bit streams from the PLC grid to the VLC setup. A design guideline is presented in order to dictate the design of the electronic devices involved in the experiment. Finally, this research highlights the feasibility of integrating PLC and VLC technologies, offering an efficient and cost-effective solution for data transmission over existing infrastructure.
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Sun, Xun. "Bidirectional Multi-Device Daisy Chain Communication Architecture and Verification Based on UART Serial Communication Protocol." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 583–91. http://dx.doi.org/10.54097/tjz7j294.
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This paper proposes an innovative bidirectional multi-device daisy chain communication framework grounded in the Universal Asynchronous Receiver-Transmitter (UART) serial communication protocol. This intricate architecture employs four distinct physical Input/Output (IO) interfaces to facilitate dynamic serial communication amongst multiple devices. These devices can be conjoined in a sequential daisy chain or in a closed-loop ring configuration. To further enhance the functionality, our system incorporates a unique mechanism that leverages randomized device codes for rapid address allocation. This not only facilitates directional communication but also supports broad-spectrum broadcast transmissions. An exhaustive simulation of the said protocol was carried out utilizing Proteus software in tandem with a Microcontroller Unit (MCU) model. Critical parameters such as communication response delay, the cumulative failure rate of transmissions, and the isolated failure rate of individual data packets between nodes were meticulously evaluated. Preliminary findings underscore the protocol's potential in fostering cost-effective and dependable communication amongst a plethora of devices. The practicality and versatility of this system manifest prominently in arenas like cluster robot command, robotic automation, and holistic environmental monitoring.
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Ebrahimi, Hassan, and Hans G. Kerkhoff. "A Digital On-Line Monitor for Detecting Intermittent Resistance Faults at Board Level." Journal of Circuits, Systems and Computers 28, supp01 (2019): 1940003. http://dx.doi.org/10.1142/s0218126619400036.
Full textAbstract:
The reliability of board-level data communications intensively depends on the reliability of interconnections on a board. One of the most challenging interconnections reliability threats is intermittent resistive faults (IRFs). Detecting such faults is a major challenge. The main reason is the random behavior of these faults. They may occur randomly in time, duration and amplitude. The occurrence rate can vary from a few nanoseconds to months. This paper investigates IRF detection at the board level by introducing a new digital in situ IRF monitor. Hardware-based fault injection has been used to validate the proposed IRF monitor. As case studies, two widely used on-board transmission protocols namely the Universal Asynchronous Receiver Transmitter (UART) and the Serial Peripheral Interface bus (SPI), have been used. In addition, one fault management framework, based on the IJTAG standard, has been implemented to collect and characterize information from the monitors. The experimental results show that the proposed monitor is effective in detecting IRFs at the board level.
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Nguyen, Van-Khanh, Vy-Khang Tran, Hai Pham, Van-Muot Nguyen, Hoang-Dung Nguyen, and Chi-Ngon Nguyen. "A multi-microcontroller-based hardware for deploying Tiny machine learning model." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 5 (2023): 5727. http://dx.doi.org/10.11591/ijece.v13i5.pp5727-5736.
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<span lang="EN-US">The tiny machine learning (TinyML) has been considered to applied on the edge devices where the resource-constrained micro-controller units (MCUs) were used. Finding a good platform to deploy the TinyML effectively is very crucial. The paper aims to propose a multiple micro-controller hardware platform for productively running the TinyML model. The proposed hardware consists of two dual-core MCUs. The first MCU is utilized for acquiring and processing input data, while the second is responsible for executing the trained TinyML network. Two MCUs communicate to each other using the universal asynchronous receiver-transmitter (UART) protocol. The multi-tasking programming technique is mainly applied on the first MCU to optimize the pre-processing new data. A three-phase motors faults classification TinyML model was deployed on the proposed system to evaluate the effectiveness. The experimental results prove that our proposed hardware platform was improved 34.8% the total inference time including pre-processing data of the proposed TinyML model in comparing with single micro-controller hardware platform.</span>
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Nguyen, Van-Khanh, Vy-Khang Tran, Hai Pham, Van-Muot Nguyen, Hoang-Dung Nguyen, and Chi-Ngon Nguyen. "A multi-microcontroller-based hardware for deploying Tiny machine learning model." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 5 (2023): 5727–36. https://doi.org/10.11591/ijece.v13i5.pp5727-5736.
Full textAbstract:
The tiny machine learning (TinyML) has been considered to apply on the edge devices where the resource-constrained micro-controller units (MCUs) were used. Finding a good platform to deploy the TinyML effectively is very crucial. The paper aims to propose a multiple micro-controller hardware platform for productively running the TinyML model. The proposed hardware consists of two dual-core MCUs. The first MCU is utilized for acquiring and processing input data, while the second one is responsible for executing the trained TinyML network. Two MCUs communicate with each other using the universal asynchronous receiver-transmitter (UART) protocol. The multitasking programming technique is mainly applied on the first MCU to optimize the pre-processing new data. A three-phase motors faults classification TinyML model was deployed on the proposed system to evaluate the effectiveness. The experimental results prove that our proposed hardware platform was improved 34.8% of the total inference time including pre-processing data of the proposed TinyML model in comparing with single micro-controller hardware platform.
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Odirichukwu, J.C. "Embedded Phone Call Based Burglary Security Alert System." Journal of Embedded Systems and Processing 4, no. 1 (2019): 24–30. https://doi.org/10.5281/zenodo.2622387.
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<em>The importance of security in our society cannot be overemphasised, as it drives economic growth. This research reviewed the problems associated with embedded alarm systems together with other embedded security system like SMS based security system. In this paper, Embedded Phone Call Burglary Security Alert System was developed which calls the house owner on detection of an intruder, so that adequate security measures may be taken to catch the burglar. It is implemented to be used with any kind of mobile phones. Also, adequate security measures can be taken by the appropriate agencies to apprehend the intruder/burglar. The system was built using Atmega32 microcontroller, GSM/GPRS modem, infra-red sensor and proximity sensors and Embedded Basic/programming. The proximity sensor is placed to sense the door and window entrance while the infrared is placed to have line of sight communication in order to capture intrusion from the ceilings. SIM900 Module is a cellular protocol that interoperates with a Universal Asynchronous Receiver and Transmitter (UART) onboard communication protocol.</em>
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Patil, Trupti, and Anuradha M. Sandi. "Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA." International Journal of Reconfigurable and Embedded Systems (IJRES) 13, no. 2 (2024): 296. http://dx.doi.org/10.11591/ijres.v13.i2.pp296-306.
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The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.
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Sajan, Ann Zenna, and G. R. Gnana King. "Wireless Speed Control of Vehicles with Detection of Person & Zebra Crossing." International Journal of Recent Technology and Engineering (IJRTE) 10, no. 2 (2021): 61–67. http://dx.doi.org/10.35940/ijrte.b6116.0710221.
Full textAbstract:
Pedestrians crossing zebra lines are one of the major concerns for road accidents. Nowadays, the number of road accidents increases due to careless driving and pedestrian motions at crosswalks. It is necessary to detect both person and zebra crossings properly and control vehicle speed accordingly. Here in this paper, a suitable solution that improves both detections can be introducing. Here used the TensorFlow Single Shot Detection (SSD) model is the best and most convenient trained model for Zebra line and person detection. A database is taking for the analysis. The input image could process as a crosswalk detection, which has more used for zebra crossing identification via the SSD model. Suppose detected the person and zebra crossings were at the same time. In that case, it will perform commands such as run, slow down, stop, horn, etc., with the help of wireless serial communication Universal Asynchronous Receiver-Transmitter. A Bluetooth command signal matches UART, which provides the vehicle with the necessary control inputs to execute the prescribed topology properly. Simultaneous detection of pedestrians at zebra crossings is a critical factor. It results most efficiently and to identify the person detection.
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Pangestu, Agung, Maulana Aziz Assuja, Maulana Aziz Assuja, Try Susanto, and Try Susanto. "PENGEMBANGAN FIRMWARE PADA SUB CONTROLLER ROBOT SEPAK BOLA HUMANOID MENGGUNAKAN PROTOKOL DYNAMIXEL 2.0." Jurnal Teknik dan Sistem Komputer 3, no. 2 (2023): 104–17. http://dx.doi.org/10.33365/jtikom.v3i2.2357.
Full textAbstract:
Firmware merupakan lapisan perangkat lunak antara perangkat keras dan sistem operasi dengan tujuan utama menginisialisasi perangkat keras, sehingga sistem operasi dan driver dapat mengkonfigurasi perangkat keras. Penelitian ini bertujuan mengembangkan firmware yang ada pada Krakatau Sub-Controller menggunakan protokol Dynamixel 2.0. Protokol Dynamixel adalah protokol komunikasi half-duplex UART (Universal Asynchronous Receiver-Transmitter) dengan panjang 8-bit data, 1 stop bit, dan none paritas. Tahapan penelitan yang akan dilakukan yaitu merancang dan mengimplementasikan board Krakatau Sub Controller Versi 2.0. Langkah selanjutnya yaitu aturan yang ada pada Protokol Dynamixel 2.0 diterjemahkan dalam bahasa pemrograman C++ dan ditanam ke Krakatau Sub Controller sebagai firmware. Skenario pengujian yang dilakukan yaitu pengujian fungsional dengan mengirim nilai bit dari tiap-tiap instruction dan pengujian non fungsional dengan menguji aspek latensi. Firmware pada Krakatau Sub-Controller berhasil dibuat dengan latensi waktu yang dibutuhkan untuk pengujian Ping yaitu 12 µS, pengujian Read yaitu 114 µS, pengujian Write yaitu 11 µS, pengujian Reg Write yaitu 7 µS, pengujian Action yaitu 9 µS, pengujian Factory Reset yaitu 14 µS, pengujian Reboot yaitu 16 µS, pengujian Clear yaitu 3 µS, pengujian Sync Read yaitu 6 µS, Pengujian Bulk Read yaitu 17 µS
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Pradip, Ram Selokar, and T. Karule P. "Security Enhancement in Networked Embedded System." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1867–73. https://doi.org/10.11591/ijece.v7i4.pp1867-1873.
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In the developed system ARM9 is a master and Two ARM7s are slaves. The peripherals are being controlled by two ARM7 boards. The Peripherals are connected to the ARM7 through Complex Programmable Logic Device (CPLD). The CPLD is in turn connected to the ARM7 using Serial Peripheral Interface (SPI). The ARM7 boards collect the information from the peripherals and send it to the ARM9 board. The communication between ARM7 and ARM9 is via UART (Universal Asynchronous Receiver Transmitter) over CAN (Controller Area Network). The ARM9 board has got the software intelligence. The ARM9 behaves as a master and two ARM7 boards behave as slaves. Being master ARM9 passes tokens to ARM7 which in turn returns (Acknowledges) the token. The ARM9 is further connected to Proxy via Ethernet. The proxy is further connected to the service platform (server) via Ethernet. So subsequently any decisions at any stage can be changed at server level. Further these commands can be passed on to ARM9 which in turn controls the peripherals through ARM7. (a) The system which we have developed consists of ARM9 as a master, Two ARM7 as Slaves. The communication between ARM9-ARM7 is via UART over a CAN, (b) Each ARM7 further communicates serially (RS232) with the two 8051 Microcontroller nodes, (c)Thus a networked Embedded System is developed wherein the serial data is brought over Ethernet. The ARM7 board, which is directly linked with the peripherals, can be modified of its functionality as and when required. The functionality of ARM7 can be modified by upgrading its firmware. To upgrade the firmware same communication link has been used. ARM7 receives the new firmware via same ARM9-ARM7 communication link. The Flash Write operation is performed using the source code to write the new firmware. Bootloader application for the ARM7 has been developed. The signature has been incorporated to assure authenticity of the new Firmware. Intel Hex File Format is used to parse the hex file.
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Tambaro, Mattia, Marta Bisio, Marta Maschietto, Alessandro Leparulo, and Stefano Vassanelli. "FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings." Digital 1, no. 1 (2021): 34–53. http://dx.doi.org/10.3390/digital1010003.
Full textAbstract:
Numerous experiments require low latencies in the detection and processing of the neural brain activity to be feasible, in the order of a few milliseconds from action to reaction. In this paper, a design for sub-millisecond detection and communication of the spiking activity detected by an array of 32 intracortical microelectrodes is presented, exploiting the real-time processing provided by Field Programmable Gate Array (FPGA). The design is embedded in the commercially available RHS stimulation/recording controller from Intan Technologies, that allows recording intracortical signals and performing IntraCortical MicroStimulation (ICMS). The Spike Detector (SD) is based on the Smoothed Nonlinear Energy Operator (SNEO) and includes a novel approach to estimate an RMS-based firing-rate-independent threshold, that can be tuned to fine detect both the single Action Potential (AP) and Multi Unit Activity (MUA). A low-latency SD together with the ICMS capability, creates a powerful tool for Brain-Computer-Interface (BCI) closed-loop experiments relying on the neuronal activity-dependent stimulation. The design also includes: A third order Butterworth high-pass IIR filter and a Savitzky-Golay polynomial fitting; a privileged fast USB connection to stream the detected spikes to a host computer and a sub-milliseconds latency Universal Asynchronous Receiver-Transmitter (UART) protocol communication to send detections and receive ICMS triggers. The source code and the instruction of the project can be found on GitHub.
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Tran, Trang Thi Thu, Phuoc-Loc Diep, Vu-Huynh-Tuan Phan, et al. "Automatic chip testing system." Science and Technology Development Journal - Natural Sciences 3, no. 3 (2020): 235–43. http://dx.doi.org/10.32508/stdjns.v3i3.605.
Full textAbstract:
In this paper, we implement an automatic chip testing system which can be applied on various types of chip packages. The conventional systems, such as manual chip testing systems, often repeat the same steps for input conditions; or high-cost testing systems are designed to be highly optimized, but the installation and operating costs are very expensive. This makes these systems difficult to be applied in education, research or small companies. The automatic chip testing system overcomes the above two weaknesses. The proposed system not only meets the requirement of a basic chip testing process, but also operates automatically and reduces the cost. Users only need to provide input data via a Graphical User Interface (GUI) which is built using C# programming language, then the system will automatically operate and return the corresponding output data to the software to synthesize and compare with the user’s expected data. The hardware is built on the TR4 FPGA Development Kit which helps save the cost of hardware design and its resources. The software and hardware withcommunicate to each other via Universal Asynchronous Receiver-Transmitter (UART) protocol. The proposed system is automatic, optimized and low-cost so that it can be applied both in IC design education and industry.
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Shrestha, Manish Man, Bibek Ropakheti, Uddhav Bhattarai, Ajaya Adhikari, and Shreeram Thakur. "Digital Ultrasonic Sensing Device with Programmable Frequency: Development and Analysis." Advances in Engineering and Technology: An International Journal 1, no. 1 (2021): 33–45. http://dx.doi.org/10.3126/aet.v1i1.39658.
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Ultrasonic wave is widely used in Structure Health Monitoring (SHM) systems. A piezoelectric transducer (PZT) is one of the most widely used sensors to acquire the structure's ultrasonic wave. As today's world is digital, it is necessary to digitize the traditional analog PZT sensing system. This paper describes the development and analysis of a digital ultrasonic sensing device (DUSD) for PZT sensors. We removed the complexities of the analog circuit by interfacing the microcontroller directly with the charge amplifier circuit. The microcontroller used in this research is a 32-bit ARM Cortex-M4 with in-built FPU (Floating Point Unit) and DSP (Digital signal processing) instructions. These features make it possible to compute complex signal processing algorithms and methods in the controller itself. The developed sensing device can communicate with the user and other devices using Universal Asynchronous Receiver/Transmitter (UART). The user can select cut-off frequencies of both high pass filters (HPF) and low pass filters (LPF) as well as types of data (ultrasonic waves, damage index) that the user wishes to collect from the device. To illustrate the proficiencies of the device, the ultrasonic wave was collected and evaluated to detect the damage in the test specimen.
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Bagbaba, Ahmet Cagri, Felipe Augusto da Silva, Matteo Sonza Reorda, Said Hamdioui, Maksim Jenihhin, and Christian Sauer. "Automated Identification of Application-Dependent Safe Faults in Automotive Systems-on-a-Chips." Electronics 11, no. 3 (2022): 319. http://dx.doi.org/10.3390/electronics11030319.
Full textAbstract:
ISO 26262 requires classifying random hardware faults based on their effects (safe, detected, or undetected) within integrated circuits used in automobiles. In general, this classification is addressed using expert judgment and a combination of tools. However, the growth of integrated circuit complexity creates a huge fault space; hence, this form of fault classification is error prone and time consuming. Therefore, an automated and systematic approach is needed to target hardware fault classification in automotive systems on chips (SoCs), considering the application software. This work focuses on identifying safe faults: the proposed approach utilizes coverage analysis to identify candidate safe faults considering all the constraints coming from the application. Then, the behavior of the application software is modeled so that we can resort to a formal analysis tool. The proposed technique is evaluated on the AutoSoC benchmark running a cruise control application. Resorting to our approach, we could classify 20%, 11%, and 13% of all faults in the central processing unit (CPU), universal asynchronous receiver–transmitter (UART), and controller area network (CAN) as safe faults, respectively. We also show that this classification can increase the diagnostic coverage of software test libraries targeting the CPU and CAN modules by 4% to 6%, increasing the achieved testable fault coverage.
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Firdaus, Sukma. "Rancang Bangun Interpreter On Board Diagnosis II(OBDII)." Jurnal Fisika FLUX 14, no. 1 (2017): 40. http://dx.doi.org/10.20527/flux.v14i1.3779.
Full textAbstract:
Telah dibuat interpreter On Board Diagnostic II (OBDII) menggunakan ic ELM 327. Untuk menjalankan ic ELM 327 ini digunakan kristal pembangkit detak sebesar 4.00MHz. Ic ELM 327 mendukung protokol pembacaan OBDII untuk beberapa jenis mobil yang diproduksi oleh perusahaan automotive sejak tahun 1996. Ic ELM 327 terhubung dengan port OBDII yang berada dibawah dashboard sisi pengemudi. Komuniksi interpreter dengan control sistem yang berfungsi sebagai pengirim perintah pembacaan data dan pemprosesan lanjutan menggunakan protokol Universal Asynchronous Receiver/Transmitter(UART). Rancangan Interpreter menggunakan standar J1979 untuk mengakses Parameter Ids (PID). PID yang diakses dalam penelitian ini adalah Throttle Position Sensor, Revolutions Per Minute(RPM) putaran mesin dan suhu kerja mesin yang dibaca melalui suhu cairan pendingin mesin. Untuk dapat membacanya, diperlukan pengaksesan terhadap registryPID. Untuk PIDT hrottle Position Sensoradalah 0x11, PID RPM putaran mesin adalah 0x0C dan untuk PID cairan pendingin mesin adalah 0x05. Dalam pengujian interpreter ini, diperoleh hasil RPM putaran mesin saat itu adalah sebesar 1956 RPM, hasil ini sesuai dengan jarum penunjuk pada panel instrument mobil, untuk persentase valve throttle terbuka sebesar 20% dengan suhu kerja mesin saat itu adalah sebesar 87oC. Dengan diperolehnyarawdata tersebut, menjadikan interpreter ini dapat melakukan proses lanjutan untuk menjadi tools evaluasi dari unjuk kerja mesin atau hanya sebatas data monitoring saja.
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Elp, Hudaverdi Emin, Hüseyin Altug, and Remzi İnan. "Designing a Brushed DC Motor Driver with a Novel Adaptive Learning Algorithm for the Automotive Industry." Electronics 13, no. 22 (2024): 4344. http://dx.doi.org/10.3390/electronics13224344.
Full textAbstract:
In this study, a stepper driver, which is suitable for use in the automotive industry, designed for general use, capable of adaptive learning in the systems in which it is used, and with CAN and universal asynchronous receiver–transmitter (UART) communication options, was designed. This design was made with a PIC18F25K22 microcontroller unit (MCU). Rotor speed, armature current, and terminal voltage can be measured on the proposed brushed DC motor drive system. It gives the desired response by evaluating obstacles and other situations in which high currents are drawn from the source. The speed measurement of the vehicle and the open and closed status of an automatic door can be monitored. The main contribution of the designed PCB is an adaptive learning algorithm (ALA) that uses the pulses of the encoder, estimates the position of the step, and manages the operation process to prevent mechanical damage at the final point of the motor. Furthermore, unexpected hitting and pinching which are defined as obstacles to the driver can be controlled by monitoring the current value drawn from the driver. The benefit of this method is that the life of the mechanical step is increased due to the management of the forward and backward step operation, preventing potential accidents.