Relevant bibliographies by topics / Universal Verification Methodology (UVM)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Universal Verification Methodology (UVM)'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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Journal articles on the topic "Universal Verification Methodology (UVM)"

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., Geethashree. "Verification of Dual Port RAM using System Verilog and UVM." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 30, 2021): 3651–56. http://dx.doi.org/10.22214/ijraset.2021.35847.

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Verification process place a prominent role in the field of SoC and ASIC design. Several verification methodologies are there apart from those Universal Verification Methodology (UVM) is advanced and it is widely used by the industries due to its special features. UVM provides reusable and well-structured verification components by using System Verilog class library. In this work, Dual Port RAM is considered as Design Under Test (DUT). System Verilog and UVM verification environments are developed to verify the DUT. Assertion and cover group coverage are set up with a goal of achieving 100% from both the environments.
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S Y, Janardhana. "Verification of AMBA AHB Protocol using UVM." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 30, 2021): 5287–92. http://dx.doi.org/10.22214/ijraset.2021.36203.

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The project aims to verify the AMBA AHB protocol by using universal verification methodology is presented in this paper. Advanced high-performance(AHB) is used for communication of on chip bus which support single clock edge operation wider data 32/64/128 bit can be supported. The new verification constructs can be easily reused for the objected-oriented feature of universal verification methodology (UVM). Verification IP is the one which provides a smart way to verify the AHB Components. The advanced verification testbench incorporates the illustrations regarding simulation result are analysed to evaluate the effectiveness of the proposed testbench and functional coverage is to check functionality of the design. The self-checking mechanism using assertions improves the quality of UVM check by shortening time to debug and reducing time to cover for the in-depth understanding of test case output.
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D. R, Pooja. "Verification of Wishbone Bus Interface for SoC using System Verilog and UVM." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 10, 2021): 158–63. http://dx.doi.org/10.22214/ijraset.2021.36282.

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The Verification phase carries important role in design cycle of a system on chip. Verification gives with the actual enactment and functionality of a DUT and to verify the design meets the system requirements. This paper present wishbone bus interface for soc integration to interconnect architecture for portable IP cores and test bench is developed in system Verilog and verification is done by both system Verilog verification methodology and universal verification methodology which includes scoreboard, functional coverage and assertion. This paper based on two application to integrate IP cores that is single master with single slave interconnection and single master with multiple slave interconnections where master is test bench and slave will be a core.
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Jain, Abhishek, and Richa Gupta. "Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors." VLSI Design 2016 (September 26, 2016): 1–14. http://dx.doi.org/10.1155/2016/7283471.

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In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP) RTL and firmware development. In this paper, we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW) implementation, reference for firmware (FW) implementation, and bit-true certification. The universal verification methodology- (UVM-) based functional verification framework of image signal processors using software reference models is described. Further, IP-XACT based tools for automatic generation of functional verification environment files and model map files are described. The proposed framework is developed both with host interface and with core using virtual register interface (VRI) approach. This modeling and functional verification framework is used in real-time image signal processing applications including cellphone, smart cameras, and image compression. The main motivation behind this work is to propose the best efficient, reusable, and automated framework for modeling and verification of image signal processor (ISP) designs. The proposed framework shows better results and significant improvement is observed in product verification time, verification cost, and quality of the designs.
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., Shambhavi. "Router1x3 Protocol Design Implementation and Verification with Virtual Cut through Mechanism for Network on Chip (NoC)." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 10, 2021): 16–24. http://dx.doi.org/10.22214/ijraset.2021.36226.

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Hundreds of processors and memory cores are implemented on a single substrate called the System on Chip (SoC). The SoC with bus-based architecture has restrictions on the processing speed of the system and as the design becomes complex and the issue of scalability arises. Hence NoC is designed to enhance the scalability, data reliability, and processing speed with low power consumption by decoupling communication from computations [1]. Using NoC the IP cores of SoC are connected through on-chip routers and send data to each other through packet switching. The router is a processing chip that decides the right path for data transmission, hence the efficient design of the router is essential to enhance the performance and throughput of the system [2]. To reduces latency through the switch, the Virtual cut-through mechanism is a packet switching technique, in which the switch starts forwarding a packet as soon as the destination address is processed by header. Hence the present work focuses on a router input-output protocol design with the Virtual Cut-through mechanism for closed-loop communication. Router 1x3 has a single input port and three output ports. The architecture of Router 1x3 with sub-modules such as FIFO, FSM, Synchronizer, and Register is designed analyzed and verified using Verilog, System Verilog language, and Universal Verification Methodology(UVM). And it is also implemented on Xilinx 14.5 IDE with Spartan-6- XC6SLX45 FPGA.
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Ankitha, Ankitha, and Dr H. V. Ravish Aradhya. "A Python based Design Verification Methodology." Journal of University of Shanghai for Science and Technology 23, no. 06 (June 18, 2021): 901–11. http://dx.doi.org/10.51201/jusst/21/05358.

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While the UVM-constrained random and coverage-driven verification methodology revolutionized IP and unit-level testing, it falls short of SoC-level verification needs. A solution must extend from UVM and enable vertical (IP to SoC) and horizontal (verification engine portability) reuse to completely handle SoC-level verification. To expedite test-case generation and use rapid verification engines, it must also provide a method to collect, distribute, and automatically amplify use cases. Opting a Python-based Design Verification approach opens the door to various such merits. Cocotb is a very useful, growing methodology which can be used for the same. This paper elaborates on the application of cocotb, an open-source framework hosted on Github which is based on CO-routine and CO-simulation of Testbench environment for verifying VHDL/Verilog RTL using Python. It employs equivalent design-reuse and functional verification concepts like UVM, however is implemented in Python, which is much simpler to understand and that leads to faster development and reduces the turnaround time.
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Rajashekar Reddy, P., P. Sreekanth, and K. Arun Kumar. "Serial Peripheral Interface-Master Universal Verification Component using UVM." International Journal of Advanced Scientific Technologies in Engineering and Management Sciences 3, no. 6 (June 1, 2017): 27. http://dx.doi.org/10.22413/ijastems/2017/v3/i6/49102.

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Kulkarni, Aman, and S. M. Sakthivel. "UVM methodology based functional Verification of SPI Protocol." Journal of Physics: Conference Series 1716 (December 2020): 012035. http://dx.doi.org/10.1088/1742-6596/1716/1/012035.

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., Darshan. "Verification of Open Core Protocol using System Verilog and UVM." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 30, 2021): 5501–10. http://dx.doi.org/10.22214/ijraset.2021.36213.

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The ever-increasing complexity of the integrated circuits design and the scale of the projects are making verification more challenging and time-consuming. As a result, the rapidly expanding VLSI industry necessitates a highly reliable and robust verification mechanism. In this paper, System Verilog Verification and Universal Verification Methodologies were adopted to verify the Accellera Open Core Protocol 3.0 as per specifications. According to the verification plan, the environment was developed under a dynamic approach, and the passive aspects included scoreboard, functional coverage, and system verilog assertions. The presented frameworks had verified OCP achieving successful dataflow signals extensions as per results.
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Sathyamurthy, Muralikrishna, Felix Neumann, Lukasz Kotynia, and Eckhard Hennig. "UVM-based verification methodology for RFID-enabled smart-sensor systems." Analog Integrated Circuits and Signal Processing 78, no. 1 (November 19, 2013): 191–207. http://dx.doi.org/10.1007/s10470-013-0225-5.

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Dissertations / Theses on the topic "Universal Verification Methodology (UVM)"

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Jayabalan, Arun. "Development of a Massively Parallel Coarse Grained Reconfigurable Fabric verification Environment using Universal Verification Methodology." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-206099.

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According to the International Roadmap for semiconductors (ITRS), there should be a 1000X improvement in performance with only 120% increase in the power budget and no increase in the design team size to deal with designs that are 10X more complex. One solution to cope with this complexity is to increase the granularity of the building blocks for developing new architectures. As a solution, Dynamically Reconfigurable Resource Array (DRRA) with Distributed Memory Architecture(DiMArch) was developed. As the design complexity increased, the need for verification became inevitable in the design flow. To include the feature of reusability, a reconfigurable verification environment is required to effectively verify the device under test (DUT) and also improve the productivity in the design cycle. The thesis work begins with the specification & design and also the verification plans for the DRRA and DiMArch. The major task of the thesis work is in developing a reconfigurable verification environment for the DRRA using Universal Verification Methodology (UVM) and a systemlevel verification test bench for the DiMArch . This thesis work also focuses on the possible power optimization in the design.
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Vavro, Tomáš. "Periferie procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-445553.

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The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.
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Tiikkainen, M. (Martti). "Automated functional coverage driven verification with Universal Verification Methodology." Master's thesis, University of Oulu, 2017. http://jultika.oulu.fi/Record/nbnfioulu-201711033027.

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Abstract. In this Master’s thesis, the validity of Universal Verification Methodology in digital design verification is studied. A brief look into the methodology’s history is taken, and its unique properties and object-oriented features are presented. Important coverage topics in project planning are discussed, and the two main types of coverage, code and functional coverage, are explained and the methods how they are captured are presented. The practical section of this thesis shows the implementation of a monitoring environment and an Universal Verification Methodology environment. The monitoring environment includes class-based components that are used to collect functional coverage from an existing SystemVerilog test bench. The Universal Verification Methodology environment uses the same monitoring system, but a different driving setup to stress the design under test. Coverage and simulation performance values are extracted and from all test benches and the data is compared. The results indicate that the Universal Verification Methodology environment incorporating constrained random stimulus is capable of faster simulation run times and better code coverage values. The simulation time measured was up to 26 % faster compared to a module-based environment.Automaattinen toiminnallisen kattavuuden ohjaama verifiointi universaalilla varmennusmenetelmällä. Tiivistelmä. Tässä diplomityössä tutkitaan universaalin varmennusmenetelmän (Universal Verification Methodology) soveltuvuutta digitaalisten laitteiden verifiointiin. Työssä tehdään lyhyt katsaus menetelmän historiaan. Lisäksi menetelmän omia ainutlaatuisia ja olio-pohjaisia ominaisuuksia käydään läpi. Kattavuuteen liittyviä käsitteitä esitetään projektihallinnan näkökulmasta. Kattavuudesta käsitellään toiminnallinen ja koodikattavuus, ja tavat, miten näitä molempia kerätään simulaatioista. Työn käytännön osuudessa esitetään monitorointiympäristön ja universaalin varmennusmenetelmän pohjalta tehdyn ympäristön toteutus. Monitorointi-ympäristössä on luokkapohjaisia komponentteja, joiden avulla kerätään toiminnallista kattavuutta jo olemassa olevasta testipenkistä. Universaalin varmennusmenetelmän pohjalta tehdyssä ympäristössä on samojen monitorointikomponenttien lisäksi testattavan kohteen ohjaamiseen vaadittavia komponentteja. Eri testipenkeistä kerätään kattavuuteen ja suorituskykyyn liittyvää dataa vertaamista varten. Tulokset viittaavat siihen, että rajoitettua satunnaista herätettä hyödykseen käyttävät universaalit varmennusmenetelmäympäristöt pääsevät nopeampiin suoritusaikoihin ja parempiin koodikattavuuslukuihin. Simulaation suoritusaikaan saatiin parhaassa tapauksessa jopa 26 % parannus.
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Yang, Xiaokun. "A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)." FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2477.

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With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations. As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI. Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs.
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Zachariášová, Marcela. "Metody akcelerace verifikace logických obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2015. http://www.nusl.cz/ntk/nusl-261278.

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Při vývoji současných číslicových systémů, např. vestavěných systému a počítačového hardware, je nutné hledat postupy, jak zvýšit jejich spolehlivost. Jednou z možností je zvyšování efektivity a rychlosti verifikačních procesů, které se provádějí v raných fázích návrhu. V této dizertační práci se pozornost věnuje verifikačnímu přístupu s názvem funkční verifikace. Je identifikováno několik výzev a problému týkajících se efektivity a rychlosti funkční verifikace a ty jsou následně řešeny v cílech dizertační práce. První cíl se zaměřuje na redukci simulačního času v průběhu verifikace komplexních systémů. Důvodem je, že simulace inherentně paralelního hardwarového systému trvá velmi dlouho v porovnání s během v skutečném hardware. Je proto navrhnuta optimalizační technika, která umisťuje verifikovaný systém do FPGA akcelerátoru, zatím co část verifikačního prostředí stále běží v simulaci. Tímto přemístěním je možné výrazně zredukovat simulační režii. Druhý cíl se zabývá ručně připravovanými verifikačními prostředími, která představují výrazné omezení ve verifikační produktivitě. Tato režie však není nutná, protože většina verifikačních prostředí má velice podobnou strukturu, jelikož využívají komponenty standardních verifikačních metodik. Tyto komponenty se jen upravují s ohledem na verifikovaný systém. Proto druhá optimalizační technika analyzuje popis systému na vyšší úrovni abstrakce a automatizuje tvorbu verifikačních prostředí tím, že je automaticky generuje z tohoto vysoko-úrovňového popisu. Třetí cíl zkoumá, jak je možné docílit úplnost verifikace pomocí inteligentní automatizace. Úplnost verifikace se typicky měří pomocí různých metrik pokrytí a verifikace je ukončena, když je dosažena právě vysoká úroveň pokrytí. Proto je navržena třetí optimalizační technika, která řídí generování vstupů pro verifikovaný systém tak, aby tyto vstupy aktivovali současně co nejvíc bodů pokrytí a aby byla rychlost konvergence k maximálnímu pokrytí co nejvyšší. Jako hlavní optimalizační prostředek se používá genetický algoritmus, který je přizpůsoben pro funkční verifikaci a jeho parametry jsou vyladěny pro tuto doménu. Běží na pozadí verifikačního procesu, analyzuje dosažené pokrytí a na základě toho dynamicky upravuje omezující podmínky pro generátor vstupů. Tyto podmínky jsou reprezentovány pravděpodobnostmi, které určují výběr vhodných hodnot ze vstupní domény. Čtvrtý cíl diskutuje, zda je možné znovu použít vstupy z funkční verifikace pro účely regresního testování a optimalizovat je tak, aby byla rychlost testování co nejvyšší. Ve funkční verifikaci je totiž běžné, že vstupy jsou značně redundantní, jelikož jsou produkovány generátorem. Pro regresní testy ale tato redundance není potřebná a proto může být eliminována. Zároveň je ale nutné dbát na to, aby úroveň pokrytí dosáhnutá optimalizovanou sadou byla stejná, jako u té původní. Čtvrtá optimalizační technika toto reflektuje a opět používá genetický algoritmus jako optimalizační prostředek. Tentokrát ale není integrován do procesu verifikace, ale je použit až po její ukončení. Velmi rychle odstraňuje redundanci z původní sady vstupů a výsledná doba simulace je tak značně optimalizována.
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Araújo, Pedro Manuel Azevedo. "Development of a Reconfigurable Multi-Protocol Verification Environment Using UVM Methodology." Dissertação, 2014. https://repositorio-aberto.up.pt/handle/10216/73167.

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Araújo, Pedro Manuel Azevedo. "Development of a Reconfigurable Multi-Protocol Verification Environment Using UVM Methodology." Master's thesis, 2014. https://repositorio-aberto.up.pt/handle/10216/73167.

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Books on the topic "Universal Verification Methodology (UVM)"

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A, Meade Kathleen, ed. A practical guide to adopting the Universal Verification Methodology (UVM). San Jose, CA: Cadence Design Systems, 2010.

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Salemi, Ray. The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology. Boston Light Press, 2013.

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Book chapters on the topic "Universal Verification Methodology (UVM)"

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Mehta, Ashok B. "UVM (Universal Verification Methodology)." In ASIC/SoC Functional Design Verification, 17–64. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59418-7_4.

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Nagesh, K. Arpitha, and D. R. Shilpa. "Verification of SerDes Design Using UVM Methodology." In Lecture Notes in Electrical Engineering, 607–16. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-0275-7_49.

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Mohamed, Khaled Salah. "New Trends in SoC Verification: UVM, Bug Localization, Scan-C0068ain-Based Methodology, GA-Based Test Generation." In Analog Circuits and Signal Processing, 121–52. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-22035-2_6.

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Logeish Raj, R., and Rosmiwati Mohd-Mokhtar. "Autonomous Agent for Universal Verification Methodology Testbench of Hard Memory Controller." In 9th International Conference on Robotic, Vision, Signal Processing and Power Applications, 9–17. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1721-6_2.

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Marconi, Sara, Elia Conti, Pisana Placidi, Andrea Scorzoni, Jorgen Christiansen, and Tomasz Hemperek. "A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications." In Lecture Notes in Electrical Engineering, 35–41. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-47913-2_5.

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Conference papers on the topic "Universal Verification Methodology (UVM)"

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Qamar, Shumaila, Wasi Haider Butt, Muhammad Waseem Anwar, Farooque Azam, and Muhammad Qasim Khan. "A Comprehensive Investigation of Universal Verification Methodology (UVM) Standard for Design Verification." In ICSCA 2020: 2020 9th International Conference on Software and Computer Applications. New York, NY, USA: ACM, 2020. http://dx.doi.org/10.1145/3384544.3384547.

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Shui, Xuanxuan, Yichun Wu, Junyi Zhou, and Yuanfeng Cai. "Component and Integration Test of an FPGA-Based PWR Protection Sub-System Using UVM." In 2017 25th International Conference on Nuclear Engineering. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/icone25-66526.

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Field programmable gate arrays (FPGAs) have drawn wide attention from nuclear power industry for digital instrument and control applications (DI&C), because it’s much easier and simpler than microprocessor-based applications, which makes it more reliable. FPGAs can also enhance safety margins of the plant with potential possibility for power upgrading at normal operation. For these reasons, more and more nuclear power corporations and research institutes are treating FPGA-based protection system as a technical alternative. As nuclear power industry requires high reliability and safety for DI&C Systems, the development method and process should be fully verified and validated. For this reason, to improve the application of FPGA in NPP I&C system, the specific test methods are critical for the developers and regulators. However, current international standards and research reports, like IEC 62566 and NUREG/CR-7006, which have demonstrated the life circle of the development of FPGA-based safety critical DI&C in NPPs, but the specific test requirements and methods which are significant to the developers are not provided. In this paper, the whole test process of a pressurized water reactor (PWR) protection sub-system (Primary Coolant Flow Low Protection, Over Temperature Delta T Protection, Over Power Delta T Protection) is described, including detail component and integration tests. The Universal Verification Methodology (UVM) based on System Verilog class libraries is applied to establish the verification test platform. All these tests are conducted in a simulation environment. The test process is driven by the test coverage which includes code coverages (i.e., Statement, Branch, Condition and Expression, Toggle, Finite State Machine) and function coverage. Specifically, Register Transaction Level (RTL) simulation is conducted for Component tests, while RTL simulation, Gate Level simulation, Timing simulation and Static timing analysis are conducted for the integration test. The issues (e.g., the floating point calculation, FPGA resource allocation and optimization) arose in the test process are also analyzed and discussed, which can be references for the developers in this area. The component and integration tests are part of the Verification and Validation (V&V) work, which should be done by the V&V team separated from the development team. The testing method could assure the test results reliable and authentic. It is practical and useful for the development and V&V of FPGA-based safety DI&C systems.
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Drechsler, Rolf, Christophe Chevallaz, Franco Fummi, Alan J. Hu, Ronny Morad, Frank Schirrmeister, and Alex Goryachev. "Panel: Future SoC verification methodology: UVM evolution or revolution?" In Design Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2014. http://dx.doi.org/10.7873/date2014.385.

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Drechsler, Rolf, Christophe Chevallaz, Franco Fummi, Alan J. Hu, Ronny Morad, Frank Schirrmeister, and Alex Goryachev. "Panel: Future SoC verification methodology: UVM evolution or revolution?" In Design Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2014. http://dx.doi.org/10.7873/date.2014.385.

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Fathy, Khaled, and Khaled Salah. "An Efficient Scenario Based Testing Methodology Using UVM." In 2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV). IEEE, 2016. http://dx.doi.org/10.1109/mtv.2016.14.

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Biswal, Barada P., Anurag Singh, and Balwinder Singh. "Cache coherency controller verification IP using SystemVerilog Assertions (SVA) and Universal Verification Methodologies (UVM)." In 2017 11th International Conference on Intelligent Systems and Control (ISCO). IEEE, 2017. http://dx.doi.org/10.1109/isco.2017.7855984.

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Khalifa, Khaled, and Khaled Salah. "Implementation and verification of a generic universal memory controller based on UVM." In 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE, 2015. http://dx.doi.org/10.1109/dtis.2015.7127364.

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El-Ashry, Sameh, and Ahmed Adel. "Efficient Methodology of Sampling UVM RAL During Simulation for SoC Functional Coverage." In 2018 19th International Workshop on Microprocessor and SOC Test and Verification (MTV). IEEE, 2018. http://dx.doi.org/10.1109/mtv.2018.00022.

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Lohmann, Douglas, Fabrizio Maziero, Elco Joao dos Santos, and Djones Lettnin. "Extending universal verification methodology with fault injection capabilities." In 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS). IEEE, 2018. http://dx.doi.org/10.1109/lascas.2018.8399945.

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Konale, Srikanth, and N. Bheema Rao. "C-based predictor for scoreboard in Universal Verification Methodology." In 2014 International Conference on Advances in Engineering and Technology Research (ICAETR). IEEE, 2014. http://dx.doi.org/10.1109/icaetr.2014.7012913.

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