Relevant bibliographies by topics / Universal Verification Methodology (UVM)

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  2. Dissertations / Theses
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Academic literature on the topic 'Universal Verification Methodology (UVM)'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2025

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Journal articles on the topic "Universal Verification Methodology (UVM)"

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Kulkarni, Manjiri, and Dr S. P. Meharunnisa. "Study on Transformation to Universal Verification Methodology." International Journal for Research in Applied Science and Engineering Technology 10, no. 8 (2022): 1847–49. http://dx.doi.org/10.22214/ijraset.2022.46466.

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Abstract: There are many approaches to the RTL design Verification. The different types of approach can be software simulation based, hardware accelerated simulation, formal verification etc. It helps to verify the correctness of the design, functional implementation and enhancing the design at every stage. Transition to Systemverilog has been done to cope up with the shrinking size of technology nodes and Time to market. In advanced times, the systems are to be designed in a generic way. The number of registers in the architecture increases as the number of combinations increases. Additionall
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Niharika, Sahu, and Sahu Chandrahas. "Boosting chip verification efficiency: UVM-based adder verification with QuestaSim." i-manager's Journal on Digital Signal Processing 11, no. 1 (2023): 16. http://dx.doi.org/10.26634/jdp.11.1.19768.

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The Very Large-Scale Integration (VLSI) industry is currently experiencing rapid growth in chip verification and design. This research focuses on generating a waveform, simulating, and verifying the Universal Verification Methodology (UVM) adder code using the QuestaSim tool and the UVM methodology. The functional verification community and researchers have an interest in UVM as it offers flexibility, reusability, and reliability properties that are useful for verifying complex chip systems. The main objective of this research is to verify the code of the UVM adder using the QuestaSim tool, wh
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Pulli, A., I. Kremastiotis, and S. Kulis. "Verification methodology of a multi-mode radiation-hard high-speed transceiver ASIC." Journal of Instrumentation 17, no. 03 (2022): C03008. http://dx.doi.org/10.1088/1748-0221/17/03/c03008.

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Abstract The second version of Low Power Giga Bit Transceiver (lpGBTv1) addresses the functional and radiation-related issues discovered during the testing of lpGBTv0 prototype. Considerable changes to the chip configuration architecture and flow were required. The Universal Verification Methodology (UVM) based verification environment was extensively refactored to address the functional verification challenges posed by the architectural changes in the chip. Additionally, the new UVM environment was designed to support extensive verification of robustness to Single Event Effects (SEE). In this
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Sonali, Sangode, and Sahu Chandrahas. "Design and verification of memory by using UVM methodology." i-manager's Journal on Digital Signal Processing 11, no. 1 (2023): 35. http://dx.doi.org/10.26634/jdp.11.1.19769.

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The design and verification of memory using the Universal Verification Methodology (UVM) methodology is discussed in this research. The advanced verification architecture uses a minimum number of macros, methods, and classes, and it provides high reusability for UVM tests. It makes use of the common attributes between different memory controllers to generate a common and configurable scoreboard, sequences, stimulus, different UVM components, and test cases. The memory controller provides a constructive control of data between the processor and memory. It provides modern structure and building
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Liao, Chin-Wen, Hsiu-Chou Yu, and Yu-Cheng Liao. "Verification of SPI Protocol Using Universal Verification Methodology for Modern IoT and Wearable Devices." Electronics 14, no. 5 (2025): 837. https://doi.org/10.3390/electronics14050837.

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The Serial Peripheral Interface (SPI) protocol plays a crucial role in wearable and IoT devices, enabling high-speed communication between microcontrollers and peripherals such as sensors, displays, and connectivity modules. With the increasing complexity of modern devices and system-on-chip (SoC) designs, robust verification methods are essential to ensure functionality and reliability. This paper utilizes the Universal Verification Methodology (UVM) to develop a scalable and reusable testbench for SPI verification. The process encompasses test planning, simulation, emulation, and top-level v
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., Geethashree. "Verification of Dual Port RAM using System Verilog and UVM." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 3651–56. http://dx.doi.org/10.22214/ijraset.2021.35847.

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Verification process place a prominent role in the field of SoC and ASIC design. Several verification methodologies are there apart from those Universal Verification Methodology (UVM) is advanced and it is widely used by the industries due to its special features. UVM provides reusable and well-structured verification components by using System Verilog class library. In this work, Dual Port RAM is considered as Design Under Test (DUT). System Verilog and UVM verification environments are developed to verify the DUT. Assertion and cover group coverage are set up with a goal of achieving 100% fr
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Bindu, A. "A rigorous approach to microprocessor verification using UVM." i-manager’s Journal on Electronics Engineering 13, no. 1 (2022): 39. http://dx.doi.org/10.26634/jele.13.1.19344.

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In today's fast-paced technology industry, microprocessors play an increasingly important role in a wide range of applications. However, verifying the correctness of complex microprocessor designs remains a significant challenge. To address this issue, a rigorous approach to microprocessor verification using the Universal Verification Methodology (UVM) is proposed. UVM provides a standardised and scalable approach to verifying digital designs, including microprocessors, and has been widely adopted in the industry. This research proposes a UVM-based verification framework for microprocessors th
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S Y, Janardhana. "Verification of AMBA AHB Protocol using UVM." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 5287–92. http://dx.doi.org/10.22214/ijraset.2021.36203.

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The project aims to verify the AMBA AHB protocol by using universal verification methodology is presented in this paper. Advanced high-performance(AHB) is used for communication of on chip bus which support single clock edge operation wider data 32/64/128 bit can be supported. The new verification constructs can be easily reused for the objected-oriented feature of universal verification methodology (UVM). Verification IP is the one which provides a smart way to verify the AHB Components. The advanced verification testbench incorporates the illustrations regarding simulation result are analysed
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Researcher. "UVM METHODOLOGY: INDUSTRY-SPECIFIC APPLICATIONS IN MODERN HARDWARE VERIFICATION." International Journal of Computer Engineering and Technology (IJCET) 15, no. 6 (2024): 20–32. https://doi.org/10.5281/zenodo.14040112.

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The Universal Verification Methodology (UVM) has revolutionized functional verification across multiple industries, demonstrating significant improvements in verification efficiency, cost reduction, and product reliability. This comprehensive analysis examines UVM's implementation impact across semiconductor, automotive, telecommunications, aerospace and defense, healthcare, and consumer electronics sectors, presenting quantitative data from industry leaders. The article reveals remarkable improvements, including an average 76% reduction in verification cycles, 85% improvement in bug detection
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Li, Haoqiang, and Shikai Zuo. "Functional verification of QSPI module based on UVM implementation." Journal of Physics: Conference Series 2645, no. 1 (2023): 012002. http://dx.doi.org/10.1088/1742-6596/2645/1/012002.

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Abstract This article presents a novel functional verification methodology based on the Universal Verification Methodology (UVM) to validate the functionality of the Quick Serial Peripheral Interface (QSPI) module. QSPI serves as a prevalent serial communication protocol widely employed for high-speed data exchange with external flash devices. By using the code coverage and functional coverage reports provided by UVM, we were able to assess how well the test cases covered the design code, identifying the parts of the design that had been adequately tested and those that needed more test covera
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Dissertations / Theses on the topic "Universal Verification Methodology (UVM)"

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Jayabalan, Arun. "Development of a Massively Parallel Coarse Grained Reconfigurable Fabric verification Environment using Universal Verification Methodology." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-206099.

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According to the International Roadmap for semiconductors (ITRS), there should be a 1000X improvement in performance with only 120% increase in the power budget and no increase in the design team size to deal with designs that are 10X more complex. One solution to cope with this complexity is to increase the granularity of the building blocks for developing new architectures. As a solution, Dynamically Reconfigurable Resource Array (DRRA) with Distributed Memory Architecture(DiMArch) was developed. As the design complexity increased, the need for verification became inevitable in the design fl
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Vavro, Tomáš. "Periferie procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-445553.

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The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the lan
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Tiikkainen, M. (Martti). "Automated functional coverage driven verification with Universal Verification Methodology." Master's thesis, University of Oulu, 2017. http://jultika.oulu.fi/Record/nbnfioulu-201711033027.

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Abstract. In this Master’s thesis, the validity of Universal Verification Methodology in digital design verification is studied. A brief look into the methodology’s history is taken, and its unique properties and object-oriented features are presented. Important coverage topics in project planning are discussed, and the two main types of coverage, code and functional coverage, are explained and the methods how they are captured are presented. The practical section of this thesis shows the implementation of a monitoring environment and an Universal Verification Methodology environment. The mon
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Yang, Xiaokun. "A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)." FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2477.

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With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can fram
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Zachariášová, Marcela. "Metody akcelerace verifikace logických obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2015. http://www.nusl.cz/ntk/nusl-261278.

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Při vývoji současných číslicových systémů, např. vestavěných systému a počítačového hardware, je nutné hledat postupy, jak zvýšit jejich spolehlivost. Jednou z možností je zvyšování efektivity a rychlosti verifikačních procesů, které se provádějí v raných fázích návrhu. V této dizertační práci se pozornost věnuje verifikačnímu přístupu s názvem funkční verifikace. Je identifikováno několik výzev a problému týkajících se efektivity a rychlosti funkční verifikace a ty jsou následně řešeny v cílech dizertační práce. První cíl se zaměřuje na redukci simulačního času v průběhu verifikace komplexníc
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Araújo, Pedro Manuel Azevedo. "Development of a Reconfigurable Multi-Protocol Verification Environment Using UVM Methodology." Master's thesis, 2014. https://repositorio-aberto.up.pt/handle/10216/73167.

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Araújo, Pedro Manuel Azevedo. "Development of a Reconfigurable Multi-Protocol Verification Environment Using UVM Methodology." Dissertação, 2014. https://repositorio-aberto.up.pt/handle/10216/73167.

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Books on the topic "Universal Verification Methodology (UVM)"

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A, Meade Kathleen, ed. A practical guide to adopting the Universal Verification Methodology (UVM). Cadence Design Systems, 2010.

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Conley, Raymond. Universal Verification Methodology : Doulos Uvm Golden Reference Guide: Uvm Debug. Independently Published, 2021.

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Meade, Kathleen, and Sharon Rosenberg. Practical Guide to Adopting the Universal Verification Methodology (UVM) Ebook. Lulu Press, Inc., 2010.

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Salemi, Ray. The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology. Boston Light Press, 2013.

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Meade, Kathleen, and Sharon Rosenberg. A Practical Guide to Adopting the Universal Verification Methodology Second Edition. Lulu.com, 2012.

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Book chapters on the topic "Universal Verification Methodology (UVM)"

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Mehta, Ashok B. "UVM (Universal Verification Methodology)." In ASIC/SoC Functional Design Verification. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59418-7_4.

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Nagesh, K. Arpitha, and D. R. Shilpa. "Verification of SerDes Design Using UVM Methodology." In Lecture Notes in Electrical Engineering. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-0275-7_49.

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Tieth, Sarabjeet Singh, and P. M. Menghal. "Verification of Microprocessor Using Universal Verification Methodology." In Smart Technologies for Energy, Environment and Sustainable Development, Vol 1. Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6875-3_41.

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Mohamed, Khaled Salah. "New Trends in SoC Verification: UVM, Bug Localization, Scan-C0068ain-Based Methodology, GA-Based Test Generation." In Analog Circuits and Signal Processing. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-22035-2_6.

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Logeish Raj, R., and Rosmiwati Mohd-Mokhtar. "Autonomous Agent for Universal Verification Methodology Testbench of Hard Memory Controller." In 9th International Conference on Robotic, Vision, Signal Processing and Power Applications. Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1721-6_2.

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Raia, Gaetano, Gianluca Rigano, David Vincenzoni, and Maurizio Martina. "A Case Study on Formal Equivalence Verification Between a C/C++ Model and Its RTL Design." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-71177-0_23.

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AbstractIn the field of communication system products, most datapath Digital Signal Processing algorithms are initially developed at a high-level in MATLAB® or C/C++. Subsequently, design engineers use these models as a reference for implementing Register Transfer Level designs. The conventional approach to verify their equivalence involves extensive Universal Verification Methodology dynamic simulations, which can last for months and require significant verification efforts. However, some elusive errors might still occur because it is infeasible to explore all input combinations with this met
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Marconi, Sara, Elia Conti, Pisana Placidi, Andrea Scorzoni, Jorgen Christiansen, and Tomasz Hemperek. "A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications." In Lecture Notes in Electrical Engineering. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-47913-2_5.

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Boiko, Yana. "MODELLING AS A METHOD OF COGNITION IN THE HUMANITIESMODELLING AS A METHOD OF COGNITION IN THE HUMANITIES." In Development of scientific, technological and innovation space in Ukraine and EU countries. Publishing House “Baltija Publishing”, 2021. http://dx.doi.org/10.30525/978-9934-26-151-0-1.

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Modelling of physical objects, processes, and phenomena, i.e. their study by creating their copies (models), which reproduce their characteristic properties, is a powerful tool used by researchers while studying the systems of different nature. The purpose of the paper is to demonstrate the genesis of modelling as an effective method of cognition in the framework of the anthropocentric paradigm of research. The solution of such research problems determines the logic of the presentation of the studied material in the paper: systematisation of achievements in the theory and practice of modelling
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Conference papers on the topic "Universal Verification Methodology (UVM)"

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B V, Uma, and Kumar Muchalambi. "Design and Verification of DDR5 Subsystem Using UVM Methodology." In 2024 8th International Conference on Computational System and Information Technology for Sustainable Solutions (CSITSS). IEEE, 2024. https://doi.org/10.1109/csitss64042.2024.10817033.

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Bhuneswary, N., K. Kiran Kumar Reddy, M. Surya Sagar Reddy, K. Venkata Sai, and K. Satyanarayana. "Serial Peripheral Interface with SOC Using Universal Verification Methodology." In 2024 Global Conference on Communications and Information Technologies (GCCIT). IEEE, 2024. https://doi.org/10.1109/gccit63234.2024.10862338.

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Qamar, Shumaila, Wasi Haider Butt, Muhammad Waseem Anwar, Farooque Azam, and Muhammad Qasim Khan. "A Comprehensive Investigation of Universal Verification Methodology (UVM) Standard for Design Verification." In ICSCA 2020: 2020 9th International Conference on Software and Computer Applications. ACM, 2020. http://dx.doi.org/10.1145/3384544.3384547.

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Loh, Siu Hong, You Hong Liew, and Jia Jia Sim. "VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM)." In 2022 IEEE 12th International Conference on Control System, Computing and Engineering (ICCSCE). IEEE, 2022. http://dx.doi.org/10.1109/iccsce54767.2022.9935582.

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Shui, Xuanxuan, Yichun Wu, Junyi Zhou, and Yuanfeng Cai. "Component and Integration Test of an FPGA-Based PWR Protection Sub-System Using UVM." In 2017 25th International Conference on Nuclear Engineering. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/icone25-66526.

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Field programmable gate arrays (FPGAs) have drawn wide attention from nuclear power industry for digital instrument and control applications (DI&C), because it’s much easier and simpler than microprocessor-based applications, which makes it more reliable. FPGAs can also enhance safety margins of the plant with potential possibility for power upgrading at normal operation. For these reasons, more and more nuclear power corporations and research institutes are treating FPGA-based protection system as a technical alternative. As nuclear power industry requires high reliability and safety for
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Drechsler, Rolf, Christophe Chevallaz, Franco Fummi, et al. "Panel: Future SoC verification methodology: UVM evolution or revolution?" In Design Automation and Test in Europe. IEEE Conference Publications, 2014. http://dx.doi.org/10.7873/date2014.385.

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Drechsler, Rolf, Christophe Chevallaz, Franco Fummi, et al. "Panel: Future SoC verification methodology: UVM evolution or revolution?" In Design Automation and Test in Europe. IEEE Conference Publications, 2014. http://dx.doi.org/10.7873/date.2014.385.

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Fathy, Khaled, and Khaled Salah. "An Efficient Scenario Based Testing Methodology Using UVM." In 2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV). IEEE, 2016. http://dx.doi.org/10.1109/mtv.2016.14.

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Su, Rui, Rui Chen, Yongping Men, and Xinen Cao. "Study on universal automatic FPGA simulation verification platform based on UVM." In 2023 3rd International Conference on Digital Signal and Computer Communications (DSCC 2023), edited by Yang Yue and Shuwen Xu. SPIE, 2023. http://dx.doi.org/10.1117/12.2685650.

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Biswal, Barada P., Anurag Singh, and Balwinder Singh. "Cache coherency controller verification IP using SystemVerilog Assertions (SVA) and Universal Verification Methodologies (UVM)." In 2017 11th International Conference on Intelligent Systems and Control (ISCO). IEEE, 2017. http://dx.doi.org/10.1109/isco.2017.7855984.

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