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Journal articles on the topic 'Universal Verification Methodology (UVM)'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Kulkarni, Manjiri, and Dr S. P. Meharunnisa. "Study on Transformation to Universal Verification Methodology." International Journal for Research in Applied Science and Engineering Technology 10, no. 8 (2022): 1847–49. http://dx.doi.org/10.22214/ijraset.2022.46466.

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Abstract: There are many approaches to the RTL design Verification. The different types of approach can be software simulation based, hardware accelerated simulation, formal verification etc. It helps to verify the correctness of the design, functional implementation and enhancing the design at every stage. Transition to Systemverilog has been done to cope up with the shrinking size of technology nodes and Time to market. In advanced times, the systems are to be designed in a generic way. The number of registers in the architecture increases as the number of combinations increases. Additionall

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Niharika, Sahu, and Sahu Chandrahas. "Boosting chip verification efficiency: UVM-based adder verification with QuestaSim." i-manager's Journal on Digital Signal Processing 11, no. 1 (2023): 16. http://dx.doi.org/10.26634/jdp.11.1.19768.

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The Very Large-Scale Integration (VLSI) industry is currently experiencing rapid growth in chip verification and design. This research focuses on generating a waveform, simulating, and verifying the Universal Verification Methodology (UVM) adder code using the QuestaSim tool and the UVM methodology. The functional verification community and researchers have an interest in UVM as it offers flexibility, reusability, and reliability properties that are useful for verifying complex chip systems. The main objective of this research is to verify the code of the UVM adder using the QuestaSim tool, wh

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Pulli, A., I. Kremastiotis, and S. Kulis. "Verification methodology of a multi-mode radiation-hard high-speed transceiver ASIC." Journal of Instrumentation 17, no. 03 (2022): C03008. http://dx.doi.org/10.1088/1748-0221/17/03/c03008.

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Abstract The second version of Low Power Giga Bit Transceiver (lpGBTv1) addresses the functional and radiation-related issues discovered during the testing of lpGBTv0 prototype. Considerable changes to the chip configuration architecture and flow were required. The Universal Verification Methodology (UVM) based verification environment was extensively refactored to address the functional verification challenges posed by the architectural changes in the chip. Additionally, the new UVM environment was designed to support extensive verification of robustness to Single Event Effects (SEE). In this

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Sonali, Sangode, and Sahu Chandrahas. "Design and verification of memory by using UVM methodology." i-manager's Journal on Digital Signal Processing 11, no. 1 (2023): 35. http://dx.doi.org/10.26634/jdp.11.1.19769.

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The design and verification of memory using the Universal Verification Methodology (UVM) methodology is discussed in this research. The advanced verification architecture uses a minimum number of macros, methods, and classes, and it provides high reusability for UVM tests. It makes use of the common attributes between different memory controllers to generate a common and configurable scoreboard, sequences, stimulus, different UVM components, and test cases. The memory controller provides a constructive control of data between the processor and memory. It provides modern structure and building

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Liao, Chin-Wen, Hsiu-Chou Yu, and Yu-Cheng Liao. "Verification of SPI Protocol Using Universal Verification Methodology for Modern IoT and Wearable Devices." Electronics 14, no. 5 (2025): 837. https://doi.org/10.3390/electronics14050837.

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The Serial Peripheral Interface (SPI) protocol plays a crucial role in wearable and IoT devices, enabling high-speed communication between microcontrollers and peripherals such as sensors, displays, and connectivity modules. With the increasing complexity of modern devices and system-on-chip (SoC) designs, robust verification methods are essential to ensure functionality and reliability. This paper utilizes the Universal Verification Methodology (UVM) to develop a scalable and reusable testbench for SPI verification. The process encompasses test planning, simulation, emulation, and top-level v

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., Geethashree. "Verification of Dual Port RAM using System Verilog and UVM." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 3651–56. http://dx.doi.org/10.22214/ijraset.2021.35847.

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Verification process place a prominent role in the field of SoC and ASIC design. Several verification methodologies are there apart from those Universal Verification Methodology (UVM) is advanced and it is widely used by the industries due to its special features. UVM provides reusable and well-structured verification components by using System Verilog class library. In this work, Dual Port RAM is considered as Design Under Test (DUT). System Verilog and UVM verification environments are developed to verify the DUT. Assertion and cover group coverage are set up with a goal of achieving 100% fr

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Bindu, A. "A rigorous approach to microprocessor verification using UVM." i-manager’s Journal on Electronics Engineering 13, no. 1 (2022): 39. http://dx.doi.org/10.26634/jele.13.1.19344.

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In today's fast-paced technology industry, microprocessors play an increasingly important role in a wide range of applications. However, verifying the correctness of complex microprocessor designs remains a significant challenge. To address this issue, a rigorous approach to microprocessor verification using the Universal Verification Methodology (UVM) is proposed. UVM provides a standardised and scalable approach to verifying digital designs, including microprocessors, and has been widely adopted in the industry. This research proposes a UVM-based verification framework for microprocessors th

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S Y, Janardhana. "Verification of AMBA AHB Protocol using UVM." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 5287–92. http://dx.doi.org/10.22214/ijraset.2021.36203.

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The project aims to verify the AMBA AHB protocol by using universal verification methodology is presented in this paper. Advanced high-performance(AHB) is used for communication of on chip bus which support single clock edge operation wider data 32/64/128 bit can be supported. The new verification constructs can be easily reused for the objected-oriented feature of universal verification methodology (UVM). Verification IP is the one which provides a smart way to verify the AHB Components. The advanced veriﬁcation testbench incorporates the illustrations regarding simulation result are analysed

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Researcher. "UVM METHODOLOGY: INDUSTRY-SPECIFIC APPLICATIONS IN MODERN HARDWARE VERIFICATION." International Journal of Computer Engineering and Technology (IJCET) 15, no. 6 (2024): 20–32. https://doi.org/10.5281/zenodo.14040112.

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The Universal Verification Methodology (UVM) has revolutionized functional verification across multiple industries, demonstrating significant improvements in verification efficiency, cost reduction, and product reliability. This comprehensive analysis examines UVM's implementation impact across semiconductor, automotive, telecommunications, aerospace and defense, healthcare, and consumer electronics sectors, presenting quantitative data from industry leaders. The article reveals remarkable improvements, including an average 76% reduction in verification cycles, 85% improvement in bug detection

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Li, Haoqiang, and Shikai Zuo. "Functional verification of QSPI module based on UVM implementation." Journal of Physics: Conference Series 2645, no. 1 (2023): 012002. http://dx.doi.org/10.1088/1742-6596/2645/1/012002.

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Abstract This article presents a novel functional verification methodology based on the Universal Verification Methodology (UVM) to validate the functionality of the Quick Serial Peripheral Interface (QSPI) module. QSPI serves as a prevalent serial communication protocol widely employed for high-speed data exchange with external flash devices. By using the code coverage and functional coverage reports provided by UVM, we were able to assess how well the test cases covered the design code, identifying the parts of the design that had been adequately tested and those that needed more test covera

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Researcher. "BEST PRACTICES IN UVM VERIFICATION: ENSURING ROBUST AND EFFICIENT DESIGN VALIDATION." International Journal of Computer Engineering and Technology (IJCET) 15, no. 6 (2024): 226–34. https://doi.org/10.5281/zenodo.14055777.

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This article presents a comprehensive exploration of best practices in Universal Verification Methodology (UVM) for ensuring robust and efficient design validation in complex digital systems. We begin by examining the foundational principles of UVM, including its key components such as agents, sequencers, and drivers, and emphasize the importance of modular architecture and reusability. The article then delves into practical strategies for testbench design, covering configuration databases, factory patterns, and transaction-level modeling. We provide in-depth insights into test planning, cover

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Tarasov, I. E. "Application of UVM Methodology to Modeling Precision Digital Signal Processing Devices." Programmnaya Ingeneria 15, no. 11 (2024): 570–77. http://dx.doi.org/10.17587/prin.15.570-577.

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The purpose of the article is to analyze the Universal Verification Methodology (UVM) approach and develop its modification for modeling precision digital signal processing devices as part of periodic signal phase meters. The article proposes a partial implementation of UVM techniques and methods based on general-purpose programming languages, which is distinguished by the presence of a subsystem for metrological evaluation of the characteristics of the simulated measuring device, while the UVM approach, implemented in the Accelera class library in the System Verilog language, assumes the pres

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Moon, Dae-Won, Seung-Hyun Pyo, Dae-Ki Hong, Otgonbayar Bataa, and Erdenekhuu Norinpel. "Assertion-Based Verification of I2C Module Using SystemVerilog." Electronics 14, no. 8 (2025): 1687. https://doi.org/10.3390/electronics14081687.

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In today’s semiconductor verification field, SystemVerilog Assertions (SVAs) are one of the most important methodologies for functional verification. A representative verification technique is Universal Verification Methodology (UVM)-based verification, which utilizes a SystemVerilog class library. On the other hand, Assertion-Based Verification (ABV) using SVA allows hardware designs to be verified without requiring knowledge of SystemVerilog’s Object-Oriented Programming (OOP) concepts or UVM. Its syntax is intuitive and concise, enabling rapid detection of RTL (Register Transfer Level) bugs

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Kaushik Velapa Reddy. "Formal Verification with ABV : A Superior Alternative to UVM for Complex Computing Chips." International Journal of Scientific Research in Computer Science, Engineering and Information Technology 10, no. 6 (2024): 90–98. http://dx.doi.org/10.32628/cseit24106157.

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This article explores the evolution and effectiveness of formal verification enhanced with Assertion-Based Verification (ABV) as a superior alternative to traditional Universal Verification Methodology (UVM) in complex computing chip design. Through analysis of implementation data from major semiconductor companies, including Intel's Core i7 and IBM's POWER processors, the article demonstrates how formal methods achieve up to 100% coverage of critical modules compared to UVM's typical 80-85% coverage. The research presents quantitative evidence of formal verification's advantages, including a

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Mishra, Juhi, Sapna Sorrot, Seema Nayak, and Puneet Mittal. "I2C master RTL development using Verilog HDL and verification using UVM." Spectrum of Emerging Sciences 4, no. 1 (2024): 37–42. http://dx.doi.org/10.55878/ses2024-4-1-7.

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The objective of the project is to develop the I2C Master RTL using VHDL and verify it using UVM. I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices, suitable for short-distance communication between multiple devices. The I2C Master facilitates communication between the Core and various slaves in the chip. The I2C Master IP implemented here is a subset of the full I2C protocol, as some features are not supported. The RTL design of I2C is open source, and its functional verification is performed using System Verilog and UVM.

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D. R, Pooja. "Verification of Wishbone Bus Interface for SoC using System Verilog and UVM." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (2021): 158–63. http://dx.doi.org/10.22214/ijraset.2021.36282.

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The Verification phase carries important role in design cycle of a system on chip. Verification gives with the actual enactment and functionality of a DUT and to verify the design meets the system requirements. This paper present wishbone bus interface for soc integration to interconnect architecture for portable IP cores and test bench is developed in system Verilog and verification is done by both system Verilog verification methodology and universal verification methodology which includes scoreboard, functional coverage and assertion. This paper based on two application to integrate IP core

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Rajesh, Thumma, and Prashanth Pilli. "Design and verification of daisy chain serial peripheral interface using system Verilog and universal verification methodology." TELKOMNIKA (Telecommunication, Computing, Electronics and Control) 21, no. 1 (2023): 168–77. https://doi.org/10.12928/telkomnika.v21i1.24093.

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Serial peripheral interface (SPI) transfers the data between electronic devices like micro controllers and other peripherals. SPI consists of two control lines: select signal and clock signal, and two data lines: input and output. In single master-single slave, the communication is in between master and slave only which will make the design complex and costly, area will increase. In regular SPI mode, the number of chip-select lines is increased if the number of slaves increases. Due to this, the input data received by the master from the slaves are corrupted at master input slave output (MISO)

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Liu, Cong, Xinyu Xu, Zhenjiao Chen, and Binghao Wang. "A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller." Electronics 12, no. 18 (2023): 3821. http://dx.doi.org/10.3390/electronics12183821.

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The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method is no longer applicable. This paper proposes a comprehensive and efficient verification testbench based on the SystemVerilog language and universal verification methodology (UVM) for an instruction Cache (I-Cache) controller. Corresponding testcases are designed for each feature of the I-Cache controller and automatical

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Lupi, M., G. Bergamin, D. Ceresa, et al. "Functional verification for Endcap Concentrator ASICs in the High-Granularity Calorimeter upgrade of CMS." Journal of Instrumentation 20, no. 02 (2025): C02004. https://doi.org/10.1088/1748-0221/20/02/c02004.

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Abstract The High-Granularity Calorimeter (HGCAL) will replace the current CMS Endcap Calorimeter during Long-Shutdown 3. The Endcap Concentrator (ECON) ASICs represent key elements in the readout chain, processing trigger (ECON-T) and data (ECON-D) streams from the HGCROC to the lpGBT. The ECONs will operate in a radiation environment with a High-Energy Hadron (E≥20 MeV) flux up to 2·107 cm-2s-1. This contribution describes the Universal Verification Methodology (UVM)-based functional verification of the ECON ASICs focusing on the re-use of existing components to manage the complexity of the

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Radu, Valentin, Diana Dranga, Catalin Dumitrescu, Alina Iuliana Tabirca, and Maria Cristina Stefan. "Generative AI Assertions in UVM-Based System Verilog Functional Verification." Systems 12, no. 10 (2024): 390. http://dx.doi.org/10.3390/systems12100390.

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This paper investigates the potential of leveraging artificial intelligence to automate and optimize the verification process, particularly in generating System Verilog assertions for an Advance Peripheral Bus verification environment using Universal Verification Methodology. Generative artificial intelligence, such as ChatGPT, demonstrated its ability to produce accurate and valuable assertions by employing text-based prompts and image-fed inputs, significantly reducing the required manual effort. This research presents a way of generating System Verilog assertions using the ChatGPT prompt, p

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Yammanuru, Pavani, and M. Amarnatha Reddy. "Design And Verification Of Advanced Peripheral Bus Protocol Using Uvm." Journal of Artificial Intelligence, Machine Learning and Neural Network, no. 12 (November 22, 2021): 1–9. http://dx.doi.org/10.55529/jaimlnn.12.1.9.

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The System on chip uses advanced micro controller bus architecture is on chip bus introduced by ARM. Advanced peripheral bus is the component of the AMBA bus architecture. APB is low bandwidth, low power and low performance it used to connect the peripherals like UART, Keypad, Timer and other peripheral devices to the bus architecture. This introduces the AMBA APB bus using UVM architecture design. The design created using the Verilog and HDL and tested by Verilog test bench and design is verified using universal verification methodology. In this, we have a master and a slave. The master sends

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Yammanuru, Pavani, and M. Amarnatha Reddy. "Design And Verification Of Advanced Peripheral Bus Protocol Using Uvm." Journal of Artificial Intelligence, Machine Learning and Neural Network, no. 12 (November 22, 2021): 8–16. http://dx.doi.org/10.55529/jaimlnn.12.8.16.

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The System on chip uses advanced micro controller bus architecture is on chip bus introduced by ARM. Advanced peripheral bus is the component of the AMBA bus architecture. APB is low bandwidth, low power and low performance it used to connect the peripherals like UART, Keypad, Timer and other peripheral devices to the bus architecture. This introduces the AMBA APB bus using UVM architecture design. The design created using the Verilog and HDL and tested by Verilog test bench and design is verified using universal verification methodology. In this, we have a master and a slave. The master sends

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CHANDUPATLA, TEJASWI, and Hamedi-Hagh Sotoudeh. "UART IP core Design and Verification using WISHBONE Interface." International Journal of Engineering and Computer Science 13, no. 10 (2024): 26492–97. http://dx.doi.org/10.18535/ijecs/v13i10.4906.

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The organization of communication between the devices is greatly aided by the communication protocol. These protocols have a clear set of guidelines that have been agreed upon by the tools needed for effective communication. A popular protocol for serial communication is UART. The hardware description language for the SV/Verilog UART functional module is designed in this paper. The serial connection capabilities offered by this UART IP CORE enable interaction with modems and other external devices. The Universal Verification Technique is used to undertake functional verification of the UART. B

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Dranga, Diana, and Catalin Dumitrescu. "Artificial Intelligence Application in the Field of Functional Verification." Electronics 13, no. 12 (2024): 2361. http://dx.doi.org/10.3390/electronics13122361.

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The rising interest in Artificial Intelligence and the increasing time invested in functional verification processes are driving the demand for AI solutions in this field. Functional verification is the process of verifying that the Register Transfer Layer (RTL) implementation behaves according to the specifications provided. This is performed using a hardware verification language (HVL) such as SystemVerilog combined with the Universal Verification Methodology (UVM). Reading, identifying the key elements from multiple documentations, creating the verification plan, building the verification e

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Jain, Abhishek, and Richa Gupta. "Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors." VLSI Design 2016 (September 26, 2016): 1–14. http://dx.doi.org/10.1155/2016/7283471.

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In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP) RTL and firmware development. In this paper, we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW) implementation, reference for firmware (FW) implementation, and bit-true certificat

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Shaila C K. "Design & Verification of AI Enabled Reconfigurable SRAM Controller for Automobile Application." Journal of Information Systems Engineering and Management 10, no. 44s (2025): 305–17. https://doi.org/10.52783/jisem.v10i44s.8601.

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The rapid advancements in artificial intelligence (AI) and automotive technology have necessitated the development of sophisticated and intelligent memory management systems. This research focuses on the design and validation of an AI-enabled reconfigurable Static Random-Access Memory (SRAM) controller tailored for automotive applications. By leveraging AI-based algorithms, the proposed controller enhances the efficiency of memory allocation, reduces access time, and optimizes power consumption, thereby improving the overall performance and reliability of automotive electronic systems. The con

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N, Hemanthraju. "A Review on Design Implementation and Verification of AMBA AXI- 4 lite Protocol for SoC Integration." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (2022): 2321–26. http://dx.doi.org/10.22214/ijraset.2022.44313.

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Abstract: The present modern bus protocols used for communication between different functional blocks on a System-on-Chip (Soc) designs face many different challenges among which complexity and communication management are the most important factors. These on-chip communications directly impact performance and functionality, hence depending on the application where the bus protocol is to be used, a perfect communication protocol is chosen. AMBA (Advanced Microcontroller Bus Architecture) provides various types of protocols to be used as IP, of which AXI4 (Advance Extensible Interface), is one

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Kohútka, Lukáš, and Ján Mach. "A New FPGA-Based Task Scheduler for Real-Time Systems." Electronics 12, no. 8 (2023): 1870. http://dx.doi.org/10.3390/electronics12081870.

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This research demonstrates a novel design of an FPGA-implemented task scheduler for real-time systems that supports both aperiodic and periodic tasks. The periodic tasks are automatically restarted once their period has expired without any need for software intervention. The proposed scheduler utilizes the Earliest-Deadline First (EDF) algorithm and is optimized for multi-core CPUs, capable of executing up to four threads simultaneously. The scheduler also provides support for task suspension, resumption, and enabling inter-task synchronization. The design is based on priority queues, which pl

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., Shambhavi. "Router1x3 Protocol Design Implementation and Verification with Virtual Cut through Mechanism for Network on Chip (NoC)." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (2021): 16–24. http://dx.doi.org/10.22214/ijraset.2021.36226.

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Hundreds of processors and memory cores are implemented on a single substrate called the System on Chip (SoC). The SoC with bus-based architecture has restrictions on the processing speed of the system and as the design becomes complex and the issue of scalability arises. Hence NoC is designed to enhance the scalability, data reliability, and processing speed with low power consumption by decoupling communication from computations [1]. Using NoC the IP cores of SoC are connected through on-chip routers and send data to each other through packet switching. The router is a processing chip that d

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Ankitha, Ankitha, and Dr H. V. Ravish Aradhya. "A Python based Design Verification Methodology." Journal of University of Shanghai for Science and Technology 23, no. 06 (2021): 901–11. http://dx.doi.org/10.51201/jusst/21/05358.

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While the UVM-constrained random and coverage-driven verification methodology revolutionized IP and unit-level testing, it falls short of SoC-level verification needs. A solution must extend from UVM and enable vertical (IP to SoC) and horizontal (verification engine portability) reuse to completely handle SoC-level verification. To expedite test-case generation and use rapid verification engines, it must also provide a method to collect, distribute, and automatically amplify use cases. Opting a Python-based Design Verification approach opens the door to various such merits. Cocotb is a very u

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Wadjikar, Ayushi. "Efficient Verification Methodologies for Digital IPs in VLSI Design: A Comparative Study and Analysis." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (2023): 5810–14. http://dx.doi.org/10.22214/ijraset.2023.52627.

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Abstract: Verification of digital IPs in VLSI is an essential step in the design and development of integrated circuits. With the growing complexity of digital systems, the verification process has become increasingly challenging and time-consuming. This survey paper provides an overview of various verification methodologies used in the verification of digital IPs in VLSI. The paper focuses on the design and verification of IP cores using different verification methodologies, assertion-based reconfigurable testbenches, UVM-based testbench architecture for coverage-driven functional verificatio

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Rajashekar Reddy, P., P. Sreekanth, and K. Arun Kumar. "Serial Peripheral Interface-Master Universal Verification Component using UVM." International Journal of Advanced Scientific Technologies in Engineering and Management Sciences 3, no. 6 (2017): 27. http://dx.doi.org/10.22413/ijastems/2017/v3/i6/49102.

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., Darshan. "Verification of Open Core Protocol using System Verilog and UVM." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 5501–10. http://dx.doi.org/10.22214/ijraset.2021.36213.

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The ever-increasing complexity of the integrated circuits design and the scale of the projects are making verification more challenging and time-consuming. As a result, the rapidly expanding VLSI industry necessitates a highly reliable and robust verification mechanism. In this paper, System Verilog Verification and Universal Verification Methodologies were adopted to verify the Accellera Open Core Protocol 3.0 as per specifications. According to the verification plan, the environment was developed under a dynamic approach, and the passive aspects included scoreboard, functional coverage, and

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Kulkarni, Aman, and S. M. Sakthivel. "UVM methodology based functional Verification of SPI Protocol." Journal of Physics: Conference Series 1716 (December 2020): 012035. http://dx.doi.org/10.1088/1742-6596/1716/1/012035.

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Sathyamurthy, Muralikrishna, Felix Neumann, Lukasz Kotynia, and Eckhard Hennig. "UVM-based verification methodology for RFID-enabled smart-sensor systems." Analog Integrated Circuits and Signal Processing 78, no. 1 (2013): 191–207. http://dx.doi.org/10.1007/s10470-013-0225-5.

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S, Someshvar. "A Review on AMBA AHB Lite Protocol and Verification using UVM Methodology." International Journal for Research in Applied Science and Engineering Technology 9, no. 2 (2021): 473–81. http://dx.doi.org/10.22214/ijraset.2021.33120.

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Kashyap, Bidisha, and V. Ravi. "Universal Verification Methodology Based Verification of UART Protocol." Journal of Physics: Conference Series 1716 (December 2020): 012040. http://dx.doi.org/10.1088/1742-6596/1716/1/012040.

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Fiergolski, A. "Simulation environment based on the Universal Verification Methodology." Journal of Instrumentation 12, no. 01 (2017): C01001. http://dx.doi.org/10.1088/1748-0221/12/01/c01001.

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Woo, Jae Hun, Yong Kwan Cho, and Sun Kyu Park. "Universal Verification Methodology Based Register Test Automation Flow." Journal of Nanoscience and Nanotechnology 16, no. 5 (2016): 5316–19. http://dx.doi.org/10.1166/jnn.2016.12252.

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Schulz, Victor Hugo, Gabriel Mariano Marcelino, Laio Oriel Seman, et al. "Universal Verification Platform and Star Simulator for Fast Star Tracker Design." Sensors 21, no. 3 (2021): 907. http://dx.doi.org/10.3390/s21030907.

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Developing star trackers quickly is non-trivial. Achieving reproducible results and comparing different algorithms are also open problems. In this sense, this work proposes the use of synthetic star images (a simulated sky), allied with the standardized structure of the Universal Verification Methodology as the base of a design approach. The aim is to organize the project, speed up the development time by providing a standard verification methodology. Future rework is reduced through two methods: a verification platform that us shared under a free software licence; and the layout of Universal

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Jain, Abhishek, Piyush Kumar Gupta, Hima Gupta, and Sachish Dhar. "Accelerating System Verilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator." International Journal of VLSI Design & Communication Systems 4, no. 6 (2013): 13–25. http://dx.doi.org/10.5121/vlsic.2013.4602.

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Jain, Abhishek. "Generic System Verilog Universal Verification Methodology Based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPS/SOCS." International Journal of VLSI Design & Communication Systems 3, no. 6 (2012): 13–25. http://dx.doi.org/10.5121/vlsic.2012.3602.

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Thumma, Rajesh, and Pilli Prashanth. "Design and verification of daisy chain serial peripheral interface using system Verilog and universal verification methodology." TELKOMNIKA (Telecommunication Computing Electronics and Control) 21, no. 1 (2023): 168. http://dx.doi.org/10.12928/telkomnika.v21i1.24093.

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Sik Cho, Young, and Joo Y. Jung. "The verification of effective leadership style for TQM." International Journal of Quality & Reliability Management 31, no. 7 (2014): 822–40. http://dx.doi.org/10.1108/ijqrm-04-2013-0065.

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Purpose – The purpose of this paper is to verify the universal applicability of total quality management (TQM) across national boundaries. Specifically, the authors examined the validity of the isomorphic nature of TQM leadership style by comparing survey samples from both USA-based firms (n=112) and China-based firms (n=121). Design/methodology/approach – The authors collected the primary data through a survey research method. Confirmatory factor analysis (CFA) and structural equation modeling (SEM) were adopted to test the hypothesized research model. Findings – The study results did not sup

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Shust, Pavel M., and Victor Dostov. "Implementing innovative customer due diligence: proposal for universal model." Journal of Money Laundering Control 23, no. 4 (2020): 871–84. http://dx.doi.org/10.1108/jmlc-01-2020-0007.

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Purpose The purpose of this paper is to present the identification-verification-confirmation of identity (IVCid) model that can be used to retroactively analyze the existing customer identification programs and devise new ones that can be used in face-to-face or non-face-to-face environment. Design/methodology/approach This paper outlines the main elements of the customer due diligence (CDD) process and identifies those which may present a barrier to the customers. It then outlines the IVCid model. The model is used to analyze existing CDD approaches in physical presence, using reliable databa

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Choromański, Włodzimierz, Iwona Grabarek, and Maciej Kozłowski. "Integrated Design of a Custom Steering System in Cars and Verification of Its Correct Functioning." Energies 14, no. 20 (2021): 6740. http://dx.doi.org/10.3390/en14206740.

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The subject of this article is the design of a nonstandard steering system in cars. The applied methodology takes into account universal design, ensuring the greatest possible adaptation of the steering system to potential users, and at the same time, thanks to the specific nature of the designed steering device, it also assumes a special approach allowing for individual adjustment of the steering system to the needs and limitations of drivers with lower-limb disabilities. It is implemented through the “custom design” methodology. This article presents the impact of the design features of the

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Iwaniak, Michał, Tamara Zalewska, and Patryk Sapiega. "Quality control of time-series seawater temperature and wave data adapted to the regional conditions of the Baltic Sea." Oceanological and Hydrobiological Studies 54, no. 1 (2025): 59–78. https://doi.org/10.26881/oahs-2025.1.06.

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Marking outliers using available methods for identifying such observations should be a standard practice in the database management process. The research aimed to adapt universal data quality control tools and tests to their applicability in the southern Baltic Sea by setting new limit values, enabling the detection of erroneous or suspicious data, which can be subjected to expert verification at a later stage. This verification stage may include analysing current conditions and processes and determining the values measured at a given time and space. Our research has proven that using global a

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Roniger, Luis, and Leonardo Senkman. "The Logic of Conspiracy Thought." ProtoSociology 36 (2019): 542–69. http://dx.doi.org/10.5840/protosociology20193624.

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This article analyzes the logic of conspiracy theories, stressing that it would be erroneous to assume that such theories about collusions and intrigues are irrational in nature. On the contrary, they operate on a logic that is no less coherent than scientific discourse, although it differs from the latter in its verification and discard methodology as well as in its mobilizing role. Being part of a larger research that explains the recurrent spread of conspiracy narratives in one region of the world, elucidating their historical and contemporary conditions of crystallization, the article clai

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Pitera, Rafał. "Verification of the effectiveness of discrimination models for forecasting bankruptcy of enterprises." Scientific Papers of Silesian University of Technology. Organization and Management Series 2023, no. 178 (2023): 497–511. http://dx.doi.org/10.29119/1641-3466.2023.178.28.

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Purpose: An attempt to evaluate the effectiveness of financial analysis tools used to assess financial health and to forecast bankruptcy. Methodology: The study used 31 of the most popular discriminatory models for bankruptcy prediction. The effectiveness of early warning models has been evaluated on the basis of financial data of economic entities operating on the territory of the Republic of Poland. The sample of the enterprises has comprised a total of 172 entities – both bankrupt and operating in good financial condition, located in 16 provinces. The data period was 2011-2020. The companie

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Belostotskiy, Alexandr M., Sergey I. Dubinsky, Irina N. Afanasyeva, et al. "External Extreme Impacts on NPP Constructions – Methodology of Computational Simulation." Advanced Materials Research 1040 (September 2014): 472–77. http://dx.doi.org/10.4028/www.scientific.net/amr.1040.472.

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In accordance with results of analysis of state-of-the-art theoretical and experimental research works, analysis and synthesis of data on the impact of extreme impacts on structures of existing nuclear power plants (including NPP "Fukushima-1", Japan), and other unique objects, the existing regulations, corresponding design codes and procedures do not fully take into account the specific definition of extreme (special) external loads and impacts on the main building of NPP, and, therefore, require clarification and development. The distinctive paper is devoted to advanced methods of analysis,

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