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Journal articles on the topic 'Variable Gain Amplifier (VGA)'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Alam, M. J., Mohammad Arif Sobhan Bhuiyan, Md Torikul Islam Badal, Mamun Bin Ibne Reaz, and Noorfazila Kamal. "Design of a low-power compact CMOS variable gain amplifier for modern RF receivers." Bulletin of Electrical Engineering and Informatics 9, no. 1 (2020): 87–93. http://dx.doi.org/10.11591/eei.v9i1.1468.

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The demand for portability has speeded up the design of low-power electronic communication devices. Variable gain amplifier (VGA) is one of the most vulnerable elements of every modern receiver for the proper baseband processing of the signal. CMOS VGAs are generally suffered from low bandwidth and small gain range. In this research, a two-stage class AB VGA, each stage comprising of a direct transconductance amplifier and a linear transimpedance amplifier, is designed in Silterra 0.13-μm CMOS utilizing Mentor Graphics environment. The post-layout simulation results reveal that the VGA design

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2

Sun, Zhengyu, and Yuepeng Yan. "Design of a 2 GHz Linear-in-dB Variable-Gain Amplifier with 80-dB Gain Range." Active and Passive Electronic Components 2014 (2014): 1–7. http://dx.doi.org/10.1155/2014/434189.

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A broadband linear-in-dB variable-gain amplifier (VGA) circuit is implemented in 0.18 μm SiGe BiCMOS process. The VGA comprises two cascaded variable-gain core, in which a hybrid current-steering current gain cell is inserted in the Cherry-Hooper amplifier to maintain a broad bandwidth while covering a wide gain range. Postlayout simulation results confirm that the proposed circuit achieves a 2 GHz 3-dB bandwidth with wide linear-in-dB gain tuning range from −19 dB up to 61 dB. The amplifier offers a competitive gain bandwidth product of 2805 GHz at the maximum gain for a 110-GHz ftBiCMOS tech

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3

Arbet, Daniel, Viera Stopjaková, Martin Kováč, Lukáš Nagy, Matej Rakús, and Michal Šovčík. "130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications." Journal of Circuits, Systems and Computers 26, no. 08 (2017): 1740003. http://dx.doi.org/10.1142/s0218126617400035.

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In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the

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4

Cortes, Fernando Paixão, and Sergio Bampi. "A 40 MHz 70 dB Gain Variable Gain Amplifier Design Using the gm/ID Design Method." Journal of Integrated Circuits and Systems 4, no. 1 (2009): 7–12. http://dx.doi.org/10.29292/jics.v4i1.290.

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This paper addresses the design and post-fabrication measurements of a 40 MHz CMOS Variable Gain Amplifier (VGA) with a 0 to 70 dB gain control range, using the gm/ID design methodology. The VGA architecture is based on a differential pair stage with an automatic continuous-time offset cancellation circuitry, providing an input offset voltage tolerance up to 50 mV. The 3-stage VGA was designed and fabricated through MOSIS service in an IBM 0.18 μm CMOS process. The VGA dissipates 2.6 mA from a 1.8 V supply, with 34,840 μm2 circuit area, excluding bond-pads.

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5

Zhang, Wei Jia, and Bo Wang. "A SiGe HBT Variable Gain Amplifier for Wireless Receiver System with On-Chip Filter." Applied Mechanics and Materials 155-156 (February 2012): 167–70. http://dx.doi.org/10.4028/www.scientific.net/amm.155-156.167.

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A using SiGe HBT variable gain amplifier (VGA) with filtering for wireless receiver system is presented in this paper. The VGA consists of three stages. The first stage is the gain control stage, and the second stage is the fixed gain stage. The third is the GM-C filter. The VGA is driven by a 3.3-V power supply, and linear gain control range varying is from 26 dB to 62dB. When control voltage varies from 0 to 1.8V. The input 1-dB compression point is -4dBm at minimum gain. The VGA is fabricated in a 0.5 μm = 80GHz and =90GHz silicon germanium heterojunction transistor technology.

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6

Hu, Shan Wen, Tao Chen, Huai Gao, Long Xing Shi, and G. P. Li. "An Advanced Traveling Wave Matching Network for DC-12GHz Variable Gain Amplifier Design." Applied Mechanics and Materials 321-324 (June 2013): 331–35. http://dx.doi.org/10.4028/www.scientific.net/amm.321-324.331.

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A traveling wave matching (TWM) network is proposed for broadband variable gain amplifier design. The TWM network lessens input return loss and noise figure dependence on VGA’s gain, which is adjusted by biasing of the gain control circuit. A wide band (DC to 12 GHz) VGA with the novel TWM network as input matching is implemented in 2μm InGaP/GaAs HBT (fT of 29.5GHz) technology with die size of 1×2 mm2. As gain control voltage sweeps, the VGA shows a gain tuned from -15 dB to 15 dB and an average noise figure ranging from 8dB to 6.5dB, while S11 (lower than -20dB) and S22 (lower than -10dB) al

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7

Liu, Yu Yang. "A Novel Circuit Design of the Wideband VGA in CMOS." Advanced Materials Research 1049-1050 (October 2014): 682–86. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.682.

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In this paper, a wideband variable-gain amplifier (VGA) in CMOS for ultra wideband (UWB) system is designed. The operation frequency of the VGA is 4.2-4.8GHz, and the gain is continuously adjustable between 0 and 30dB. Cascaded Cherry-Hooper with two stages is adopted as the core unit of the VGA, and a temperature compensation circuit is used to reduce the effect of temperature on the performance of the system. The simulation shows that the temperature compensation circuit can compensate the effect of the temperature very well, and the noise figure of the wideband VGA can meet the requirements

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8

del Pino, J., Sunil L. Khemchandani, D. Galante-Sempere, and C. Luján-Martínez. "A Compact Size Wideband RF-VGA Based on Second Generation Controlled Current Conveyors." Electronics 9, no. 10 (2020): 1600. http://dx.doi.org/10.3390/electronics9101600.

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This paper presents a methodology to design a wideband radio frequency variable gain amplifier (RF-VGA) in a low-cost SiGe BiCMOS 0.35 μm process. The circuit uses two Class A amplifiers based on second-generation controlled current conveyors (CCCII). The main feature of this circuit is the wideband input match along with a reduced NF (5.5–9.6 dB) and, to the authors’ knowledge, the lowest die footprint reported (62 × 44 μm2 area). The implementation of the RF-VGA based on CCCII allows a wideband input match without the need of passive elements. Due to the nature of the circuit, when the gain

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9

Hu, Zhengfei, Li Zhang та Mindi Huang. "A 2.9 mm2 Highly Integrated Low Noise GPS Receiver in 0.18-μm CMOS Technology". Journal of Circuits, Systems and Computers 24, № 03 (2015): 1550036. http://dx.doi.org/10.1142/s021812661550036x.

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An L1 band highly integrated low noise GPS receiver in 0.18-μm CMOS is presented in this paper. The receiver adopts double conversion structure and two dynamic range control modes of variable gain amplifier (VGA) and programmable gain amplifier (PGA). The receiver includes the blocks of LNA, down-conversion mixers, band pass filter, received signal strength indicator (RSSI), VGA, PGA, 2-bit ADC, two frequency synthesizers and so on. The LNA adopts source inductive degeneration technique to achieve good noise performance, and a novel positive feedback capacitor is introduced to enhance gain. Th

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10

CHEN, ZHIMING, YUANJIN ZHENG, and XIAOJUN YUAN. "CMOS LOW-POWER ANALOGUE BASEBAND CIRCUITS FOR A NON-COHERENT LOW DATA RATE IR-UWB RECEIVER." Journal of Circuits, Systems and Computers 20, no. 01 (2011): 45–55. http://dx.doi.org/10.1142/s0218126611007062.

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A low-power analogue baseband circuit for a low data-rate impulse radio ultra-wideband (IR-UWB) receiver is designed and implemented in a 0.18 μm CMOS technology, including a variable-gain amplifier (VGA), a received signal strength indicator (RSSI), and a limiting amplifier (LA). The VGA has gain range from -9 to 63 dB and bandwidth from 31 to 187 MHz. An input P1dB of -15.4 dBm is achieved at 0 dB gain. The RSSI has a dynamic range of approximately 70 dB. The RSSI linearity error is within ±1.2 dB for an input power from -77.5 dBm to -36.2 dBm. By adjusting the VGA gain and the LA threshold,

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11

Pan, Quan, Xiongshi Luo, Zhenghao Li, et al. "A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS." Journal of Semiconductors 43, no. 7 (2022): 072401. http://dx.doi.org/10.1088/1674-4926/43/7/072401.

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Abstract This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ transimpedance gain, 20.4-GHz −3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overc

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12

Lahiani, Sawssen, Samir Ben Salem, Houda Daoud, and Mourad Loulou. "A CMOS Low-Power Digital Variable Gain Amplifier Design for a Cognitive Radio Receiver “Application for IEEE 802.22 Standard”." Journal of Circuits, Systems and Computers 27, no. 09 (2018): 1850135. http://dx.doi.org/10.1142/s0218126618501359.

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This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA). The proposed circuit based on transconductance, gm, amplifier and a transconductance amplifier is analyzed and designed for a cognitive radio receiver. The variable-gain amplifier (VGA) proposed consists of a digital control block, an auxiliary pair to retain a constant current density, and offers a gain-independent bandwidth (BW). A novel cell structure is designed for high gain, high BW, low power consumption and low Noise Figure (NF). The Heuristic Method is used to optimize the proposed circuit performance

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13

Zhang, Qingfeng, Chenxi Zhao, and Kai Kang. "A Wideband Reconfigurable CMOS VGA Based on an Asymmetric Capacitor Technique with a Low Phase Variation." Electronics 11, no. 5 (2022): 751. http://dx.doi.org/10.3390/electronics11050751.

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This paper presents a wideband digitally controlled variable gain amplifier (VGA) with a reconfigurable gain tuning range and gain step in a 65 nm CMOS process. A unique asymmetric capacitor-based reconfigurable technique is proposed to extend the gain tuning range and realize gain step reconfiguration. An active neutralization topology based on a stackless transistor is utilized to compensate for the additional phase shift introduced by the gain tuning. Moreover, a current-type digital-to-analog converter (DAC) is also integrated for easier precise gain control. With the asymmetric capacitor

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14

Langhammer, Lukas, Roman Sotner, Jan Dvorak, Jan Jerabek, and Peter A. Ushakov. "Novel Reconnection-Less Reconfigurable Filter Design Based on Unknown Nodal Voltages Method and Its Fractional-Order Counterpart." Elektronika ir Elektrotechnika 25, no. 3 (2019): 34–38. http://dx.doi.org/10.5755/j01.eie.25.3.23673.

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A novel solution of reconnection-less electronically reconfigurable filter is introduced in the paper. The filter is designed based on unknown nodal voltages method (MUNV) using operational transconductance amplifiers (OTAs) and variable gain amplifier (VGA). The structure can provide all-pass, band-stop, high-pass 2nd order functions, high-pass function of the 1st order and direct transfer from the same topology without requirement of manual reconnection. The proposed structure also offers the electronic control of the pole frequency. Moreover, fractional-order design of the proposed filter i

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15

Shin, Gibeom, Kyunghwan Kim, Kangseop Lee, Hyun-Hak Jeong, and Ho-Jin Song. "An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS." Electronics 10, no. 7 (2021): 804. http://dx.doi.org/10.3390/electronics10070804.

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This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consu

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16

Zhang, Da Hui, Ze Dong Nie, Feng Guan, and Lei Wang. "An Energy-Efficient Receiver for Human Body Communication." Applied Mechanics and Materials 195-196 (August 2012): 84–89. http://dx.doi.org/10.4028/www.scientific.net/amm.195-196.84.

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A low-power, wideband signaling receiver for data transmission through a human body was presented in this paper. The receiver utilized a novel implementation of energy-efficient wideband impulse communication that uses the human body as the transmission medium, provides low power consumption, high reception sensitivity. The receiver consists of a low-noise amplifier, active balun, variable gain amplifier (VGA) Gm-C filter, comparator, and FSK demodulator. It was designed with 0.18um CMOS process in an active area of 1.54mm0.414mm. Post-simulation showed that the receiver has a gain range of-2d

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17

Wang, Ming Fei, Peng Cao, Hui Yong Sun, and Ming Jin Xu. "Optimal Design of Broadband and Large Dynamic Range IF AGC Circuit." Advanced Materials Research 722 (July 2013): 194–97. http://dx.doi.org/10.4028/www.scientific.net/amr.722.194.

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The bandwidth and the dynamic range is the critical performance parameter of IF AGC (Intermediate Frequency Automatic Gain Control) in wireless receiver. In order to design broadband and large dynamic range IF AGC circuit, the main functions and performance of the VGA (Variable Gain Amplifier) AD8367 and the logarithmic amplifier AD8318 are analyzed. A kind of a broadband large dynamic range IF AGC module is designed by using these two chips. Detail circuit is provided; key technology of AGC module is analyzed and the actual testing results are offered. Compared to the traditional AGC circuit,

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18

Nagulapalli, Rajasekhar, Khaled Hayatleh, and Steve Barker. "A VGA Linearity Improvement Technique for ECG Analog Front-End in 65nm CMOS." Journal of Circuits, Systems and Computers 29, no. 07 (2019): 2050113. http://dx.doi.org/10.1142/s0218126620501133.

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This paper presents a 65[Formula: see text]nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5–100[Formula: see text]mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loop-gain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with po

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19

Han, Jingyu, Yu Jiang, Guiliang Guo, and Xu Cheng. "A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process." Electronics 9, no. 5 (2020): 831. http://dx.doi.org/10.3390/electronics9050831.

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A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generato

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20

Tang, Yuxuan, Yulang Feng, He Hu, et al. "A Wideband Noise and Harmonic Distortion Canceling Low-Noise Amplifier for High-Frequency Ultrasound Transducers." Sensors 21, no. 24 (2021): 8476. http://dx.doi.org/10.3390/s21248476.

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This paper presents a wideband low-noise amplifier (LNA) front-end with noise and distortion cancellation for high-frequency ultrasound transducers. The LNA employs a resistive shunt-feedback structure with a feedforward noise-canceling technique to accomplish both wideband impedance matching and low noise performance. A complementary CMOS topology was also developed to cancel out the second-order harmonic distortion and enhance the amplifier linearity. A high-frequency ultrasound (HFUS) and photoacoustic (PA) imaging front-end, including the proposed LNA and a variable gain amplifier (VGA), w

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21

Nam, Hyosung, Taejoo Sim, and Junghyun Kim. "A 2.4 GHz 20 W 8-channel RF Source Module with Solid-State Power Amplifiers for Plasma Generators." Electronics 9, no. 9 (2020): 1378. http://dx.doi.org/10.3390/electronics9091378.

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This paper presents a novel multi-channel type RF source module with solid-state power amplifiers for plasma generators. The proposed module is consisted of a DC control part, RF source generation part, and power amplification part. A 2-stage power amplifier (PA) is combined with a gallium arsenide hetero bipolar transistor (GaAs HBT) as a drive PA and a gallium nitride high electron mobility transistor (GaN HEMT) as a main PA, respectively. By employing 8 channels, the proposed module secures better area coverage on the wafer during semiconductor processes such as chemical vapor deposition (C

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22

Esteban Eraso, Uxua, Carlos Sánchez-Azqueta, Concepción Aldea, and Santiago Celma. "A 19.5 GHz 5-Bit Digitally Programmable Phase Shifter for Active Antenna Arrays." Electronics 12, no. 13 (2023): 2862. http://dx.doi.org/10.3390/electronics12132862.

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This paper presents the design of a new phase shifter to be used in a receiver of active antenna array operating in the range from 17 GHz to 22 GHz. Beamforming is achieved by controlling the phase of the signal in each radiant element. In this context, the phase shift is obtained by the combination of a quadrature signal generator (QSG) and a variable gain amplifier (VGA). This work is focused on the design of a VGA which has a set of dummy transistors to keep the input and output impedance constant. The phase shifter is digitally programmable using a 5-bit word. The system was laid out using

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23

Zhang, Kai, Ting Li, Haisong Li, Jie He, and Weidong Xu. "Low-Power and High-Precision Readout Circuit Design for Micro-Electromechanical Systems (MEMS) Acceleration Sensors." Journal of Nanoelectronics and Optoelectronics 18, no. 2 (2023): 130–37. http://dx.doi.org/10.1166/jno.2023.3390.

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MEMS acceleration sensors are widely used in Internet of Things, electronic machinery, aerospace and other fields with outstanding advantages such as small size, high reliability, intelligence and high integration. Traditional MEMS acceleration sensors limit their applications due to high-power consumption and low-precision; the standby time and service life are being increased in order to study the low-power and high-precision MEMS acceleration sensor readout, this paper adopts the Fully Differential Switched Capacitor-Variable Gain Amplifier (FDSC-VGA) instead of the traditional high-power C

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24

Hyun, Eugin, Young-Seok Jin, and Jong-Hun Lee. "Design and Implementation of 24 GHz Multichannel FMCW Surveillance Radar with a Software-Reconfigurable Baseband." Journal of Sensors 2017 (2017): 1–11. http://dx.doi.org/10.1155/2017/3148237.

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We designed and developed a 24 GHz surveillance FMCW (Frequency Modulated Continuous Wave) radar with a software-reconfigurable baseband. The developed radar system consists of transceiver, two selectable transmit antennas, eight parallel receive antennas, and a back-end module for data logging and to control the transceiver. The architecture of the developed radar system can support various waveforms, gain control of receive amplifiers, and allow the selection of two transmit antennas. To do this, we implemented the transceiver using a frequency synthesizer device and a two-step VGA (Variable

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25

Zhao, Yinan, Jinwu Zhuang, Zhihao Ye, Zhiliang Qian, and Fang Peng. "Simulation of Steady-State Temperature Rise of Electric Heating Field of Wireless Sensor Circuit Fault Current Trigger." Journal of Sensors 2021 (September 30, 2021): 1–11. http://dx.doi.org/10.1155/2021/8359504.

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This article analyzes the structure of the wireless sensor circuit, considering the balance of power consumption, integration, area, noise, etc., and adopts a radio frequency wireless sensor circuit with a low-IF structure. Through the analysis and comparison of traditional analog current trigger and digital current trigger structure, the feed-forward current trigger structure is selected, which is composed of received signal strength indicator (RSSI) and variable gain amplifier (VGA), which achieves low power consumption, fast stabilization time, and wide dynamic range design. The received si

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26

Sotner, Roman, Jan Jerabek, Norbert Herencsar, Jiun-Wei Horng, Kamil Vrba, and Tomas Dostal. "Simple Oscillator with Enlarged Tunability Range Based on ECCII and VGA Utilizing Commercially Available Analog Multiplier." Measurement Science Review 16, no. 2 (2016): 35–41. http://dx.doi.org/10.1515/msr-2016-0006.

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Abstract This work presents an example of implementation of electronically controllable features to an originally unsuitable circuit structure of oscillator. Basic structure does not allow any electronic control and has mutually dependent condition of oscillation (CO) and frequency of oscillation (FO) if only values of passive elements are considered as the only way of control. Utilization of electronically controllable current conveyor of second generation (ECCII) brings control of CO independent of FO. Additional application of voltage amplifier with variable gain in both polarities (voltage

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27

Mansour, Nehad, Mohamed Elnozahi, and Hani Ragaai. "Parasitic-Aware Simulation-Based Optimization Design Tool for Current Steering VGAs." Electronics 12, no. 1 (2022): 132. http://dx.doi.org/10.3390/electronics12010132.

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Designing millimeter-wave variable gain amplifiers (VGAs) is very challenging owing to the parasitic effects of the interconnects of both active and passive devices. An automated parasitic-aware optimization RF design tool is proposed in this paper to address this challenge. The proposed tool considers the parasitic effects prior to layout. It employs a knowledge-aware optimization technique. The augmentation between parasitic-aware and knowledge-aware techniques speeds up the design process and leads to a design as close to the final design after finalizing the layout. The proposed tool gives

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Xu, Haojie, Jiarui Liu, Zhiyu Wang, Min Zhou, Jiongjiong Mo, and Faxin Yu. "An Area-Efficient and Programmable 4 × 25-to-28.9 Gb/s Optical Receiver with DCOC in 0.13 µm SiGe BiCMOS." Electronics 9, no. 6 (2020): 1032. http://dx.doi.org/10.3390/electronics9061032.

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In this paper, we present an area-efficient noise-optimized programmable 4 × 25-to-28.9 Gb/s optical receiver. Both high- and low-power modes are available for the receiver to meet different requirements. Emitter degeneration provides the input transimpedance amplifier (TIA) stage with improved stability. The noise of the TIA with emitter degeneration is analyzed, and an improved noise optimization method for the TIA is proposed. A sink current source with emitter degeneration in a DC offset cancellation (DCOC) loop reduces the noise introduced by the DCOC circuit. Moreover, with parasitic cap

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Asl, S. Ali Hosseini, Behnam S. Rikan, Arash Hejazi, et al. "A Design of Analog Front-End with DBPSK Demodulator for Magnetic Field Wireless Network Sensors." Sensors 22, no. 19 (2022): 7217. http://dx.doi.org/10.3390/s22197217.

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This paper presents an on-chip fully integrated analog front-end (AFE) with a non-coherent digital binary phase-shift keying (DBPSK) demodulator suitable for short-range magnetic field wireless communication applications. The proposed non-coherent DBPSK demodulator is designed based on using comparators to digitize the received differential analog BPSK signal. The DBPSK demodulator does not need any phase-lock loop (PLL) to detect the data and recover the clock. Moreover, the proposed demodulator provides the detected data and the recovered clock simultaneously. Even though previous studies ha

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del Pino, Javier, Sunil L. Khemchandani, Mario San-Miguel-Montesdeoca, et al. "A 17.8–20.2 GHz Compact Vector-Sum Phase Shifter in 130 nm SiGe BiCMOS Technology for LEO Gateways Receivers." Micromachines 14, no. 6 (2023): 1184. http://dx.doi.org/10.3390/mi14061184.

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This paper presents a novel and compact vector modulator (VM) architecture implemented in 130 nm SiGe BiCMOS technology. The design is suitable for use in receive phased arrays for the gateways of major low Earth orbit (LEO) constellations that operate in the 17.8 to 20.2 GHz frequency range. The proposed architecture uses four variable gain amplifiers (VGA) that are active at any given time and are switched to generate the four quadrants. Compared to conventional architectures, this structure is more compact and produces double the output amplitude. The design offers 6-bit phase control for 3

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31

George, Deepa, and Saurabh Sinha. "BiCMOS Colpitts oscillator for vector-sum interpolators." Microelectronics International 33, no. 2 (2016): 87–93. http://dx.doi.org/10.1108/mi-03-2015-0029.

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Purpose The demand for higher bandwidth has resulted in the development of mm-wave phased array systems. This paper aims to explore a technique that could be used to feed the individual antennas in a mm-wave phased array system with the appropriate phase shifted signal to achieve the required directivity. It presents differential Colpitts oscillators at 5 and 60 GHz that can provide differential output signals to the quadrature signal generators in the proposed phase shifter system. Design/methodology/approach The phase shifter system comprises a differential Colpitts voltage controlled oscill

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32

Abdalla, Kasim K. "Condition of phase angle for a new VDGA-based multiphase variable phase shift oscillator from 0^o to 90^o." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (2020): 3801. http://dx.doi.org/10.11591/ijece.v10i4.pp3801-3810.

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A novel interesting type of variable phase angle voltage mode oscillator using modern building block has been presented in this paper. The new proposed oscillator configuration which uses four voltage differencing gain amplifier (VDGA) and two grounded capacitors can generate two sinusoidal signals that change out of phase by 0 to 90 degree. It has four floating and explicit voltage mode outputs where every two outputs have the same phase. The circuit is characterized by (i) the condition of phase angle of the oscillation (PO) (this concept is introduced for the first time in this paper) can b

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Zhang, Dianwei, Fei Chu, Wu Wen, and Ze Cheng. "A large gain variable range, high linearity, lownoise, low DC offset VGAs used in BD system." MATEC Web of Conferences 355 (2022): 03050. http://dx.doi.org/10.1051/matecconf/202235503050.

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In this paper, a large gain variable range, high linearity, low noise, low DC offset VGAs with a simple gain-dB variable circuit are introduced. In the VGAs chain, the last and the first VGAs employ Bipolar transistors, to improve the linearity and noise characteristics. And the middle three stages VGAs employ MOS transistors. The whole circuitry is designed in 0.35um BiCMOS process, including variable gain amplifiers (VGAs) , fixed gain amplifiers , gain control and DC offset cancellation parts. The automatic gain control loop (AGC) provides a process independent gain variable range of 60dB (

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34

Zhang, Jing Zhi. "A 520MHz Wideband Variable Gain Amplifier." Applied Mechanics and Materials 556-562 (May 2014): 1564–67. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1564.

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The design and realization of a wideband variable gain amplifier for RF system is presented. The cascade of LNA and controllable attenuation makes the design have a 0-90dB gain adjustment range. Special care is devoted to the solution of typical problems encountered in the design of the amplifier, such as signal shielding and power supply decoupling. The amplifier uses passive amplitude-frequency equalization, 0.1-460MHz band variation is less than 1dB, the 3dB bandwidth is up to 520MHz. The noise characteristic is low, the total input referred noise is less than 15.5nV⁄√¯Hz.

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Balteanu, F., and M. Cloutier. "Charge-pump controlled variable gain amplifier." Electronics Letters 34, no. 9 (1998): 838. http://dx.doi.org/10.1049/el:19980644.

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Cho, Young-Kyun, Young-Deuk Jeon, and Jong-Kee Kwon. "Switched-Capacitor Variable Gain Amplifier with Operational Amplifier Preset Technique." ETRI Journal 31, no. 2 (2009): 234–36. http://dx.doi.org/10.4218/etrij.09.0208.0288.

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Choi, Ye-Ji, and Jee-Youl Ryu. "Design of Low-Power Variable Gain Amplifier." Journal of Institute of Control, Robotics and Systems 28, no. 1 (2022): 1–5. http://dx.doi.org/10.5302/j.icros.2022.21.0138.

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Asgari, Vahid, and Leonid Belostotski. "Wideband 28-nm CMOS Variable-Gain Amplifier." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 1 (2020): 37–47. http://dx.doi.org/10.1109/tcsi.2019.2942492.

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Chaudhry, Q., R. Alidio, G. Sakamoto, and T. Cisco. "A SiGe MMIC variable gain cascode amplifier." IEEE Microwave and Wireless Components Letters 12, no. 11 (2002): 424–25. http://dx.doi.org/10.1109/lmwc.2002.805533.

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Thanachayanont, Apinunt. "Low-voltage compact CMOS variable gain amplifier." AEU - International Journal of Electronics and Communications 62, no. 6 (2008): 413–20. http://dx.doi.org/10.1016/j.aeue.2007.06.002.

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41

El-Gabaly, A. M., and C. E. Saavedra. "Wideband variable gain amplifier with noise cancellation." Electronics Letters 47, no. 2 (2011): 116. http://dx.doi.org/10.1049/el.2010.3226.

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42

Floc'h, J. M., and L. Desclos. "Variable gain amplifier with traveling wave structure." Microwave and Optical Technology Letters 7, no. 12 (1994): 539–42. http://dx.doi.org/10.1002/mop.4650071203.

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Choi, Inyoung, Heesong Seo, and Bumman Kim. "Accurate dB-Linear Variable Gain Amplifier With Gain Error Compensation." IEEE Journal of Solid-State Circuits 48, no. 2 (2013): 456–64. http://dx.doi.org/10.1109/jssc.2012.2227606.

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CHA, S. "A CMOS IF Variable Gain Amplifier with Exponential Gain Control." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 2 (2005): 410–15. http://dx.doi.org/10.1093/ietfec/e88-a.2.410.

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Chang, C. C., M. L. Lin, and S. I. Liu. "CMOS current-mode exponential-control variable-gain amplifier." Electronics Letters 37, no. 14 (2001): 868. http://dx.doi.org/10.1049/el:20010593.

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Mahdavi, S., A. Soltani, M. Jafarzadeh, and T. Moradi Khanshan. "A novel method to design variable gain amplifier." Journal of Fundamental and Applied Sciences 8, no. 2 (2016): 1003. http://dx.doi.org/10.4314/jfas.v8i2s147.

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De Ridder, T., P. Ossieur, X. Yin, et al. "BiCMOS variable gain transimpedance amplifier for automotive applications." Electronics Letters 44, no. 4 (2008): 287. http://dx.doi.org/10.1049/el:20083101.

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Fujimoto, Y., H. Tani, M. Maruyama, H. Akada, H. Ogawa, and M. Miyamoto. "A low-power switched-capacitor variable gain amplifier." IEEE Journal of Solid-State Circuits 39, no. 7 (2004): 1213–16. http://dx.doi.org/10.1109/jssc.2004.829919.

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Thanachayanont, A., and P. Naktongkul. "Low-voltage wideband compact CMOS variable gain amplifier." Electronics Letters 41, no. 2 (2005): 51. http://dx.doi.org/10.1049/el:20057110.

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Vintola, V. T. S., M. J. Matilainen, S. J. K. Kalajo, and E. A. Jarvinen. "Variable-gain power amplifier for mobile WCDMA applications." IEEE Transactions on Microwave Theory and Techniques 49, no. 12 (2001): 2464–71. http://dx.doi.org/10.1109/22.971637.

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