Relevant bibliographies by topics / Variable gain amplifiers (VGA)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Variable gain amplifiers (VGA)'

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Published: 4 June 2021
Last updated: 16 February 2022

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Journal articles on the topic "Variable gain amplifiers (VGA)"

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Alam, M. J., Mohammad Arif Sobhan Bhuiyan, Md Torikul Islam Badal, Mamun Bin Ibne Reaz, and Noorfazila Kamal. "Design of a low-power compact CMOS variable gain amplifier for modern RF receivers." Bulletin of Electrical Engineering and Informatics 9, no. 1 (2020): 87–93. http://dx.doi.org/10.11591/eei.v9i1.1468.

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The demand for portability has speeded up the design of low-power electronic communication devices. Variable gain amplifier (VGA) is one of the most vulnerable elements of every modern receiver for the proper baseband processing of the signal. CMOS VGAs are generally suffered from low bandwidth and small gain range. In this research, a two-stage class AB VGA, each stage comprising of a direct transconductance amplifier and a linear transimpedance amplifier, is designed in Silterra 0.13-μm CMOS utilizing Mentor Graphics environment. The post-layout simulation results reveal that the VGA design achieves the widest bandwidth of 200 MHz and high gain range from -33 to 32 dB. The VGA dissipates only 2mW from a single 1.2 V DC supply. The core chip area of the VGA is also only 0.026 mm2 which is also the lowest compared to recent researches. Such a VGA will be a very useful module for all modern communication devices.
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del Pino, J., Sunil L. Khemchandani, D. Galante-Sempere, and C. Luján-Martínez. "A Compact Size Wideband RF-VGA Based on Second Generation Controlled Current Conveyors." Electronics 9, no. 10 (2020): 1600. http://dx.doi.org/10.3390/electronics9101600.

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This paper presents a methodology to design a wideband radio frequency variable gain amplifier (RF-VGA) in a low-cost SiGe BiCMOS 0.35 μm process. The circuit uses two Class A amplifiers based on second-generation controlled current conveyors (CCCII). The main feature of this circuit is the wideband input match along with a reduced NF (5.5–9.6 dB) and, to the authors’ knowledge, the lowest die footprint reported (62 × 44 μm2 area). The implementation of the RF-VGA based on CCCII allows a wideband input match without the need of passive elements. Due to the nature of the circuit, when the gain is increased, the power consumption is reduced. The architecture is suitable for designing wideband, low-power, and low-noise amplifiers. The proposed design achieves a tunable gain of 6.7–18 dB and a power consumption of 1.7 mA with a ±1.5 V DC supply. At maximum gain, the proposed RF-VGA covers from DC up to 1 GHz and can find application in software design radios (SDRs), the low frequency medical implant communication system (MICS) or industrial, scientific, and medical (ISM) bands.
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Cortes, Fernando Paixão, and Sergio Bampi. "A 40 MHz 70 dB Gain Variable Gain Amplifier Design Using the gm/ID Design Method." Journal of Integrated Circuits and Systems 4, no. 1 (2009): 7–12. http://dx.doi.org/10.29292/jics.v4i1.290.

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This paper addresses the design and post-fabrication measurements of a 40 MHz CMOS Variable Gain Amplifier (VGA) with a 0 to 70 dB gain control range, using the gm/ID design methodology. The VGA architecture is based on a differential pair stage with an automatic continuous-time offset cancellation circuitry, providing an input offset voltage tolerance up to 50 mV. The 3-stage VGA was designed and fabricated through MOSIS service in an IBM 0.18 μm CMOS process. The VGA dissipates 2.6 mA from a 1.8 V supply, with 34,840 μm2 circuit area, excluding bond-pads.
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Zhang, Wei Jia, and Bo Wang. "A SiGe HBT Variable Gain Amplifier for Wireless Receiver System with On-Chip Filter." Applied Mechanics and Materials 155-156 (February 2012): 167–70. http://dx.doi.org/10.4028/www.scientific.net/amm.155-156.167.

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A using SiGe HBT variable gain amplifier (VGA) with filtering for wireless receiver system is presented in this paper. The VGA consists of three stages. The first stage is the gain control stage, and the second stage is the fixed gain stage. The third is the GM-C filter. The VGA is driven by a 3.3-V power supply, and linear gain control range varying is from 26 dB to 62dB. When control voltage varies from 0 to 1.8V. The input 1-dB compression point is -4dBm at minimum gain. The VGA is fabricated in a 0.5 μm = 80GHz and =90GHz silicon germanium heterojunction transistor technology.
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Sun, Zhengyu, and Yuepeng Yan. "Design of a 2 GHz Linear-in-dB Variable-Gain Amplifier with 80-dB Gain Range." Active and Passive Electronic Components 2014 (2014): 1–7. http://dx.doi.org/10.1155/2014/434189.

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A broadband linear-in-dB variable-gain amplifier (VGA) circuit is implemented in 0.18 μm SiGe BiCMOS process. The VGA comprises two cascaded variable-gain core, in which a hybrid current-steering current gain cell is inserted in the Cherry-Hooper amplifier to maintain a broad bandwidth while covering a wide gain range. Postlayout simulation results confirm that the proposed circuit achieves a 2 GHz 3-dB bandwidth with wide linear-in-dB gain tuning range from −19 dB up to 61 dB. The amplifier offers a competitive gain bandwidth product of 2805 GHz at the maximum gain for a 110-GHz ftBiCMOS technology. The amplifier core consumes 31 mW from a 3.3 V supply and occupies active area of 280 μm by 140 μm.
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Arbet, Daniel, Viera Stopjaková, Martin Kováč, Lukáš Nagy, Matej Rakús, and Michal Šovčík. "130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications." Journal of Circuits, Systems and Computers 26, no. 08 (2017): 1740003. http://dx.doi.org/10.1142/s0218126617400035.

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In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency.
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Hu, Shan Wen, Tao Chen, Huai Gao, Long Xing Shi, and G. P. Li. "An Advanced Traveling Wave Matching Network for DC-12GHz Variable Gain Amplifier Design." Applied Mechanics and Materials 321-324 (June 2013): 331–35. http://dx.doi.org/10.4028/www.scientific.net/amm.321-324.331.

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A traveling wave matching (TWM) network is proposed for broadband variable gain amplifier design. The TWM network lessens input return loss and noise figure dependence on VGA’s gain, which is adjusted by biasing of the gain control circuit. A wide band (DC to 12 GHz) VGA with the novel TWM network as input matching is implemented in 2μm InGaP/GaAs HBT (fT of 29.5GHz) technology with die size of 1×2 mm2. As gain control voltage sweeps, the VGA shows a gain tuned from -15 dB to 15 dB and an average noise figure ranging from 8dB to 6.5dB, while S11 (lower than -20dB) and S22 (lower than -10dB) almost unchanged over the operation frequency band.
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Langhammer, Lukas, Roman Sotner, Jan Dvorak, Jan Jerabek, and Peter A. Ushakov. "Novel Reconnection-Less Reconfigurable Filter Design Based on Unknown Nodal Voltages Method and Its Fractional-Order Counterpart." Elektronika ir Elektrotechnika 25, no. 3 (2019): 34–38. http://dx.doi.org/10.5755/j01.eie.25.3.23673.

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A novel solution of reconnection-less electronically reconfigurable filter is introduced in the paper. The filter is designed based on unknown nodal voltages method (MUNV) using operational transconductance amplifiers (OTAs) and variable gain amplifier (VGA). The structure can provide all-pass, band-stop, high-pass 2nd order functions, high-pass function of the 1st order and direct transfer from the same topology without requirement of manual reconnection. The proposed structure also offers the electronic control of the pole frequency. Moreover, fractional-order design of the proposed filter is also provided. The behaviour is verified by simulations using Cadence IC6 (spectre) software.
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Liu, Yu Yang. "A Novel Circuit Design of the Wideband VGA in CMOS." Advanced Materials Research 1049-1050 (October 2014): 682–86. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.682.

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In this paper, a wideband variable-gain amplifier (VGA) in CMOS for ultra wideband (UWB) system is designed. The operation frequency of the VGA is 4.2-4.8GHz, and the gain is continuously adjustable between 0 and 30dB. Cascaded Cherry-Hooper with two stages is adopted as the core unit of the VGA, and a temperature compensation circuit is used to reduce the effect of temperature on the performance of the system. The simulation shows that the temperature compensation circuit can compensate the effect of the temperature very well, and the noise figure of the wideband VGA can meet the requirements of the system.
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Hu, Zhengfei, Li Zhang та Mindi Huang. "A 2.9 mm2 Highly Integrated Low Noise GPS Receiver in 0.18-μm CMOS Technology". Journal of Circuits, Systems and Computers 24, № 03 (2015): 1550036. http://dx.doi.org/10.1142/s021812661550036x.

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An L1 band highly integrated low noise GPS receiver in 0.18-μm CMOS is presented in this paper. The receiver adopts double conversion structure and two dynamic range control modes of variable gain amplifier (VGA) and programmable gain amplifier (PGA). The receiver includes the blocks of LNA, down-conversion mixers, band pass filter, received signal strength indicator (RSSI), VGA, PGA, 2-bit ADC, two frequency synthesizers and so on. The LNA adopts source inductive degeneration technique to achieve good noise performance, and a novel positive feedback capacitor is introduced to enhance gain. The novel gain-boosting charge pump (CP) structure acquires accurate current matching of 0.1% error which improves the output phase noise of frequency synthesizer. The measured radio performances of noise figure (NF) is only 4 dB and the maximum gain is 110 dB. The gain control range achieves 50 dB provided by PGA and VGA. The receiver occupies an area of 1.875 mm × 1.575 mm including all needed voltage reference and the 1.8 V low dropout regulator.
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Dissertations / Theses on the topic "Variable gain amplifiers (VGA)"

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Krishnanji, Sivasankari. "Design of a variable gain amplifier for an ultrawideband receiver." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2576.

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A fully differential CMOS variable gain amplifier (VGA) has been designed for an ultra-wideband receiver. The VGA comprises of two variable gain stages followed by a post amplifier stage. The interface between the digital control block and the analog VGA is formed by a digital-to-analog converter and an exponential voltage generator. The gain of the VGA varies dB-linearly from 0 to 52 dB with respect to the control voltage. The VGA is operated in open loop with a bandwidth greater than 500 MHz throughout the gain range to cater to the requirements of the ultra-wideband system. The noise-to-power ratio of the VGA is -23.9 dB for 1Vp-p differential input signal in the low gain setting, and the equivalent input referred noise is 1.01 V2 for the high gain setting. All three stages use common mode feedback to fix and stabilize the output DC levels at a particular voltage depending on the input common-mode requirement of the following stage. DC offset cancellation has also been incorporated to minimize the input referred DC offset caused by systematic and random mismatches in the circuit. Compensation schemes to minimize the effects of temperature, supply and process variations have been included in the design. The circuit has been designed in 0.18??m CMOS technology, and the post layout simulations are in good agreement with the schematic simulations.
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Jha, Nand Kishore. "Design of a complementary silicon-germanium variable gain amplifier." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24614.

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Chen, Lin. "A low power, high dynamic-range, broadband variable gain amplifier for an ultra wideband receiver." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5843.

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A fully differential Complementary Metal-Oxide Semiconductor (CMOS) Variable Gain Amplifier (VGA) consisting of complementary differential pairs with source degeneration, a current gain stage with programmable current mirror, and resistor loads is designed for high frequency and low power communication applications, such as an Ultra Wideband (UWB) receiver system. The gain can be programmed from 0dB to 42dB in 2dB increments with -3dB bandwidth greater than 425MHz for the entire range of gain. The 3rd-order intercept point (IIP3) is above -13.6dBm for 1Vpp differential input and output voltages. These low distortion broadband features benefit from the large linear range of the differential pair with source degeneration and the low impedance internal nodes in the current gain stages. In addition, common-mode feedback is not required because of these low impedance nodes. Due to the power efficient complementary differential pairs in the input stage, power consumption is minimized (9.5mW) for all gain steps. The gain control scheme includes fine tuning (2dB/step) by changing the bias voltage of the proposed programmable current mirror, and coarse tuning (14dB/step) by switching on/off the source degeneration resistors in the differential pairs. A capacitive frequency compensation scheme is used to further extend the VGA bandwidth.
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Ehteshamuddin, Mohammed. "Design of a High Temperature GaN-Based Variable Gain Amplifier for Downhole Communications." Thesis, Virginia Tech, 2017. http://hdl.handle.net/10919/74958.

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The decline of easily accessible reserves pushes the oil and gas industry to explore deeper wells, where the ambient temperature often exceeds 210 °C. The need for high temperature operation, combined with the need for real-time data logging has created a growing demand for robust, high temperature RF electronics. This thesis presents the design of an intermediate frequency (IF) variable gain amplifier (VGA) for downhole communications, which can operate up to an ambient temperature of 230 °C. The proposed VGA is designed using 0.25 μm GaN on SiC high electron mobility transistor (HEMT) technology. Measured results at 230 °C show that the VGA has a peak gain of 27dB at center frequency of 97.5 MHz, and a gain control range of 29.4 dB. At maximum gain, the input P1dB is -11.57 dBm at 230 °C (-3.63 dBm at 25 °C). Input return loss is below 19 dB, and output return loss is below 12 dB across the entire gain control range from 25 °C to 230 °C. The variation with temperature (25 °C to 230 °C) is 1 dB for maximum gain, and 4.7 dB for gain control range. The total power dissipation is 176 mW for maximum gain at 230 °C.<br>Master of Science
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Azmat, Rehan. "Design and implementation of a low-noise high-linearity variable gain amplifier for high speed transceivers." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73449.

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The variable gain amplifier (VGA) is utilized in various applications of remote sensing and communication equipments. Applications of the variable gain amplifier (VGA) include radar, ultrasound, wireless communication and even speech analysis. These applications use the variable gain amplifier (VGA) to enhance dynamic performance. The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier architectures are designed and compared. First architecture is an amplifier with diode connected load and second architecture is a source degenerative amplifier. The performance of the amplifier with diode connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage variable gain differential amplifier is implemented with selected architecture. The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35 mW at 1.8 V supply source.
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Deza, Julien. "Etude, Conception et Caractérisation de circuits pour la Conversion Analogique Numérique à très hautes performances en technologie TBH InP 0.7µm." Thesis, Cergy-Pontoise, 2013. http://www.theses.fr/2013CERG0680/document.

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Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la linéarité.Des architectures de circuits Echantillonneurs/Bloqueurs (E/B) avec ou sans l'étage d'amplification à gain variable ont été conçues, optimisées, réalisées et caractérisées et des performances à l'état de l'art ont été obtenues : des circuits E/B de bande passante supérieure à 50 GHz et cadencées à 70 Gs/s ont été réalisés pour les applications de communications optiques et des circuits de bande passante supérieure à 16 GHz cadencés à (2-8) Gs/s ont été réalisés pour la transposition de fréquence<br>This thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation
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Emira, Ahmed Ahmed Eladawy. "Bluetooth/WLAN receiver design methodology and IC implementations." Texas A&M University, 2003. http://hdl.handle.net/1969.1/49.

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Emerging technologies such as Bluetooth and 802.11b (Wi-Fi) have fuelled the growth of the short-range communication industry. Bluetooth, the leading WPAN (wireless personal area network) technology, was designed primarily for cable replacement applications. The first generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. In the WLAN (wireless local area network) arena, Wi-Fi appears to be the superior product. Wi-Fi is designed for high speed internet access, with higher radio power and longer distances. Both technologies use the same 2.4GHz ISM band. The differences between Bluetooth and Wi-Fi standard features lead to a natural partitioning of applications. Nowadays, many electronics devices such as laptops and PDAs, support both Bluetooth and Wi-Fi standards to cover a wider range of applications. The cost of supporting both standards, however, is a major concern. Therefore, a dual-mode transceiver is essential to keep the size and cost of such system transceivers at a minimum. A fully integrated low-IF Bluetooth receiver is designed and implemented in a low cost, main stream 0.35um CMOS technology. The system includes the RF front end, frequency synthesizer and baseband blocks. It has -82dBm sensitivity and draws 65mA current. This project involved 6 Ph.D. students and I was in charge of the design of the channel selection complex filter is designed. In the Bluetooth transmitter, a frequency modulator with fine frequency steps is needed to generate the GFSK signal that has +/-160kHz frequency deviation. A low power ROM-less direct digital frequency synthesizer (DDFS) is designed to implement the frequency modulation. The DDFS can be used for any frequency or phase modulation communication systems that require fast frequency switching with fine frequency steps. Another contribution is the implementation of a dual-mode 802.11b/Bluetooth receiver in IBM 0.25um BiCMOS process. Direct-conversion architecture was used for both standards to achieve maximum level of integration and block sharing. I was honored to lead the efforts of 7 Ph.D. students in this project. I was responsible for system level design as well as the design of the variable gain amplifier. The receiver chip consumes 45.6/41.3mA and the sensitivity is -86/-91dBm.
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Opperman, Tjaart Adriaan Kruger. "A 5 GHz BiCMOS I/Q VCO with 360° variable phase outputs using the vector sum method." Diss., Pretoria : [s.n.], 2009. http://upetd.up.ac.za/thesis/available/etd-04082009-171225/.

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Thesis (M.Eng.(Microelectronic Engineering))--University of Pretoria, 2009.<br>Includes summaries in Afrikaans and English. Includes bibliographical references (leaves [74]-78). Mode of access: World Wide Web.
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Oksasoglu, Ali 1960. "GAIN-BANDWIDTH EFFECTS IN THE STATE-VARIABLE FILTERS." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276419.

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Häkkinen, J. (Juha). "Integrated RF building blocks for base station applications." Doctoral thesis, University of Oulu, 2003. http://urn.fi/urn:isbn:951426908X.

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Abstract This thesis studies the level of performance achievable using today's standard IC processes in the integrated RF subcircuits of the modern GSM base station. The thesis concentrates on those circuit functions, i.e. I/Q modulators, variable gain amplifiers and frequency synthesizers, most relevant for integration in the base station environment as pinpointed by studying the receiver/transmitter architectures available today. Several RF integrated circuits have been designed, fabricated and their level of performance measured. All main circuits were fabricated in a standard double-metal double-poly 1.2 and 0.8 μm BiCMOS process. Key circuit structures and their measured properties are: 90° phase shifter with ±1° phase error with VCC = 4.5…5.5 V and T = -10…+85 °C, I/Q modulator suitable for operation at output frequencies from 100 MHz to 1 GHz and baseband frequencies from 60 to 500 kHz (2.0 mm × 2.0 mm, 100 mA, 5.0 V) with LO suppression of 38 dBc and image rejection of 41 dBc, temperature compensated DC to 1.5 GHz variable gain amplifier (1.15 mm × 2.00 mm, 100 mA, 5.0 V) with a linear 50 dB gain adjustment range, maximum gain of 18.5 dB and gain variation of 1 dB up to 700 MHz over the whole operating conditions range of VCC = 4.5…5.5 V and T = -10…+85 °C, a complete bipolar semicustom synthesizer (90…122 mA, 5.0 V) and two complete full-custom BiCMOS synthesizer chips including all building blocks of a PLL-based synthesizer except for the voltage controlled oscillator and the loop filter. The synthesizers include circuit structures such as ∼2 GHz multi-modulus divider and low-noise programmable phase detector/charge pump (18.7 pA/√Hz at Iout = 500 μA) and have an exemplar phase noise performance of -110 dBc/Hz at 200 kHz offset. One of the main problems of the integer-N PLL based synthesizer when used in a multichannel telecommunications system is the level of spurious signals at the output, when the synthesizer is optimised for fast frequency switching. Therefore, a method using only two current pulses to make the frequency step response of the loop faster, thus allowing a narrower loop bandwidth to be used for additional spur suppression, is proposed. The operation of the proposed speed-up method is analysed mathematically and verified by measurements of an existing RF-IC synthesizer operating at 800 MHz. Measurements show that simple current pulses can be used to speed up the channel switching of a practical RF synthesizer having a frequency step time in the tens of μs range. In the example, a 7.65 MHz frequency step was made seven times faster using the proposed method.
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Book chapters on the topic "Variable gain amplifiers (VGA)"

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Chen, Sherry Xi, and Georg Seelig. "A DNA Neural Network Constructed from Molecular Variable Gain Amplifiers." In Lecture Notes in Computer Science. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-66799-7_8.

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Sovcik, Michal, Lukas Nagy, Viera Stopjakova, and Daniel Arbet. "Digital On-Chip Calibration of Analog Systems towards Enhanced Reliability." In Practical Applications in Reliability Engineering. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.96609.

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This chapter deals with digital method of calibration for analog integrated circuits as a means of extending its lifetime and reliability, which consequently affects the reliability the analog electronic system as a whole. The proposed method can compensate for drift in circuit’s electrical parameters, which occurs either in a long term due to aging and electrical stress or it is rather more acute, being caused by process, voltage and temperature variations. The chapter reveals the implementation of ultra-low voltage on-chip system of digitally calibrated variable-gain amplifier (VGA), fabricated in CMOS 130 nm technology. It operates reliably under supply voltage of 600mV with 10% variation, in temperature range from −20°C to 85°C. Simulations suggest that the system will preserve its parameters for at least 10 years of operation. Experimental verification over 10 packaged integrated circuit (IC) samples shows the input offset voltage of VGA is suppressed in range of 13μV to 167μV. With calibration the VGA closely meets its nominally designed essential specifications as voltage gain or bandwidth. Digital calibration is comprehensively compared to its widely used alternative, Chopper stabilization through its implementation for the same VGA.
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Conference papers on the topic "Variable gain amplifiers (VGA)"

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Zhao, Yibing, Bin Hou, and Shuyun Zhang. "Monolithically integrated high performance digital variable gain amplifiers." In 2012 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2012. http://dx.doi.org/10.1109/rfic.2012.6242254.

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Kong, Lingshan, Yong Chen, Haohong Yu, et al. "Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique." In 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2019. http://dx.doi.org/10.1109/apccas47518.2019.8953084.

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Diebold, S., D. Muller, D. Schwantuschke, et al. "AlGaN/GaN-based variable gain amplifiers for W-band operation." In 2013 IEEE/MTT-S International Microwave Symposium - MTT 2013. IEEE, 2013. http://dx.doi.org/10.1109/mwsym.2013.6697340.

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Muh-Dey Wei, Sheng-Fuh Chang, and Renato Negra. "A DC-invariant gain control technique for CMOS differential variable-gain low-noise amplifiers." In 2010 NORCHIP. IEEE, 2010. http://dx.doi.org/10.1109/norchip.2010.5669481.

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Pham, Duy-Dong, Kai Kang, and Fujiang Lin. "Current diversion technique for the design of broadband variable gain amplifiers." In 2010 IEEE International Conference on Communication Systems (ICCS). IEEE, 2010. http://dx.doi.org/10.1109/iccs.2010.5686108.

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Halvorsrod, T. "A dynamic range boosted, low-power method adding continuous variable gain to amplifiers." In 2005 NORCHIP. IEEE, 2005. http://dx.doi.org/10.1109/norchp.2005.1597036.

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Hartzell, Kenneth R. "Free electron laser amplifiers in the high gain Compton regime with variable wigglers." In AIP Conference Proceedings Volume 172. AIP, 1988. http://dx.doi.org/10.1063/1.37474.

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Spiridon, Silvian, Claudius Dan, and Mircea Bodea. "Determining the optimal number of gain stages of variable gain amplifiers used in multi-standard homodyne wireless receivers." In 2013 International Semiconductor Conference (CAS 2013). IEEE, 2013. http://dx.doi.org/10.1109/smicnd.2013.6688652.

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"Compact HEMT MMIC K-band variable gain amplifiers for satellite receiver and transmitter applications." In 15th International Communicatons Satellite Systems Conference and Exhibit. American Institute of Aeronautics and Astronautics, 1994. http://dx.doi.org/10.2514/6.1994-949.

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Cabuk, A., A. V. T. Do, C. C. Boon, Kiat-Seng Yeo, and Manh Anh Do. "Digitally controllable variable-gain amplifiers in 0.18-μm CMOS technology for μ-power applications." In 2007 International Symposium on Integrated Circuits - ISIC 2007. IEEE, 2007. http://dx.doi.org/10.1109/isicir.2007.4441908.

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