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Journal articles on the topic 'Vector processor'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Lai, Bing-Chang, Phillip John McKerrow, and Jo Abrantes. "The abstract vector processor." Microprocessors and Microsystems 30, no. 2 (2006): 86–101. http://dx.doi.org/10.1016/j.micpro.2005.06.002.

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2

Madeswaran, V., and A. Mathialagan. "Microprogrammable pipelined vector processor." Computers in Industry 13, no. 4 (1990): 367–70. http://dx.doi.org/10.1016/0166-3615(90)90009-e.

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3

Lin, Qi. "Design of a vector processor." Journal of Computer Science and Technology 1, no. 1 (1986): 26–34. http://dx.doi.org/10.1007/bf02943298.

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4

Hussain, Tassadaq, Oscar Palomar, Osman S. Ünsal, Adrian Cristal, and Eduard Ayguadé. "Memory Controller for Vector Processor." Journal of Signal Processing Systems 90, no. 11 (2016): 1533–49. http://dx.doi.org/10.1007/s11265-016-1215-5.

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5

Soliman, Mostafa I., and Elsayed A. Elsayed. "Simultaneous Multithreaded Matrix Processor." Journal of Circuits, Systems and Computers 24, no. 08 (2015): 1550114. http://dx.doi.org/10.1142/s0218126615501145.

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This paper proposes a simultaneous multithreaded matrix processor (SMMP) to improve the performance of data-parallel applications by exploiting instruction-level parallelism (ILP) data-level parallelism (DLP) and thread-level parallelism (TLP). In SMMP, the well-known five-stage pipeline (baseline scalar processor) is extended to execute multi-scalar/vector/matrix instructions on unified parallel execution datapaths. SMMP can issue four scalar instructions from two threads each cycle or four vector/matrix operations from one thread, where the execution of vector/matrix instructions in threads

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6

Suaib, Mohammad, Abel Palaty, and Kumar Sambhav Pandey. "Architecture of SIMD Type Vector Processor." International Journal of Computer Applications 20, no. 4 (2011): 42–45. http://dx.doi.org/10.5120/2418-3233.

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7

Krashinsky, Ronny, Christopher Batten, and Krste Asanović. "Implementing the scale vector-thread processor." ACM Transactions on Design Automation of Electronic Systems 13, no. 3 (2008): 1–24. http://dx.doi.org/10.1145/1367045.1367050.

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8

Boeri, F., and M. Auguin. "OPSILA: a vector and parallel processor." IEEE Transactions on Computers 42, no. 1 (1993): 76–82. http://dx.doi.org/10.1109/12.192215.

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9

Heath, L. S., C. J. Ribbens, and S. V. Pemmaraju. "Processor-efficient sparse matrix-vector multiplication." Computers & Mathematics with Applications 48, no. 3-4 (2004): 589–608. http://dx.doi.org/10.1016/j.camwa.2003.06.009.

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10

BRUCK, JEHOSHUA, and CHING-TIEN HO. "EFFICIENT GLOBAL COMBINE OPERATIONS IN MULTI-PORT MESSAGE-PASSING SYSTEMS." Parallel Processing Letters 03, no. 04 (1993): 335–46. http://dx.doi.org/10.1142/s012962649300037x.

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We present a class of efficient algorithms for global combine operations in k-port message-passing systems. In the k-port communication model, in each communication round, a processor can send data to k other processors and simultaneously receive data from k other processors. We consider algorithms for global combine operations in n processors with respect to a commutative and associative reduction function. Initially, each processor holds a vector of m data items and finally the result of the reduction function over the n vectors of data items, which is also a vector of m data items, is known

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11

Fu, Hui Kai. "An Embedded Optical Vector Matrix Multiplication Processor." Applied Mechanics and Materials 263-266 (December 2012): 1334–37. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.1334.

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In this paper, an embedded architecture of optical vector matrix multiplier (OVMM) is presented. The embedded architecture is aimed at optimizing the data flow of vector matrix multiplier (VMM) to promote its performance. The performance according to the architecture is analyzed and the simulation shows that Amdahl's law is used to analyze the hybrid opto-electronic system, and the electronic part and its interaction with optical part form the bottleneck of system.

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12

Deering, Michael, Stephanie Winner, Bic Schediwy, Chris Duffy, and Neil Hunt. "The triangle processor and normal vector shader." ACM SIGGRAPH Computer Graphics 22, no. 4 (1988): 21–30. http://dx.doi.org/10.1145/378456.378468.

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13

Takatoo, M., S. Abe, T. Bando, et al. "Floating Vector Processor for Power System Simulation." IEEE Power Engineering Review PER-5, no. 12 (1985): 29–30. http://dx.doi.org/10.1109/mper.1985.5528607.

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14

Mosca, Eugene P., Richard D. Griffin, Frank P. Pursel, and John N. Lee. "Acoustooptical matrix-vector product processor: implementation issues." Applied Optics 28, no. 18 (1989): 3843. http://dx.doi.org/10.1364/ao.28.003843.

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15

Yu, Jason, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, and Guy Lemieux. "Vector Processing as a Soft Processor Accelerator." ACM Transactions on Reconfigurable Technology and Systems 2, no. 2 (2009): 1–34. http://dx.doi.org/10.1145/1534916.1534922.

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16

Takatoo, M., S. Abe, T. Bando, et al. "Floating Vector Processor for Power System Simulation." IEEE Transactions on Power Apparatus and Systems PAS-104, no. 12 (1985): 3360–66. http://dx.doi.org/10.1109/tpas.1985.318863.

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17

Gündel, Lutz. "A novel high-speed fourier-vector processor." Signal Processing 9, no. 2 (1985): 107–20. http://dx.doi.org/10.1016/0165-1684(85)90033-7.

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18

Batuzov, K. A. "The use of vector instructions of a processor architecture for emulating the vector instructions of another processor architecture." Programming and Computer Software 43, no. 6 (2017): 366–72. http://dx.doi.org/10.1134/s0361768817060032.

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19

VALERO, MATEO, TOMÁS LANG, JOSÉ M. LLABERÍA, MONTSE PEIRON, JUAN J. NAVARRO, and EDUARD AYGUADÉ. "CONFLICT-FREE STRIDES FOR VECTORS IN MATCHED MEMORIES." Parallel Processing Letters 01, no. 02 (1991): 95–102. http://dx.doi.org/10.1142/s0129626491000045.

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Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access to one family of strides in vector processors with matched memories. In this paper, we extend these schemes to achieve this conflict-free access for several families. The basic idea is to perform an out-of-order access to vectors of fixed length, equal to that of the vector registers of the processor. The hardware rcquired is similar to that for the access in order.

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20

Dikarev, Nikolay, Boris Shabanov, and Aleksandr Shmelëv. "Fused Multiply-Adders Using in Vector Dataflow Processor." Program Systems: Theory and Applications 6, no. 4 (2015): 227–41. http://dx.doi.org/10.25209/2079-3316-2015-6-4-227-241.

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21

Dikarev, Nikolay, Boris Shabanov, and Aleksandr Shmelev. "Execution of sorting algorithms on vector dataflow processor." Program Systems: Theory and Applications 8, no. 4 (2017): 305–17. http://dx.doi.org/10.25209/2079-3316-2017-8-4-305-317.

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22

Winter, Dik T. "Influence of memory systems on vector processor performance." Applied Numerical Mathematics 10, no. 1 (1992): 59–72. http://dx.doi.org/10.1016/0168-9274(92)90055-i.

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23

Dekeyser, J. L., Ph Marquet, and Ph Preux. "Vector addressing processor for direct and indirect accesses." Microprocessing and Microprogramming 30, no. 1-5 (1990): 657–64. http://dx.doi.org/10.1016/0165-6074(90)90314-y.

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24

Starikov, R. S. "Technical limitations on an optoelectronic vector-matrix processor." Journal of Communications Technology and Electronics 53, no. 8 (2008): 927–33. http://dx.doi.org/10.1134/s106422690808010x.

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25

Pochapsky, E., and David P. Casasent. "Acoustooptic linear heterodyned complex-valued matrix–vector processor." Applied Optics 29, no. 17 (1990): 2532. http://dx.doi.org/10.1364/ao.29.002532.

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26

Gorodkov, S. S. "Use of a vector processor in reactor calculations." Soviet Atomic Energy 61, no. 4 (1986): 833–35. http://dx.doi.org/10.1007/bf01126159.

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27

Philippe, Bernard. "An Algorithm to Improve Nearly Orthonormal Sets of Vectors on a Vector Processor." SIAM Journal on Algebraic Discrete Methods 8, no. 3 (1987): 396–403. http://dx.doi.org/10.1137/0608032.

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28

Dikarev, Nikolay, Boris Shabanov, and Aleksandr Shmelev. "Simulation of multicore vector dataflow processor with shared memory." Program Systems: Theory and Applications 9, no. 1 (2018): 37–52. http://dx.doi.org/10.25209/2079-3316-2018-9-1-37-52.

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29

Rooholamin, Seyed A., and Sotirios G. Ziavras. "Modular vector processor architecture targeting at data-level parallelism." Microprocessors and Microsystems 39, no. 4-5 (2015): 237–49. http://dx.doi.org/10.1016/j.micpro.2015.04.007.

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30

Qureshi, Q. A., and T. Fischer. "A hardware processor for implementing the pyramid vector quantizer." IEEE Transactions on Acoustics, Speech, and Signal Processing 37, no. 7 (1989): 1135–42. http://dx.doi.org/10.1109/29.32288.

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31

Kawabata, S., and T. Kaneko. "A multi-dimensional integration package for a vector processor." Computer Physics Communications 48, no. 3 (1988): 353–65. http://dx.doi.org/10.1016/0010-4655(88)90201-9.

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32

Pang, Yeyong, Shaojun Wang, Yu Peng, and Xiyuan Peng. "Fully Pipelined Soft Vector Processor as a CPU Accelerator." Chinese Journal of Electronics 26, no. 6 (2017): 1198–205. http://dx.doi.org/10.1049/cje.2017.09.014.

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33

Lukinova, O. V. "Parallel-loop-execution technology for implementation on vector processor." Cybernetics and Systems Analysis 29, no. 2 (1993): 247–49. http://dx.doi.org/10.1007/bf01132786.

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34

Inoue, Atsushi, and Akira Maeda. "The architecture of a multi-vector processor system, VPP." Parallel Computing 8, no. 1-3 (1988): 185–93. http://dx.doi.org/10.1016/0167-8191(88)90123-8.

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35

VanLuchene, R. D., R. H. Lee, and V. J. Meyers. "Large scale finite element analyses on a vector processor." Computers & Structures 24, no. 4 (1986): 625–35. http://dx.doi.org/10.1016/0045-7949(86)90201-4.

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36

Dasalukunte, Deepak, Richard Dorrance, Le Liang, and Lu Lu. "A Vector Processor for Mean Field Bayesian Channel Estimation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29, no. 7 (2021): 1348–59. http://dx.doi.org/10.1109/tvlsi.2021.3077408.

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37

Дикарев, Николай Иванович, Борис Михайлович Шабанов, and Александр Сергеевич Шмелёв. "Advantages and disadvantages of using the pointer vector method in a vector dataflow processor." Program Systems: Theory and Applications 11, no. 4 (2020): 55–71. http://dx.doi.org/10.25209/2079-3316-2020-11-4-55-71.

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Статья посвящена анализу выполнения программы быстрой сортировки (QS) в векторном процессоре с архитектурой управления потоком данных, в котором для хранения массивов используется метод векторов/указателей. Анализируется выявленный на программе QS недостаток хранения массивов с помощью векторов указателей и предложен способ решения этого недостатка введением команд split и fuse в систему команд процессора. Несмотря на значительное усложнение графа и числа выполняемых команд в программе QS, введение в систему команд ВПП новых команд split и fuse позволило достичь на этой программе до 11 раз бол

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38

Dikarev, Nikolay Ivanovich, and Aleksandr Sergeevich Shmelev. "THE VECTOR-POINTER METHOD AND ITS USE IN THE DATAFLOW PROCESSOR." ITNOU: Information technologies in education, science and management, no. 2 (December 2, 2020): 23–27. http://dx.doi.org/10.47501/itnou.2020.2.23-27.

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39

SOLIMAN, MOSTAFA I., and ABDULMAJID F. Al-JUNAID. "SYSTEMC IMPLEMENTATION AND PERFORMANCE EVALUATION OF A DECOUPLED GENERAL-PURPOSE MATRIX PROCESSOR." Parallel Processing Letters 20, no. 02 (2010): 103–21. http://dx.doi.org/10.1142/s0129626410000090.

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Technological advances in IC manufacturing provide us with the capability to integrate more and more functionality into a single chip. Today's modern processors have nearly one billion transistors on a single chip. With the increasing complexity of today's system, the designs have to be modeled at a high-level of abstraction before partitioning into hardware and software components for final implementation. This paper explains in detail the implementation and performance evaluation of a matrix processor called Mat-Core with SystemC (system level modeling language). Mat-Core is a research proce

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40

Hasoun, Mhammed, Aziz El Afia, Mohamed Khafallah, and Karim Benkirane. "Experimental implementation PWM strategy for dual three-phase PMSM using 12-sector vector space decomposition applied on electric ship propulsion." International Journal of Power Electronics and Drive Systems (IJPEDS) 11, no. 4 (2020): 1701. http://dx.doi.org/10.11591/ijpeds.v11.i4.pp1701-1710.

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The current paper aims at presenting and examining an implementation on a digital signal processor (DSP) of the conventional space vector pulse width modulation (CSVPWM) so as to control the dual three phase permanent magnet synchronous motors (DTP-PMSM) drives applied on electric ship propulsion. It is also an attempt to accomplish a developed control of this technique based on vector space decomposition (VSD) strategy. By this strategy, the analysis and the control of the machine are achieved in three two-dimensional orthogonal subspaces. Among the 12 voltage vectors having maximum, the conv

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41

Goto, Nobuo, and Yasumitsu Miyazaki. "Crosstalk in Integrated-Optic Matrix-Vector Processor Using Acoustooptic Effect." Japanese Journal of Applied Physics 30, S1 (1991): 292. http://dx.doi.org/10.7567/jjaps.30s1.292.

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42

Shahabuddin, Shahriar, Janne Janhunen, Markku Juntti, Amanullah Ghazi, and Olli Silvén. "Design of a transport triggered vector processor for turbo decoding." Analog Integrated Circuits and Signal Processing 78, no. 3 (2013): 611–22. http://dx.doi.org/10.1007/s10470-013-0183-y.

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43

Yang, C., L. Wu, Y. Y. Huang, Y. H. Zhang, H. Yang, and G. X. Cui. "Performance of an embedded optical vector matrix multiplication processor architecture." IET Optoelectronics 4, no. 4 (2010): 159–64. http://dx.doi.org/10.1049/iet-opt.2009.0012.

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44

Marzolla, Moreno. "Fast training of support vector machines on the Cell processor." Neurocomputing 74, no. 17 (2011): 3700–3707. http://dx.doi.org/10.1016/j.neucom.2011.04.011.

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45

Aono, K., M. Toyokura, T. Araki, A. Ohtani, H. Kodama, and K. Okamoto. "A video digital signal processor with a vector-pipeline architecture." IEEE Journal of Solid-State Circuits 27, no. 12 (1992): 1886–94. http://dx.doi.org/10.1109/4.173119.

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46

Xu, Huaiyu, Yoshio Mita, and Tadashi Shibata. "Optimizing Vector-Quantization Processor Architecture for Intelligent Query-Search Applications." Japanese Journal of Applied Physics 41, Part 1, No. 4B (2002): 2295–300. http://dx.doi.org/10.1143/jjap.41.2295.

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47

Cheng, H. H., and K. C. Gupta. "Vectorization of robot inverse dynamics on a pipelined vector processor." IEEE Transactions on Robotics and Automation 9, no. 6 (1993): 858–63. http://dx.doi.org/10.1109/70.265931.

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48

Brooks, Eugene D. "A butterfly processor-memory interconnection for a vector processing environment." Parallel Computing 4, no. 1 (1987): 103–10. http://dx.doi.org/10.1016/0167-8191(87)90066-4.

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49

RACCA, R. G., Z. MENG, J. M. OZARD, and M. J. WILMUT. "EVALUATION OF MASSIVELY PARALLEL COMPUTING FOR EXHAUSTIVE AND CLUSTERED MATCHED-FIELD PROCESSING." Journal of Computational Acoustics 04, no. 02 (1996): 159–73. http://dx.doi.org/10.1142/s0218396x96000039.

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Many computer algorithms contain an operation that accounts for a substantial portion of the total execution cost in a frequently executed loop. The use of a parallel computer to execute that operation may represent an alternative to a sheer increase in processor speed. The signal processing technique known as matched-field processing (MFP) involves performing identical and independent operations on a potentially huge set of vectors. To investigate a massively parallel approach to MFP and clustered nearest neighbors MFP, algorithms were implemented on a DECmpp 12000 massively parallel computer

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50

Rajagopal, S., Sheba Charles, Priyanka Vedula, C. Bharatiraja, and S. S. Dash. "FPGA Implementation of Three Dimensional SVPWM." Applied Mechanics and Materials 392 (September 2013): 501–6. http://dx.doi.org/10.4028/www.scientific.net/amm.392.501.

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In this paper includes an approach to implement Three Dimensional Space Vector Pulse width Modulation (3D-SVPWM) for multilevel inverter/Converter. The Proposed 3D-SVM scheme finds the reference vector by using simple mathematical equations for selecting switching states without redundant switching vectors. Moreover, the proposed PWM strategy satisfies the constraint that the output voltage vector should be only changed by one switching action. Not requiring extra hardware, the NPC inverter with the proposed PWM results are remarkable. The proposed algorithm is simulated by MATLAB and Implemen

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