Relevant bibliographies by topics / Verilog-AMS

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Verilog-AMS'

Author: Grafiati
Published: 4 June 2021
Last updated: 7 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Verilog-AMS.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Verilog-AMS"

1

Blanco-Filgueira, B., P. López, and J. B. Roldán. "A Verilog-AMS photodiode model including lateral effects." Microelectronics Journal 43, no. 12 (2012): 980–84. http://dx.doi.org/10.1016/j.mejo.2012.09.001.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Pecheux, F., C. Lallement, and A. Vachoux. "VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 2 (2005): 204–25. http://dx.doi.org/10.1109/tcad.2004.841071.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Ballo, Andrea, Michele Bottaro, Alfio Dario Grasso, and Gaetano Palumbo. "Regulated Charge Pumps: A Comparative Study by Means of Verilog-AMS." Electronics 9, no. 6 (2020): 998. http://dx.doi.org/10.3390/electronics9060998.

Full text
Abstract:
This paper proposes a comparative study of regulation schemes for charge-pump-based voltage generators using behavioral models in Verilog- Analog Mixed Signal (AMS) code. An accurate and simple model of the charge pump is first introduced. It allows reducing the simulation time of complex electronic systems made up by both analog and digital circuits while maintaining a good agreement with transistor-level simulations. Finally, a comprehensive comparative study of the different regulation schemes for charge pumps is reported which allows the designer to choose the most suitable topology for a given application and Charge Pump (CP) operative zone.
APA, Harvard, Vancouver, ISO, and other styles
4

YE, Z., W. CHEN, and M. P. KENNEDY. "Modeling and Simulation of Fractional-N PLL Frequency Synthesizer in Verilog-AMS." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E90-A, no. 10 (2007): 2141–47. http://dx.doi.org/10.1093/ietfec/e90-a.10.2141.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

KOMAWAKI, Takuya, Michitarou YABUUCHI, Ryo KISHIDA, Jun FURUTA, Takashi MATSUMOTO, and Kazutoshi KOBAYASHI. "Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A, no. 12 (2017): 2758–63. http://dx.doi.org/10.1587/transfun.e100.a.2758.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Li, Bo, Yonglei Zhao, and Guoyong Shi. "A novel design of memristor-based bidirectional associative memory circuits using Verilog-AMS." Neurocomputing 330 (February 2019): 437–48. http://dx.doi.org/10.1016/j.neucom.2018.11.050.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Jakobsson, Anders, Adriana Serban, and Shaofang Gong. "Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 3 (2015): 680–88. http://dx.doi.org/10.1109/tcsi.2014.2377411.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Marthi, Poorna, Nazir Hossain, Huan Wang, et al. "Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 12 (2016): 2236–44. http://dx.doi.org/10.1109/tcsi.2016.2618387.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Zlobin, A. V., V. I. Klyukin, and Yu K. Niсkolaenkov. "Clock Signal and Data Recovery Unit Modeling Based on Phase-Locked-Frequency Scheme." Proceedings of Universities. Electronics 26, no. 3-4 (2021): 324–27. http://dx.doi.org/10.24151/1561-5405-2021-26-3-4-324-327.

Full text
Abstract:
In many VLSIs, full amplitude CMOS drivers are used for information transfer via unterminated line. What is more, path length decreases carrying capacity of such interconnection in a greater degree than CMOS drivers’ performance. Because transmit channel considerably garbles transferred information, prevailing solution to this problem are clock data recovery blocks the role of which is to retrieve data along with recovering clock signal. In this work, the process of constructing a clock signal and data recovery unit based on a single-loop phase-locked-frequency scheme that does not require a reference periodic signal is considered. The development of its behavioral model was carried out in the Verilog-AMS hardware description language, and the block modeling at the transistor level was carried out in the 90 nm CMOS technology. In this case, the recovery time was 4.8 microseconds, and the «jitter» indicator of clock signal recovery unit was 7.6 ps. The obtained values of developed clock signal and data recovery unit’s output parameters are up to the best foreign analogues.
APA, Harvard, Vancouver, ISO, and other styles
10

Jmai, Bassem, Vitor Silva, and Paulo M. Mendes. "2D Electronics Based on Graphene Field Effect Transistors: Tutorial for Modelling and Simulation." Micromachines 12, no. 8 (2021): 979. http://dx.doi.org/10.3390/mi12080979.

Full text
Abstract:
This paper provides modeling and simulation insights into field-effect transistors based on graphene (GFET), focusing on the devices’ architecture with regards to the position of the gate (top-gated graphene transistors, back-gated graphene transistors, and top-/back-gated graphene transistors), substrate (silicon, silicon carbide, and quartz/glass), and the graphene growth (CVD, CVD on SiC, and mechanical exfoliation). These aspects are explored and discussed in order to facilitate the selection of the appropriate topology for system-level design, based on the most common topologies. Since most of the GFET models reported in the literature are complex and hard to understand, a model of a GFET was implemented and made available in MATLAB, Verilog in Cadence, and VHDL-AMS in Simplorer—useful tools for circuit designers with different backgrounds. A tutorial is presented, enabling the researchers to easily implement the model to predict the performance of their devices. In short, this paper aims to provide the initial knowledge and tools for researchers willing to use GFETs in their designs at the system level, who are looking to implement an initial setup that allows the inclusion of the performance of GFETs.
APA, Harvard, Vancouver, ISO, and other styles

Dissertations / Theses on the topic "Verilog-AMS"

1

Zheng, Geng. "Layout-accurate Ultra-fast System-level Design Exploration Through Verilog-ams." Thesis, University of North Texas, 2013. https://digital.library.unt.edu/ark:/67531/metadc271923/.

Full text
Abstract:
This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution.
APA, Harvard, Vancouver, ISO, and other styles
2

Kandala, Aravind. "High-Frequency Oscillator Design and Characterization Using Verilog-ams Modeling and Simulation." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142011059.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

RAGHURAMAN, SRINIVASAN. "IMPLEMENTATION AND PERFORMANCE MEASUREMENTS OF A VERILOG-AMS MODEL OF BSIM3v3.3 TRANSISTOR." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1163711277.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

GURUMURTHY, ARAVIND. "COMPARISON OF BEHAVIOR OF MOSFET TRANSISTORS DESCRIBED IN HARDWARE DESCRIPTION LANGUAGES." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1141363591.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

SINGH, GUNEET. "HIGH-FREQUENCY CHARGE-PUMP BASED PHASE-LOCKED LOOP DESIGN AND IT'S CHARACTERIZATION USING VERILOG-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155077793.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Singh, Guneet. "High-frequency charge-pump based phase-locked loop design and it's characterization using verilog-ams." Cincinnati, Ohio : University of Cincinnati, 2006. http://www.ohiolink.edu/etd/view.cgi?acc%5Fnum=ucin1155077793.

Full text
Abstract:
Thesis (M.S.)--University of Cincinnati, 2006.<br>Title from electronic thesis title page (viewed Nov. 29, 2006). Includes abstract. Keywords: Phase Locked Loops, PLLs, PLL, Verilog-AMS. Includes bibliographical references.
APA, Harvard, Vancouver, ISO, and other styles
7

Srinivasan, Vikram. "HDL Descriptions of Artificial Neuron Activation Functions." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1121113992.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Books on the topic "Verilog-AMS"

1

Kundert, Ken, and Olaf Zinke. The Designer’s Guide to Verilog-AMS. Springer, 2013.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

The Designer’s Guide to Verilog-AMS, June 2004. Kluwer Academic Publishers, 2004. http://dx.doi.org/10.1007/b117108.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Zinke, Olaf, and Kenneth S. Kundert. [The Designer's Guide to Verilog-AMS] [published: September, 2004]. Kluwer Academic Pub, 2004.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Kundert, Ken, and Olaf Zinke. The Designer's Guide to Verilog-AMS (The Designer's Guide Book Series). Kluwer Academic Publishers, Boston, 2004.

Find full text
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Verilog-AMS"

1

"Verilog-AMS Codes for Non-Ballistic CNT-FET Modeling." In Carbon-Based Electronics. Jenny Stanford Publishing, 2015. http://dx.doi.org/10.1201/b18254-10.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Verilog-AMS"

1

Zheng, Geng, Saraju P. Mohanty, Elias Kougianos, and Oleg Garitselov. "Verilog-AMS-PAM." In the great lakes symposium. ACM Press, 2012. http://dx.doi.org/10.1145/2206781.2206866.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Dall'Ora, Nicola, Enrico Fraccaroli, Sara Vinco, and Franco Fummi. "Multi-Discipline Fault Modeling with Verilog-AMS." In 2021 4th IEEE International Conference on Industrial Cyber-Physical Systems (ICPS). IEEE, 2021. http://dx.doi.org/10.1109/icps49255.2021.9468133.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Kuo-Hua Cheng and C. F. Jou. "2.4 GHz CMOS VCO design with Verilog-AMS." In Proceedings of the 15th International Conference on Microelectronics. IEEE, 2003. http://dx.doi.org/10.1109/icm.2003.238421.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

da Costa, Haulisson Jody Batista, Francisco de Assis Brito Filho, and Pedro Ivo de Araujo do Nascimento. "Memristor behavioural modeling and simulations using Verilog-AMS." In 2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS). IEEE, 2012. http://dx.doi.org/10.1109/lascas.2012.6180334.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Chandra, Sri. "Driving Analog Mixed Signal Verification through Verilog-AMS." In 21st International Conference on VLSI Design (VLSID 2008). IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.141.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Hujer, Martin, Radek Manasek, Jerry O'Mahony, Patrick Feerick, Mark Barry, and Brendan Walsh. "Nanometer Wireless Transceiver Modeling using Verilog-AMS and SystemC." In 2006 IEEE International Behavioral Modeling and Simulation Workshop. IEEE, 2006. http://dx.doi.org/10.1109/bmas.2006.283486.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Peruzzi, Robert. "Verification of Digitally Calibrated Analog Systems with Verilog-AMS Behavioral Models." In 2006 IEEE International Behavioral Modeling and Simulation Workshop. IEEE, 2006. http://dx.doi.org/10.1109/bmas.2006.283462.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

David, Jonathan. "Verification of CML circuits used in PLL contexts with Verilog-AMS." In 2006 IEEE International Behavioral Modeling and Simulation Workshop. IEEE, 2006. http://dx.doi.org/10.1109/bmas.2006.283477.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Buffeteau, David, Dominique Morche, and Jose-Luis Gonzalez-Jimenez. "VCO Verilog AMS Model for Fast Simulation in VCO-Based ADC." In 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE, 2018. http://dx.doi.org/10.1109/patmos.2018.8463999.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Das, S., S. Bhattacharya, and D. Das. "Modeling of carbon nanotube based device and interconnect using Verilog-AMS." In 3rd International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom 2011). IET, 2011. http://dx.doi.org/10.1049/ic.2011.0050.

Full text
APA, Harvard, Vancouver, ISO, and other styles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography