Relevant bibliographies by topics / Verilog code

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Verilog code'

Author: Grafiati
Published: 5 June 2025
Last updated: 2 August 2025

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Journal articles on the topic "Verilog code"

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Koti, Mr Manjunath, and Dr Basavaraj I. Neelgar. "CAN Tx Frame Implementation using Verilog." Journal of University of Shanghai for Science and Technology 23, no. 07 (2021): 1303–13. http://dx.doi.org/10.51201/jusst/21/07311.

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This article discusses the concept of CAN protocol and its implementation in verilog language. Initially the CAN protocol description is given in brief with the block diagram, later its design, implementation in verilog code is presented. The CAN transmission (Tx) data Frame is realized using verilog code, this is achieved by defining individual sub-blocks verilog codes and combining these to get the CAN transmission of data frame. In the year 1986, CAN data link layer protocol was introduced in SAE conference. In 1993, CAN protocol and high speed physical layer were internationally accredited
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Ho, Chia-Tung, Haoxing Ren, and Brucek Khailany. "VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool." Proceedings of the AAAI Conference on Artificial Intelligence 39, no. 1 (2025): 300–307. https://doi.org/10.1609/aaai.v39i1.32007.

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Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using coll
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Xu, Ying. "Asynchronous FIFO Design Based on Verilog." Highlights in Science, Engineering and Technology 38 (March 16, 2023): 965–70. http://dx.doi.org/10.54097/hset.v38i.5983.

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With the rapid development of integrated circuits, asynchronous First Input First Output (FIFO) is often used to solve the problem of data transmission across the clock domain. This paper mainly studies the key problem of asynchronous FIFO design - the generation of empty - full signal. To solve this problem, it is necessary to realize the synchronization of signal across the clock domain and convert binary code into gray code to reduce the probability of metastable state. The null and full signals generated by the asynchronous FIFO designed in this paper are false null and false full, but thi
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Chen, Qinlin, Nairen Zhang, Jinpeng Wang, et al. "The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog." Proceedings of the ACM on Programming Languages 7, OOPSLA2 (2023): 234–63. http://dx.doi.org/10.1145/3622805.

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With the increasing need to apply modern software techniques to hardware design, Verilog, the most popular Hardware Description Language (HDL), plays an infrastructure role. However, Verilog has several semantic pitfalls that often confuse software and hardware developers. Although prior research on formal semantics for Verilog exists, it is not comprehensive and has not fully addressed these issues. In this work, we present a novel scheme inspired by previous work on defining core languages for software languages like JavaScript and Python. Specifically, we define the formal semantics of Veri
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V, S. Sneha, and Joe Nithin. "Implementation of Turbo Coder Using Verilog HDL for LTE." International Journal of Innovative Science and Research Technology 7, no. 7 (2022): 380–83. https://doi.org/10.5281/zenodo.6930806.

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In many communication systems, turbo codesare employed to repair errors. Turbo codes demonstrate high error correction when compared to other error correction methods. A Very Large Scale Integration is suggested in this study. VLSI architecture for the Turbo encoder implementation, Interleaves and de interleaves, and soft-in-soft-out decoders are employed. This study employs a technique that for the encoder portion, includes two recursive systematic convolutional (RSC) encoders , a Block interleaver and the decoder part involve Soft Output Virtebi Algorithm(SOVA) decoder. Aconvolutional code i
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Fun, Chuah Ching, and Nandha Kumar Thulasiraman. "Synthesizable Verilog Code Generator for Variable-Width Tree Multipliers." Journal of Physics: Conference Series 1962, no. 1 (2021): 012046. http://dx.doi.org/10.1088/1742-6596/1962/1/012046.

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Aminuddin, Zaim Zakwan, Irni Hamiza Binti Hamzah, Ahmad Asri Abd Samat, Mohaiyedin Idris, Alhan Farhanah Abd Rahim, and Zainal Hisham Che Soh. "An FPGA application of home security code using verilog." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 3 (2022): 205. http://dx.doi.org/10.11591/ijres.v11.i3.pp205-214.

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Traditional entrance keys performed a number of drawbacks, including the ease with which they can be stolen, duplicated, or misplaced, allowing unauthorized people to gain access to cash, valuables, and other important documents. As known, most digital electronic entrance locks use application specific integrated circuits (ASICs) as based, which have the disadvantage of being unable to be reconfigured, as opposed to field programmable gate arrays (FPGA). This project proposed a home security code lock using verilog hardware descriptive language (HDL) with two unlocking modes, using a button or
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Zaim, Zakwan Aminuddin, Hamiza Hamzah Irni, Asri Abd Samat Ahmad, Idris Mohaiyedin, Farhanah Abd Rahim Alhan, and Hisham Che Soh Zainal. "An FPGA application of home security code using verilog." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 3 (2022): 205–14. https://doi.org/10.11591/ijres.v11.i3.pp205-214.

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Traditional entrance keys performed a number of drawbacks, including the ease with which they can be stolen, duplicated, or misplaced, allowing unauthorized people to gain access to cash, valuables, and other important documents. As known, most digital electronic entrance locks use application specific integrated circuits (ASICs) as based, which have the disadvantage of being unable to be reconfigured, as opposed to field programmable gate arrays (FPGA). This project proposed a home security code lock using verilog hardware descriptive language (HDL) with two unlocking modes, using a button or
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Wu, Jiang, Zhuo Zhang, Jianjun Xu, et al. "Detraque: Dynamic execution tracing techniques for automatic fault localization of hardware design code." PLOS ONE 17, no. 9 (2022): e0274515. http://dx.doi.org/10.1371/journal.pone.0274515.

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In an error-prone development process, the ability to localize faults is a crucial one. Generally speaking, detecting and repairing errant behavior at an early stage of the development cycle considerably reduces costs and development time. The debugging of the Verilog program takes much time to read the waveform and capture the signal, and in many cases, problem-solving relies heavily on experienced developers. Most existing Verilog fault localization methods utilize the static analysis method to find faults. However, using static analysis methods exclusively may result in some types of faults
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V., Sathya, Nalayini C., M. Kiran Kumar, Kumar G., and Dinesh Babu M. "Plagiarism detection in verilog and textual content using linguistic features." Indonesian Journal of Electrical Engineering and Computer Science 38, no. 3 (2025): 1924. https://doi.org/10.11591/ijeecs.v38.i3.pp1924-1935.

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<span lang="EN-US">The illicit act of appropriating programming code has long been an appealing notion due to the immediate time and effort savings it affords perpetrators. However, it is universally acknowledged that concerted efforts are imperative to identify and rectify such transgressions. This is particularly crucial as academic institutions, including universities, may inadvertently confer degrees for work tainted by this form of plagiarism. Consequently, the primary objective of this research is to scrutinize the feasibility of identifying plagiarism within pairs of Verilog algor
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Dissertations / Theses on the topic "Verilog code"

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Roy, Diana. "Realisierung eines Verilog/VHDL Codegenerators fuer graphisch erfasste Finite State Machines." Master's thesis, Universitätsbibliothek Chemnitz, 1997. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-199700155.

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Es wurden verschieden Kodierungsarten fuer FSMs untersucht, schwerpunktmaessig Gray Code und andere Arten der hazardfreien Kodierung. Ein spezieller Kodierungsalgorithmus zur hazardfreien Kodierung wurde entwickelt und in eine Entwurfsumgebung implementiert. Ein weitere Schwerpunkt der Arbeit sind Codegeneratoren, die eine Verhaltensbeschreibung der FSM in Verilog oder in VHDL erzeugen.
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Bäck, Carl. "Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments." Thesis, Luleå tekniska universitet, Institutionen för system- och rymdteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-78738.

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FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. Developing code for FPGA applications usually requires knowledge about special languages, which are not common knowledge in the signal processing domain. High-level synthesis is an approach where high-level languages, as MATLAB or C++, can be used together with a code generation tool, to directly generate an FPGA ready output. This thesis uses the development of a histog
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Rangoonwala, Sakina. "A Verilog 8051 Soft Core for FPGA Applications." Thesis, University of North Texas, 2009. https://digital.library.unt.edu/ark:/67531/metadc11013/.

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The objective of this thesis was to develop an 8051 microcontroller soft core in the Verilog hardware description language (HDL). Each functional unit of the 8051 microcontroller was developed as a separate module, and tested for functionality using the open-source VHDL Dalton model as benchmark. These modules were then integrated to operate as concurrent processes in the 8051 soft core. The Verilog 8051 soft core was then synthesized in Quartus® II simulation and synthesis environment (Altera Corp., San Jose, CA, www.altera.com) and yielded the expected behavioral response to test programs w
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Rangoonwala, Sakina Kougianos Elias. "A Verilog 8051 soft core for FPGA applications." [Denton, Tex.] : University of North Texas, 2009. http://digital.library.unt.edu/permalink/meta-dc-11013.

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Sampath, Kumar Santhiya. "Implementation of Low-Bit Rate Audio Codec, Codec2, in Verilog on Modern FPGAS." Miami University / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=miami158819886466373.

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Lin, Jia-Hao, and 林家豪. "Multi-Symbol Codec for H.263 and the Synthesizable Verilog Code Generator Thereof." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/5ug37d.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>95<br>The first topic of this thesis is to carry out a multi-symbol codec (encoder-decoder) design for interfacing variable-length and fixed-length data conversion of H.263. The poor memory efficient of the variable-length can be avoided while its advantages can be reserved. The proposed codec converts variable-length symbols to fixed-length packets which can be decoded parallelly. The basic idea is to encode extra symbols in the redundant bits of the fixed-length packets. This encoding scheme relaxes the intrinsic poor compression rate of the prior fixed-length da
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Wang, Wen-shin, and 王文新. "24-bit Automatic Verilog Code Generation of A General Audio Codec Processor Design." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/99960551877271132895.

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碩士<br>南台科技大學<br>電子工程系<br>92<br>This thesis is to design a 24-bit audio processor using automatic verilog code generation method. The processor is based on RISC architecture to get better performance for audio compression and decompression. Three algorithms: G.711(A-Law , u-Law)、ADPCM and MELP(Mixed Excitation Linear Prediction) will be implemented as examples of using proposed audio processor. Using automatic Verilog RTL Code design can reduce the factitious mistakes and shorten design time. The design procedures are as follows. First is to define the instruction set、SFR、ALU、and ad
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Sha, Yuan-Bin, and 夏源斌. "The Study on Code Coverage Metris for Verilog-A." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/25187024637892680986.

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Lai, Jui-Min, and 賴瑞明. "Automatic Verilog Code Generation of an 8-Bit RISC Micro-controller." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/55957143643896340979.

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碩士<br>南台科技大學<br>電子工程系<br>90<br>In this paper, we describe a design method, which can automatically generate verilog code for an 8-bit RISC micro-controller with a user-definable instruction set. With this method, one can shorten the verilog coding time, increase the efficiency of verilog coding, and decrease the man-hour requirement. It is easy to design an 8-bit RISC micro-controller using this method. First of all, the architecture that satisfies the design specification has to be fixed. Then, according to the architecture, the I/O ports, memory size, address space, etc., should b
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Shiao, Yat-Tai, and 蕭義泰. "An Implementation of Space Time Block Codes by Verilog HDL." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/39828380361265411230.

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碩士<br>中原大學<br>電機工程研究所<br>93<br>Foschini,Gans and Telatar proved that multiple input multiple output can introduce spatial diversity and increased information capacity. These results have motivated a new area in error correcting codes . The Space Time Block Codes (STBC) proposed by Tarkoh .Space-Time Coding (STC) schemes can combine the channel code design and the use of multiple transmit antennas . The Verilog language be Gateway Design Automation company build up since 1994 , Verilog language already become a standard hardware description language, Popularly use in VLSI and Digital Syste
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Books on the topic "Verilog code"

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Keating, Michael. Simple art of SoC design: Closing the gap between RTL and ESL. Springer, 2011.

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A Hdl Verilog Code. LAP Lambert Academic Publishing, 2012.

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Vagga, Vittalkumar K., and Kavita V. Vagga. Verilog Tutorial and Programming: With Program Code Examples. Independently Published, 2019.

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Introduction to X86 Machine Code Assembly Language: Using an FPGA with Verilog. Gaul Communications, 2023.

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Introduction to X86 Machine Code Assembly Language: Using an FPGA with Verilog. Gaul Communications, 2023.

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Introduction to X86 Machine Code Assembly Language: Using an FPGA with Verilog. Gaul Communications, 2023.

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Book chapters on the topic "Verilog code"

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Golze, Ulrich. "Das Interpreter-Modell als VERILOG-Code." In Der RISC-Prozessor TOOBSIE. Vieweg+Teubner Verlag, 1995. http://dx.doi.org/10.1007/978-3-322-89551-6_3.

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Barbadekar, Ashwini, and Shreyas Sirshikar. "Design of SPI to I2C Code Converter Using Verilog." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-97-4657-6_35.

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Khatri, Abdul Rafay, Ali Hayek, and Josef Börcsök. "Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs." In Lecture Notes in Computer Science. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-56258-2_11.

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Curzel, Serena. "Modern High-Level Synthesis: Improving Productivity with a Multi-level Approach." In Special Topics in Information Technology. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-51500-2_2.

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AbstractHigh-Level Synthesis (HLS) tools simplify the design of hardware accelerators by automatically generating Verilog/VHDL code starting from a general-purpose software programming language. Because of the mismatch between the requirements of hardware descriptions and the characteristics of input languages, HLS tools still require hardware design knowledge and non-trivial design space exploration, which might be an obstacle for domain scientists seeking to accelerate applications written, for example, in Python-based programming frameworks. This research proposes a modern approach based on
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Radhakrishnan, Sreevatsan, Syed Ishtiyaq Ahmed, and S. R. Ramesh. "Implementation of Classical Error Control Codes for Memory Storage Systems Using VERILOG." In Intelligent Sustainable Systems. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2894-9_3.

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"PicoBlaze Assembly Code Development." In FPGA Prototyping by Verilog Examples. John Wiley & Sons, Inc., 2008. http://dx.doi.org/10.1002/9780470374283.ch16.

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Chopde, Abhay, Sharvari Bodas, Varada Deshmukh, and Shamish Bramhekar. "Fast Inverse Square Root using FPGA." In Advancements in Communication and Systems. Soft Computing Research Society, 2024. http://dx.doi.org/10.56155/978-81-955020-7-3-21.

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The Fast Inverse Square Root (FISR) algorithm, originally introduced in the Quake III source code, accomplishes the vector normalization task required in graphics application through basic multiplication and bit-shifting operations. The core of this algorithm relies on the use of approximation techniques to enhance an initial estimation, which is primarily based on a designated “magic” constant. The implemented Verilog code utilizes the Newton-Raphson iterations, modified booth’s multiplier, and the inverse square root, featuring a core “Inverse Square Root” module with 32-bit input and output
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Yi Qian and Jing Han. "Design and Implementation of a Universal QC-LDPC Encoder." In Frontiers in Artificial Intelligence and Applications. IOS Press, 2016. https://doi.org/10.3233/978-1-61499-722-1-306.

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This paper designed a programmable processor based on multiple instruction multiple data (MIMD) structure, to realize the quasi-cyclic low density parity check code (QC-LDPC) coding algorithm for the wireless LAN (WLAN) and the worldwide interoperability for microwave access (WIMAX). Compared with the traditional LDPC encoder, the processor uses a programmable concatenation-operation to achieve matrix-vector multiplication, obtains high computation speed and easy chip layout. The RTL code of the processor has been written with the Verilog language on the Xilinx ISE platform, and is synthesized
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Sheik Althaf, M., K. P. Ray, Nethravathi K A, Bhishm Tripathi, and Ashish K. Adiga. "Computational Challenges in Firmware Implementation of Beamforming Techniques and Enhancement." In Advances in Transdisciplinary Engineering. IOS Press, 2022. http://dx.doi.org/10.3233/atde220729.

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Adaptive beamforming has been studied extensively from a simulation point of view. While existing works compare various techniques based on their simulation output performance, their emulation on hardware systems and the prerequisite analysis of firmware viability remain relatively unexplored. The work presented in this paper addresses two issues. One is the firmware implementation of adaptive beamforming and the analysis of the Hardware Description Language implementation of the Least Mean Squares (LMS) Algorithm. It begins with the development of the algorithm on MATLAB Simulation Environmen
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Kashayp, Katyayani, Kandarpa Kumar Sarma, and Manash Pratim Sarma. "Design of Logistic Map-Based Spreading Sequence Generation for Use in Wireless Communication." In Next Generation Wireless Network Security and Privacy. IGI Global, 2015. http://dx.doi.org/10.4018/978-1-4666-8687-8.ch003.

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Spread spectrum modulation (SSM) finds important place in wireless communication primarily due to its application in Code Division Multiple Access (CDMA) and its effectiveness in channels fill with noise like signals. One of the critical issues in such modulation is the generation of spreading sequence. This chapter presents a design of chaotic spreading sequence for application in a Direct Sequence Spread Spectrum (DS SS) system configured for a faded wireless channel. Enhancing the security of data transmission is a prime issue which can better be addressed with a chaotic sequence. Generatio
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Conference papers on the topic "Verilog code"

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Shukla, Abhishiek, Jyotsana Singh, and R. K. Chauhan. "128-bit Asynchronous Gray Code FIFO using Verilog HDL." In 2024 International Conference on IoT, Communication and Automation Technology (ICICAT). IEEE, 2024. https://doi.org/10.1109/icicat62666.2024.10923331.

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Nadimi, Bardia, and Hao Zheng. "A Multi-Expert Large Language Model Architecture for Verilog Code Generation." In 2024 IEEE LLM Aided Design Workshop (LAD). IEEE, 2024. http://dx.doi.org/10.1109/lad62341.2024.10691683.

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Gao, Mingzhe, Jieru Zhao, Zhe Lin, et al. "AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs." In 2024 IEEE 42nd International Conference on Computer Design (ICCD). IEEE, 2024. https://doi.org/10.1109/iccd63220.2024.00033.

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Anand, Archana, Saurabh Kumar, and R. K. Chauhan. "CNTFET-based SRAM cell Designing and Analysis by using Verilog-A code." In 2024 International Conference on IoT, Communication and Automation Technology (ICICAT). IEEE, 2024. https://doi.org/10.1109/icicat62666.2024.10922889.

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Zhao, Zhuorui, Ruidi Qiu, Ing-Chao Lin, Grace Li Zhang, Bing Li, and Ulf Schlichtmann. "VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency." In 2025 26th International Symposium on Quality Electronic Design (ISQED). IEEE, 2025. https://doi.org/10.1109/isqed65160.2025.11014398.

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Chen, Kexin, and Gang Chen. "Formal Verification and Verilog Code Generation for Coq-based Carry-Lookahead Adder Algorithm." In 2024 9th International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2024. https://doi.org/10.1109/icicm63644.2024.10814122.

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Prajapati, Shivani, Priyanka Tripathi, and Koushik Dutta. "Parametric Optimization of Verilog-A code for Double-PHL of RRAM Device in a Step-by-Step Approach." In 2025 Devices for Integrated Circuit (DevIC). IEEE, 2025. https://doi.org/10.1109/devic63749.2025.11012324.

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Pola, Yashwanth, Aditya Tiwari, Sarda Sharma, and Sandeep Singh Chauhan. "Design and Hardware Implementation of Polar Codes Using Verilog for Digital Systems." In 2025 IEEE 5th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA). IEEE, 2025. https://doi.org/10.1109/vlsisata65374.2025.11070044.

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Amjad, Hafiz Muhammad, Jianwei Niu, Kai Hu, Naveed Akram, and Loic Besnard. "Verilog Code Generation Scheme from Signal Language." In 2019 16th International Bhurban Conference on Applied Sciences and Technology (IBCAST - 2019). IEEE, 2019. http://dx.doi.org/10.1109/ibcast.2019.8667266.

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Karpuzcu, Ulya R. "Automatic verilog code generation through grammatical evolution." In the 2005 workshops. ACM Press, 2005. http://dx.doi.org/10.1145/1102256.1102346.

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