Relevant bibliographies by topics / Verilog (Computer hardware description language)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Verilog (Computer hardware description language)'

Author: Grafiati
Published: 4 June 2021
Last updated: 27 July 2024

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Verilog (Computer hardware description language).'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Verilog (Computer hardware description language)"

1

Yan, Ziqi. "The application of Verilog in the development of casual games." Applied and Computational Engineering 76, no. 1 (July 16, 2024): 245–49. http://dx.doi.org/10.54254/2755-2721/76/20240600.

Full text
Abstract:
Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and intelligence in modern society. As digital technology continues to advance across various industries, the need for effective and dependable digital circuit design languages is also increasing. This paper delves into the complex process of recreating the timeless arcade classic Pac-Man on the Spartan 3E FPGA platform using hardware description and digital circuit techniques and the Verilog programming language. Through a comprehensive review of existing literature and research, this study investigates the fusion of traditional game design principles with state-of-the-art hardware programming methods, demonstrating the seamless integration of software-driven game mechanics with hardware-based implementation. Through careful design and coding strategies, Pac-Man's basic functionality, such as maze traversal, ghost AI, and pellet consumption, is faithfully replicated using Verilog modules customized for the Spartan 3E FPGA board. By bridging the realms of game development and hardware engineering, this paper not only showcases the versatility of Field Programmable Gate Array (FPGA) technology in entertainment applications but also underscores the interdisciplinary nature of modern computing endeavours.
APA, Harvard, Vancouver, ISO, and other styles
2

Azhari, Zul Imran, Samsul Setumin, Emilia Noorsal, and Mohd Hanapiah Abdullah. "Digital image enhancement by brightness and contrast manipulation using Verilog hardware description language." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (April 1, 2023): 1346. http://dx.doi.org/10.11591/ijece.v13i2.pp1346-1357.

Full text
Abstract:
A foggy environment may cause digitally captured images to appear blurry, dim, or low in contrast. This will impact computer vision systems that rely on image information. With the need for real-time image information, such as a plate number recognition system, a simple yet effective image enhancement algorithm using a hardware implementation is very much needed to fulfil the need. To improve images that suffer from low exposure and hazy, the hardware implementations are usually based on complex algorithms. Hence, the aim of this paper is to propose a less complex enhancement algorithm for hardware implementation that is able to improve the quality of such images. The proposed method simply combines brightness and contrast manipulation to enhance the image. In order to see the performance of the proposed method, a total of 100 vehicle registration number images were collected, enhanced, and evaluated. The evaluation results were compared to two other enhancement methods quantitatively and qualitatively. Quantitative evaluation is done by evaluating the output image using peak signal-to-noise ratio and mean-square error evaluation metrics, while a survey is done to evaluate the output image qualitatively. Based on the quantitative evaluation results, our proposed method outperforms the other two enhancement methods.
APA, Harvard, Vancouver, ISO, and other styles
3

Zheng, Hua Qiang, Li Fu Ma, Yang Liu, and Fei Cai. "Real-Time Video Convert System Design Based on LVDS." Advanced Materials Research 159 (December 2010): 514–21. http://dx.doi.org/10.4028/www.scientific.net/amr.159.514.

Full text
Abstract:
In this paper, we designed a real-time video convert system for the imaging devices which used digital precision progressive scan monochrome camera or the similar camera and as video signal sensor. System hardware circuit design based on LVDS transmission chip, multiformat video decoder chip: ADV718X and the Cyclone II series FPGA. System software design based on hardware description language, verilog HDL and VHDL. The system could real-time capture, process CVBS and output LVDS video data without the system computer.
APA, Harvard, Vancouver, ISO, and other styles
4

Santa, Fernando Martínez, Edwar Jacinto, and Holman Montie. "Hardware description of a simplified 4-bit softcore processor with BCD capabilities." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (April 1, 2020): 1570. http://dx.doi.org/10.11591/ijece.v10i2.pp1570-1576.

Full text
Abstract:
The objective of the work reported in this paper is to improve a 4-bit softcore processor previously designed in Verilog language, keeping its compact size. This processor was thought to be used as academic and didactic tool for teaching as computers architecture subject as digital circuits subject in the technology faculty of the Universidad Distrital. The new features include arithmetic instruction with input carry, BCD operations enabling, rotating instructions, implementation of input and output register banks, increase of the number of general purpose registers of the data memory, and the reduction of the execution clock cycles per instruction. Additionally, the assembler software was enabled to support macro-instructions to make easy the comprehension of some composed functions. As result, a very compact softcore processor was obtained, by means of a Verilog description done in a single file. This implementation occupies only the 2% of the medium-size FPGA used for the application, reaching a maximum possible working clock frequency of 929 Mhz.
APA, Harvard, Vancouver, ISO, and other styles
5

Krishna, B. Murali, B. T. Krishna, and K. Babulu. "Hardware Implementation of Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution Transform on FPGA using CORDIC Algorithm." International Journal of Recent Technology and Engineering (IJRTE) 10, no. 5 (January 30, 2022): 57–60. http://dx.doi.org/10.35940/ijrte.e6705.0110522.

Full text
Abstract:
A comparison of linear and quadratic transform implementation on field programmable gate array (FPGA) is presented. Popular linear transform namely Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution (SPWVD) transform from Quadratic transforms is considered for the implementation on FPGA. Both the transforms are coded in Verilog hardware description language (Verilog HDL). Complex calculations of transformation are performed by using CORDIC algorithm. From FPGA family, Spartan-6 is chosen as hardware device to implement. Synthetic chirp signal is taken as input to test the both designed transforms. Summary of hardware resource utilization on Spartan-6 for both the transforms is presented. Finally, it is observed that both the transforms S-Transform and SPWVD are computed with low elapsed time with respect to MATLAB simulation.
APA, Harvard, Vancouver, ISO, and other styles
6

Pecheux, F., C. Lallement, and A. Vachoux. "VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 2 (February 2005): 204–25. http://dx.doi.org/10.1109/tcad.2004.841071.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Sayudzi, Mohd Faris Izzwan Mohd, Irni Hamiza Hamzah, Azman Ab Malik, Mohaiyedin Idris, Zainal Hisham Che Soh, Alhan Farhanah Abd Rahim, and Nor Shahanim Mohamad Hadis. "FPGA in hardware description language based digital clock alarm system with 24-hr format." International Journal of Reconfigurable and Embedded Systems (IJRES) 13, no. 2 (July 1, 2024): 244. http://dx.doi.org/10.11591/ijres.v13.i2.pp244-252.

Full text
Abstract:
Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition software, all submodule components is developed and being test benched using ModelSim-Altera Starter Edition 13.1 to ensure the correct functionality. Then all inputs and outputs will be assigned through pin assignment in the software. For verification purpose, it will be downloaded to the Altera DE2-115 board. In conclusion, the file has been successfully implemented to the board and the digital clock with alarm is fully functional as expected. This was proved by the alarm signal, time adjustment and display of the three-display mode which is clock, alarm, and input where each mode carries their own functions as expected.
APA, Harvard, Vancouver, ISO, and other styles
8

Doğan, Mustafa, Kasım Öztoprak, and Mehmet Reşit Tolun. "Teaching computer architecture by designing and simulating processors from their bits and bytes." PeerJ Computer Science 10 (February 19, 2024): e1818. http://dx.doi.org/10.7717/peerj-cs.1818.

Full text
Abstract:
Teaching computer architecture (Comp-Arch) courses in undergraduate curricula is becoming more of a challenge as most students prefer software-oriented courses. In some computer science/engineering departments, Comp-Arch courses are offered without the lab component due to resource constraints and differing pedagogical priorities. This article demonstrates how students working in teams are motivated to study the Comp-Arch course and how instructors can increase student motivation and knowledge by taking advantage of hands-on practices. The teams are asked to design and implement a 16-bit MIPS-like processor with constraints as a specific instruction set, and limited data and instruction memory. Student projects include following three phases, namely, design, desktop simulator implementation, and verification using hardware description language (HDL). In the design phase, teams develop their Comp-Arch to implement specified instructions. A range of designs resulted, e.g., (a) a processor with extensive user-defined instructions resulting in longer cycle times (b) a processor with a minimal instruction set but with a faster clock cycle time. Next, teams developed a desktop simulator in any programming language to execute instructions on the architecture. Finally, students engage in Verilog Hardware Description Language (HDL) projects to simulate and verify the data-path designed during the initial phase. Student feedback and their current understanding of the project were collected through a questionnaire featuring varying Likert scale questions, some with a ten-point scale, and others with a five-point scale. Results of the survey show that the hands-on approach increases students’ motivation and knowledge in the Comp-Arch course, which is centered around computer system design principles. This approach can also be effectively extended to related courses, such as Microprocessor Design, which delves into the intricacies of creating and implementing microprocessors or central processing units (CPUs) at the hardware level. Furthermore, the present study demonstrates that interactions, specifically through peer reviews and public presentations, between students in each phase increases their knowledge and perspective on designing custom processors.
APA, Harvard, Vancouver, ISO, and other styles
9

Wang, Chua-Chin, Chenn-Jung Huang, and I.-Yen Chang. "Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library." VLSI Design 11, no. 4 (January 1, 2000): 331–38. http://dx.doi.org/10.1155/2000/69148.

Full text
Abstract:
A high speed 64b/32b integer divider employing digit-recurrence division method and the on-the-fly conversion algorithm, wherein a fast normalizer is included, which is used as the pre-processor of the proposed integer divider. For the sake of enhancing throughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of the traditional radix-2 division. On-the-fly remainder adjustment is also realized in the converter module of the divider. The entire design is written in Verilog HDL (hardware description language) employing COMPASS 0.6 μm 1P3M cell library (V3.0), and then synthesized by SYNOPSYS. The simulation results indicate that our design is a better option than the existing long divider designs.
APA, Harvard, Vancouver, ISO, and other styles
10

Basha, Mudasar, M. Siva Kumar, and M. C. Chinnaiah. "Implementation of Robotic Navigation Algorithms Using Partial Reconfiguration on Zynq SoC." ECS Transactions 107, no. 1 (April 24, 2022): 13887–901. http://dx.doi.org/10.1149/10701.13887ecst.

Full text
Abstract:
The purpose for this research work is to design a heterogeneous method for adaptive, task-based computer hardware reconfiguration for adaptive mobile robotic applications. The proposed method uses the dynamic reconfiguration technique to modify the navigation system to meet the requirements of various navigation algorithms for accomplishing an assigned task. In this work, we have proposed an efficient architecture that satisfies the requirements with adequate hardware and software resources by dynamically reconfiguring the system. The ability to change resources allows robots to collaborate more easily, to enhance performance and fault tolerance. The method is endorsed with case studies in which a multiple mobile robots are loaded with bitfile and their behaviors are dynamically modified during runtime. This paper also proposes the hardware implementation of navigation algorithms on Zynq SoC, XC7Z020CLG484-1, using Xilinx Vivado 2017.3 to simulate and synthesize the design. Verilog is a real-time hardware description language, which is used to deploy multiple robots. Software Development Kit (SDK) is used to facilitate the generation of integrated software applications for Xilinx embedded processors. One of the important aspects of this work is adopting an FPGA-based robot in service-based applications for assisting humans in their daily lives.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Verilog (Computer hardware description language)"

1

Chen, Adam Y. (Adam Yu-Chih). "Implementation of the Intel 486 SX microprocessor in Verilog hardware description language." Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/79470.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Feng, Zhiming Niu Guofu. "Compact modeling of SiGe HBTs using VERILOG-A." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Summer/Theses/FENG_ZHIMING_19.pdf.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Leija, Carlos Ivan. "An artificial neural network with reconfigurable interconnection network." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2008. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Ou, Jen-Chieh. "HARDWARE DESCRIPTION LANGUAGE PROGRAM SLICING AND WAY TO REDUCE BOUNDED MODEL CHECKING SEARCH OVERHEAD." Case Western Reserve University School of Graduate Studies / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=case1159738055.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Kasarabada, Yasaswy. "A Verilog Description and Efficient Hardware Implementation of the Baillie-PSW Primality Test." University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1471347471.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Park, Su-Hyun. "ADH, Aspect Described Hardware-Description-Language." Thesis, University of Canterbury. Electrical and Computer Engineering, 2006. http://hdl.handle.net/10092/1113.

Full text
Abstract:
Currently, many machine vision, signal and image processing problems are solved on personal computers due to the low cost involved in these computers and the many excellent software tools that exist, such as MATLAB. However, computationally expensive tasks require the use of multi-processor computers that are expensive and difficult to use efficiently due to communications between the processors. In these cases, FPGAs (Field Programmable Gate Arrays) are the best choice but they are not as widely used because of lack of experience in using these devices, difficulties with algorithmic translation and immaturity of the design and implementation tools for FPGAs. Programming languages are always evolving and the programming languages for microprocessors have evolved significantly, from functional and procedural languages to object-oriented languages. Nowadays, a new paradigm called aspect-oriented software development (AOSD) is becoming more widespread. However, hardware programming languages have not evolved to the same extent as the software programming languages for microprocessors. They are still dominated by the technologies developed in 1980s, which have significant deficiencies described in this thesis. Recent advances in HDLs (Hardware Description Languages) have taken a conservative approach based on well-proven software techniques.
APA, Harvard, Vancouver, ISO, and other styles
7

Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Dailey, David M. "Integration of VHDL simulation and test verification into a Process Model Graph design environment." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-11242009-020247/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Blumenthal, Carl. "Development of the NoGAP CL Hardware Description Language and its Compiler." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8865.

Full text
Abstract:

The need for a more general hardware description language aimed specifically at processors, and vague notions and visions of how that language would be realized, lead to this thesis. The aim was to use the visions and initial ideas to evolve and formalize a language and begin implementing the tools to use it. The language, called NoGAP Common Language, is designed to give the programmer freedom to implement almost any processor design without being encumbered by many of the tedious tasks normally present in the creation process. While evolving the language it was chosen to borrow syntaxes from C++ and verilog to make the code and concepts easy to understand. The main advantages of NoGAP Common Language compared to RTL languages are;

-the ability to define the data paths of instructions separate from each other and have them merged automatically along with assigned timings to form the pipeline.

-having control paths automatically routed by activating named clauses of code coupled to control signals.

-being able to specify a decoder, where the instructions and control structures are defined, that control signals are routed to.

The implemented compiler was created with C++, Bison, and Flex and utilizes an AST structure, a symbol table, and a connection graph. The AST is traversed by several functions to generate the connection graph where the instructions of the processor can be merged into a pipeline. The compiler is in the early stages of development and much is left to do and solve. It has become clear though that the concepts of NoGAP Common Language can be implemented and are not just visions.


Behovet av ett mer generellt hårdvarubeskrivande språk specialiseret för processorer och visioner om ett sådant gav upphov till detta examensarbete. Målet var att utveckla visionerna, formalisera dem till ett fungerande språk och börja implementera dess verktyg. Språket, som kallas NoGAP Common Language, är designat för att ge programmeraren friheten att implementera nästan vilken processordesign som helst utan att bli nedtyngd av många av de enformiga uppgifter som annars måste utföras. Under utvecklingsprocessen valdes det att låna många syntax från C++ och verilog för att göra språket lätt att förstå och känna igen för många. De största fördelarna med att utveckla i NoGAP Common Language jämfört

med vanliga RTL språk som verilog är;

-att kunna specificera datavägar för instruktioner separat från varandra och få dem automatiskt förenade med hjälp av tidsangivelser till en pipeline.

-att få kontrollvägar automatiskt dragna genom att aktivera namngivna klausuler med kod kopplade till kontrollsignaler.

-att kunna specifiera en avkodare som kontrollvägarna kan kopplas till där

kodning för instruktioner kan anges.

Kompilatorn som implementerats med C++, Bison och Flex använder sig av en AST struktur, en symboltabell och en signalvägsgraf. AST strukturen traverseras av flera funktioner som bygger upp signalvägsgrafen där processorns instruktioner förenas till en pipeline. Utvecklingen av kompilatorn är ännu bara i de första stadierna och mycket är kvar att göra och lösa. Det har dock blivit klart att det är möjligt att implementera koncepten i NoGAP Common Language och att de inte bara är lösa visioner.

APA, Harvard, Vancouver, ISO, and other styles
10

Costi, Claudio. "A methodology for analyzing hardware description language specifications of legacy designs." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/NQ58564.pdf.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "Verilog (Computer hardware description language)"

1

Thomas, D. E. The Verilog hardware description language. 2nd ed. Boston: Kluwer Academic Pub., 1995.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

1953-, Moorby Philip R., ed. The Verilog hardware description language. 3rd ed. Boston: Kluwer Academic Publishers, 1996.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

1953-, Moorby Philip R., ed. The Verilog hardware description language. 5th ed. Norwell, Mass: Kluwer Academic Publishers, 2002.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

1953-, Moorby Philip R., ed. The Verilog hardware description language. Boston: Kluwer Academic Publishers, 1991.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

1953-, Moorby Philip R., ed. The Verilog hardware description language. 4th ed. Boston: Kluwer Academic Publishers, 1998.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Thomas, Donald E. The Verilog® Hardware Description Language. Boston, MA: Springer US, 1998.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Thomas, Donald E. The Verilog® Hardware Description Language. Boston, MA: Springer US, 1991.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Thomas, Donald E. The Verilog® Hardware Description Language. Boston, MA: Springer US, 1995.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Thomas, Donald E. The Verilog® Hardware Description Language. Boston, MA: Springer US, 1996.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

Engineers, Institute Of Electrical and Electronics. IEEE standard Verilog hardware description language. New York: Institute of Electrical and Electronics Engineers, 2001.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "Verilog (Computer hardware description language)"

1

Bowen, Jonathan P. "Combining Operational Semantics, Logic Programming and Literate Programming in the Specification and Animation of the Verilog Hardware Description Language." In Lecture Notes in Computer Science, 277–96. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-40911-4_16.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Thomas, Donald E., and Philip R. Moorby. "Verilog -- A Tutorial Introduction." In The Verilog® Hardware Description Language, 1–24. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Thomas, Donald E., and Philip R. Moorby. "Verilog — A Tutorial Introduction." In The Verilog® Hardware Description Language, 1–29. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4757-2365-6_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Thomas, Donald E., and Philip R. Moorby. "Verilog — A Tutorial Introduction." In The Verilog® Hardware Description Language, 1–32. Boston, MA: Springer US, 1996. http://dx.doi.org/10.1007/978-1-4757-2464-6_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Thomas, Donald E., and Philip R. Moorby. "Verilog—A Tutorial Introduction." In The Verilog® Hardware Description Language, 1–45. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2896-5_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Thomas, Donald E., and Philip R. Moorby. "Behavioral Modeling Constructs." In The Verilog® Hardware Description Language, 25–50. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Thomas, Donald E., and Philip R. Moorby. "Concurrent Process Statements." In The Verilog® Hardware Description Language, 51–72. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Thomas, Donald E., and Philip R. Moorby. "Logic Level Modeling." In The Verilog® Hardware Description Language, 73–97. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Thomas, Donald E., and Philip R. Moorby. "Defining Gate Level Primitives." In The Verilog® Hardware Description Language, 99–111. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Thomas, Donald E., and Philip R. Moorby. "Switch Level Modeling." In The Verilog® Hardware Description Language, 113–34. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_6.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Verilog (Computer hardware description language)"

1

Power, James F., and John Waldron. "Calibration and Analysis of Source Code Similarity Measures for Verilog Hardware Description Language Projects." In SIGCSE '20: The 51st ACM Technical Symposium on Computer Science Education. New York, NY, USA: ACM, 2020. http://dx.doi.org/10.1145/3328778.3366928.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Ebeling, Carl, and Brian French. "Abstract Verilog: A Hardware Description Language for Novice Students." In 2007 IEEE International Conference on Microelectronic Systems Education. IEEE, 2007. http://dx.doi.org/10.1109/mse.2007.16.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Patidar, Jitendra, Rajesh Khatri, and R. C. Gurjar. "Precision Agriculture System Using Verilog Hardware Description Language to Design an ASIC." In 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech). IEEE, 2019. http://dx.doi.org/10.1109/iementech48150.2019.8981128.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

"The Computer Architecture and Hardware Description Language." In 2015 The 5th International Workshop on Computer Science and Engineering-Information Processing and Control Engineering. WCSE, 2015. http://dx.doi.org/10.18178/wcse.2015.04.024.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Burlakov, A. S., and A. E. Khmelnov. "The Computer Architecture and Hardware Description Language." In 2015 38th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO). IEEE, 2015. http://dx.doi.org/10.1109/mipro.2015.7160433.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Klassen, Nicholas, Michael Lyons, Michael Prysiazny, Paul Roth, Peter Socha, Murphy Berzish, Atulan Zaman, and Derek Rayside. "Manifold 2.0: A hardware description language for microfluidic devices." In 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE). IEEE, 2017. http://dx.doi.org/10.1109/ccece.2017.7946805.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Liu, Jianming, Yunjie Zhang, Lili Xu, and Pengtao Liu. "Design of Simple CPU Based on Hardware Description Language." In 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013). Paris, France: Atlantis Press, 2013. http://dx.doi.org/10.2991/iccsee.2013.462.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Wang, Lisheng, Hang Zhou, and Dongdong Zhang. "Automatic testing scheme of hardware description language programs for practice teaching." In 2017 12th International Conference on Computer Science and Education (ICCSE). IEEE, 2017. http://dx.doi.org/10.1109/iccse.2017.8085575.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Polat, Ovunc, and Tulay Yildirim. "Modeling and simulation of a General Regression Neural Network using hardware description language." In 2007 22nd international symposium on computer and information sciences. IEEE, 2007. http://dx.doi.org/10.1109/iscis.2007.4456845.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Reiss, Charles, and Luther Tychonievich. "Experiences with a Hardware Description Language for a CS-major's Computer Organization Course." In 2023 IEEE Frontiers in Education Conference (FIE). IEEE, 2023. http://dx.doi.org/10.1109/fie58773.2023.10343254.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Verilog (Computer hardware description language)' for particular source types:
Journal articles Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography