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Yan, Ziqi. "The application of Verilog in the development of casual games." Applied and Computational Engineering 76, no. 1 (July 16, 2024): 245–49. http://dx.doi.org/10.54254/2755-2721/76/20240600.
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Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and intelligence in modern society. As digital technology continues to advance across various industries, the need for effective and dependable digital circuit design languages is also increasing. This paper delves into the complex process of recreating the timeless arcade classic Pac-Man on the Spartan 3E FPGA platform using hardware description and digital circuit techniques and the Verilog programming language. Through a comprehensive review of existing literature and research, this study investigates the fusion of traditional game design principles with state-of-the-art hardware programming methods, demonstrating the seamless integration of software-driven game mechanics with hardware-based implementation. Through careful design and coding strategies, Pac-Man's basic functionality, such as maze traversal, ghost AI, and pellet consumption, is faithfully replicated using Verilog modules customized for the Spartan 3E FPGA board. By bridging the realms of game development and hardware engineering, this paper not only showcases the versatility of Field Programmable Gate Array (FPGA) technology in entertainment applications but also underscores the interdisciplinary nature of modern computing endeavours.
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Azhari, Zul Imran, Samsul Setumin, Emilia Noorsal, and Mohd Hanapiah Abdullah. "Digital image enhancement by brightness and contrast manipulation using Verilog hardware description language." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (April 1, 2023): 1346. http://dx.doi.org/10.11591/ijece.v13i2.pp1346-1357.
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A foggy environment may cause digitally captured images to appear blurry, dim, or low in contrast. This will impact computer vision systems that rely on image information. With the need for real-time image information, such as a plate number recognition system, a simple yet effective image enhancement algorithm using a hardware implementation is very much needed to fulfil the need. To improve images that suffer from low exposure and hazy, the hardware implementations are usually based on complex algorithms. Hence, the aim of this paper is to propose a less complex enhancement algorithm for hardware implementation that is able to improve the quality of such images. The proposed method simply combines brightness and contrast manipulation to enhance the image. In order to see the performance of the proposed method, a total of 100 vehicle registration number images were collected, enhanced, and evaluated. The evaluation results were compared to two other enhancement methods quantitatively and qualitatively. Quantitative evaluation is done by evaluating the output image using peak signal-to-noise ratio and mean-square error evaluation metrics, while a survey is done to evaluate the output image qualitatively. Based on the quantitative evaluation results, our proposed method outperforms the other two enhancement methods.
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Zheng, Hua Qiang, Li Fu Ma, Yang Liu, and Fei Cai. "Real-Time Video Convert System Design Based on LVDS." Advanced Materials Research 159 (December 2010): 514–21. http://dx.doi.org/10.4028/www.scientific.net/amr.159.514.
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In this paper, we designed a real-time video convert system for the imaging devices which used digital precision progressive scan monochrome camera or the similar camera and as video signal sensor. System hardware circuit design based on LVDS transmission chip, multiformat video decoder chip: ADV718X and the Cyclone II series FPGA. System software design based on hardware description language, verilog HDL and VHDL. The system could real-time capture, process CVBS and output LVDS video data without the system computer.
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Santa, Fernando Martínez, Edwar Jacinto, and Holman Montie. "Hardware description of a simplified 4-bit softcore processor with BCD capabilities." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (April 1, 2020): 1570. http://dx.doi.org/10.11591/ijece.v10i2.pp1570-1576.
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The objective of the work reported in this paper is to improve a 4-bit softcore processor previously designed in Verilog language, keeping its compact size. This processor was thought to be used as academic and didactic tool for teaching as computers architecture subject as digital circuits subject in the technology faculty of the Universidad Distrital. The new features include arithmetic instruction with input carry, BCD operations enabling, rotating instructions, implementation of input and output register banks, increase of the number of general purpose registers of the data memory, and the reduction of the execution clock cycles per instruction. Additionally, the assembler software was enabled to support macro-instructions to make easy the comprehension of some composed functions. As result, a very compact softcore processor was obtained, by means of a Verilog description done in a single file. This implementation occupies only the 2% of the medium-size FPGA used for the application, reaching a maximum possible working clock frequency of 929 Mhz.
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Krishna, B. Murali, B. T. Krishna, and K. Babulu. "Hardware Implementation of Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution Transform on FPGA using CORDIC Algorithm." International Journal of Recent Technology and Engineering (IJRTE) 10, no. 5 (January 30, 2022): 57–60. http://dx.doi.org/10.35940/ijrte.e6705.0110522.
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A comparison of linear and quadratic transform implementation on field programmable gate array (FPGA) is presented. Popular linear transform namely Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution (SPWVD) transform from Quadratic transforms is considered for the implementation on FPGA. Both the transforms are coded in Verilog hardware description language (Verilog HDL). Complex calculations of transformation are performed by using CORDIC algorithm. From FPGA family, Spartan-6 is chosen as hardware device to implement. Synthetic chirp signal is taken as input to test the both designed transforms. Summary of hardware resource utilization on Spartan-6 for both the transforms is presented. Finally, it is observed that both the transforms S-Transform and SPWVD are computed with low elapsed time with respect to MATLAB simulation.
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Pecheux, F., C. Lallement, and A. Vachoux. "VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 2 (February 2005): 204–25. http://dx.doi.org/10.1109/tcad.2004.841071.
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Sayudzi, Mohd Faris Izzwan Mohd, Irni Hamiza Hamzah, Azman Ab Malik, Mohaiyedin Idris, Zainal Hisham Che Soh, Alhan Farhanah Abd Rahim, and Nor Shahanim Mohamad Hadis. "FPGA in hardware description language based digital clock alarm system with 24-hr format." International Journal of Reconfigurable and Embedded Systems (IJRES) 13, no. 2 (July 1, 2024): 244. http://dx.doi.org/10.11591/ijres.v13.i2.pp244-252.
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Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition software, all submodule components is developed and being test benched using ModelSim-Altera Starter Edition 13.1 to ensure the correct functionality. Then all inputs and outputs will be assigned through pin assignment in the software. For verification purpose, it will be downloaded to the Altera DE2-115 board. In conclusion, the file has been successfully implemented to the board and the digital clock with alarm is fully functional as expected. This was proved by the alarm signal, time adjustment and display of the three-display mode which is clock, alarm, and input where each mode carries their own functions as expected.
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Doğan, Mustafa, Kasım Öztoprak, and Mehmet Reşit Tolun. "Teaching computer architecture by designing and simulating processors from their bits and bytes." PeerJ Computer Science 10 (February 19, 2024): e1818. http://dx.doi.org/10.7717/peerj-cs.1818.
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Teaching computer architecture (Comp-Arch) courses in undergraduate curricula is becoming more of a challenge as most students prefer software-oriented courses. In some computer science/engineering departments, Comp-Arch courses are offered without the lab component due to resource constraints and differing pedagogical priorities. This article demonstrates how students working in teams are motivated to study the Comp-Arch course and how instructors can increase student motivation and knowledge by taking advantage of hands-on practices. The teams are asked to design and implement a 16-bit MIPS-like processor with constraints as a specific instruction set, and limited data and instruction memory. Student projects include following three phases, namely, design, desktop simulator implementation, and verification using hardware description language (HDL). In the design phase, teams develop their Comp-Arch to implement specified instructions. A range of designs resulted, e.g., (a) a processor with extensive user-defined instructions resulting in longer cycle times (b) a processor with a minimal instruction set but with a faster clock cycle time. Next, teams developed a desktop simulator in any programming language to execute instructions on the architecture. Finally, students engage in Verilog Hardware Description Language (HDL) projects to simulate and verify the data-path designed during the initial phase. Student feedback and their current understanding of the project were collected through a questionnaire featuring varying Likert scale questions, some with a ten-point scale, and others with a five-point scale. Results of the survey show that the hands-on approach increases students’ motivation and knowledge in the Comp-Arch course, which is centered around computer system design principles. This approach can also be effectively extended to related courses, such as Microprocessor Design, which delves into the intricacies of creating and implementing microprocessors or central processing units (CPUs) at the hardware level. Furthermore, the present study demonstrates that interactions, specifically through peer reviews and public presentations, between students in each phase increases their knowledge and perspective on designing custom processors.
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Wang, Chua-Chin, Chenn-Jung Huang, and I.-Yen Chang. "Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library." VLSI Design 11, no. 4 (January 1, 2000): 331–38. http://dx.doi.org/10.1155/2000/69148.
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A high speed 64b/32b integer divider employing digit-recurrence division method and the on-the-fly conversion algorithm, wherein a fast normalizer is included, which is used as the pre-processor of the proposed integer divider. For the sake of enhancing throughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of the traditional radix-2 division. On-the-fly remainder adjustment is also realized in the converter module of the divider. The entire design is written in Verilog HDL (hardware description language) employing COMPASS 0.6 μm 1P3M cell library (V3.0), and then synthesized by SYNOPSYS. The simulation results indicate that our design is a better option than the existing long divider designs.
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Basha, Mudasar, M. Siva Kumar, and M. C. Chinnaiah. "Implementation of Robotic Navigation Algorithms Using Partial Reconfiguration on Zynq SoC." ECS Transactions 107, no. 1 (April 24, 2022): 13887–901. http://dx.doi.org/10.1149/10701.13887ecst.
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The purpose for this research work is to design a heterogeneous method for adaptive, task-based computer hardware reconfiguration for adaptive mobile robotic applications. The proposed method uses the dynamic reconfiguration technique to modify the navigation system to meet the requirements of various navigation algorithms for accomplishing an assigned task. In this work, we have proposed an efficient architecture that satisfies the requirements with adequate hardware and software resources by dynamically reconfiguring the system. The ability to change resources allows robots to collaborate more easily, to enhance performance and fault tolerance. The method is endorsed with case studies in which a multiple mobile robots are loaded with bitfile and their behaviors are dynamically modified during runtime. This paper also proposes the hardware implementation of navigation algorithms on Zynq SoC, XC7Z020CLG484-1, using Xilinx Vivado 2017.3 to simulate and synthesize the design. Verilog is a real-time hardware description language, which is used to deploy multiple robots. Software Development Kit (SDK) is used to facilitate the generation of integrated software applications for Xilinx embedded processors. One of the important aspects of this work is adopting an FPGA-based robot in service-based applications for assisting humans in their daily lives.
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Kirei, Botond Sandor, Calin-Adrian Farcas, Cosmin Chira, Ionut-Alin Ilie, and Marius Neag. "Hardware Emulation of Step-Down Converter Power Stages for Digital Control Design." Electronics 12, no. 6 (March 10, 2023): 1328. http://dx.doi.org/10.3390/electronics12061328.
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This paper proposes a methodology of delivering the emulation hardware of several step-down converter power stages. The generalized emulator design methodology follows these steps: first, the power stage is described using an ordinary differential equation system; second, the ordinary differential equation system is solved using Euler’s method, and thus an accurate time-domain model is obtained; next, this time-domain model can be described using either general-purpose programming language (MATLAB, C, etc.) or hardware description language (VHDL, Verilog, etc.). As a result, the emulator has been created; validation of the emulator may be carried out by comparing it to SPICE transient simulations. Finally, the validated emulator can be implemented on the preferred target technology, either in a general-purpose processor or a field programmable gate array. As the emulator relies on the ordinary differential equation system of the power stage, it has better behavioral accuracy than the emulators based on average state space models. Moreover, this paper also presents the design methodology of a manually tuned proportional–integrative–derivative controller deployed on a field programmable gate array.
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MANULIAK, I., S. MELNYCHUK, S. VASCHYSHAK, and S. RUDAK. "IMPLEMENTATION OF THE SLIDING MEDIAN METHOD ON FPGA FOR SENSOR SIGNALS PRE-PROCESSING." HERALD OF KHMELNYTSKYI NATIONAL UNIVERSITY 295, no. 2 (May 2021): 35–39. http://dx.doi.org/10.31891/2307-5732-2021-295-2-35-39.
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The use of modern hardware platforms in the development of computer system components, including digital signal processing, allows to describe circuit solutions using specialized languages such as AlteraHDL, VHDL, Verilog, etc. One of the options for using the resources of programmable logic integrated circuits is to create digital components of signal pre-processing, in particular in information and measurement channels. The application of this approach is due to the presence of various distortions that lead to information and accuracy loss. Another problem is the need to preserve the information performance of such information and measurement channels. It is common to use analog implementations of signal pre-processing methods, in particular different types filters. In this case, the implementation of pre-processing methods at the hardware level will provide the appropriate processing speed at insignificant hardware costs. The paper proposes the implementation of the algorithm for processing information and measurement signals using the sliding median method, implemented on a programmable logic integrated circuit. Based on the simulation in a numerical experiment, the efficiency of using such a method is shown in a relatively simple implementation scheme on the FPGA platform. In fact, the pyramidal scheme of conditional constructions provides a simple description of the logical scheme by means of the Altera HDL language, and also allows to reduce the number of comparison operations. The proposed algorithm does not require complex hardware resources, which allows you to effectively involve typical circuit solutions.
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Malhotra, Kashish, Revathi M. S., Uma B. V., and Ajay K. M. "Architectural framework and register-transfer level design synthesis for cost-effective smart eyewear." Indonesian Journal of Electrical Engineering and Computer Science 31, no. 1 (July 1, 2023): 88. http://dx.doi.org/10.11591/ijeecs.v31.i1.pp88-97.
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In today’s time more than 70% of the world’s population suffer from eye disnormalities leading to the usage of eyewear or spectacles. Integrating profound technologies with daily utilities could serve some of the issues improving and optimizing our lifestyle to the most. One such way is to infuse nanosized chip in eyewear i.e., powered spectacles or shades to detect the location of the spectacles whenever it is necessary. The nanosized chip proposed has features including self-designed Bluetooth operating digital circuit, timer logic, clock generation using astable multivibrator circuit, emergency button, beep alarm and impact sensor. The values of resistance and capacitace is calculated to be 18 K ohm and 47 uF to obtain 1 Hz frequency. An optimal pin placement arrangement is analyzed, and the timing waveform is simulated using Verilog as proof of logical working of the chip. 13 D flipflops have been calculated to refrain from eye related strains. This paper suggests a bottom-up approach and develops the architectural framework of the chip, its working flow, system on chip top-view, digital logic description of each block and its implementation using Verilog hardware description language (HDL). The complexity and computational cost of the designed chip is minimal thus being commercially viable.
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Zhang, Yi, Lufeng Qiao, Lin Hu, Xin Xu, and Qinghua Chen. "Cuckoo Bloom Hybrid Filter: Algorithm and Hardware Architecture for High Performance Satellite Internet Protocol Route Lookup." Applied Sciences 13, no. 18 (September 15, 2023): 10360. http://dx.doi.org/10.3390/app131810360.
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The next-generation satellite Internet Protocol (IP) router is required to achieve tens of millions of route lookups per second, since satellite Internet services based on low Earth orbit (LEO) constellations have become a reality. Due to the limitation of hardware resources on satellites and the high reliability requirements for equipment, a new satellite IP route lookup architecture is proposed in this paper. The proposed architecture uses a Bloom and cuckoo filter-based structure called cuckoo Bloom hybrid filter (CBHF), which guarantees only one off-chip memory access per lookup, to accelerate the Prefix-Route Trie (PR-Trie) algorithm. The proposed architecture has been evaluated through both a behavioral simulation in C++ language and a hardware implementation in Verilog hardware description language (HDL). Our simulation and implementation results show that the proposed satellite IP route lookup architecture can achieve a single-port throughput beyond 13 Gbps on a field programmable gate array (FPGA) board with a single DDR3 memory chip when operating at 200 MHz. In addition, the resource utilization in the FPGA shows that the proposed architecture also supports triple modular redundancy (TMR) to enhance reliability.
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Et. al., Deepti Gautam,. "Resourceful Fast Discrete Hartley Transform to Replace Discrete Fourier Transform with Implementation of DHT Algorithm for VLSI Architecture." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 10 (April 28, 2021): 5290–98. http://dx.doi.org/10.17762/turcomat.v12i10.5329.
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Discrete Fourier Transform (DFT) is used in a range of digital signal processing applications, such as signal and image compression systems, filter banks, signal representation or harmonic analysis. The Discrete Hartley Transform (DHT) can be used to effectively replace the DFT when the input sequence is real. This paper introduces and applies the Discrete Hartley Transform (DHT) algorithm, which is well suited to the VLSI architecture. The purpose of using the DHT algorithm is to reduce the complexity of the VLSI architecture. With the introduction of VLSI architectures, 100,000 transistors can be mounted on a single chip. For manufacturers, the verification of these circuits on breadboards is not feasible. Computer-aided design methods have now come into being, but programmers also had to make connections manually at the gate level. Subsequently, Hardware Description Language (HDL) such as Verilog and VHDL came into being. With the integration of the DHT algorithm and its execution, Verilog authors have worked to reduce the complexity of the VLSI circuits in this article. With reduced complexity, the power consumption is reduced and thus the area is therefore reduced. DHT is an algorithm for the Radix-2. It is especially useful for image and signal processing. The DHT algorithm for length N=8 is introduced here.
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Serpa, Francisco Silva e., Alan Marcel Fernandes De Souza, Hélio Fernando Bentzen Pessoa Filho, and Kassio Derek Nogueira Cavalcante. "RISC processor implementation 32-bit MIPS-based: an approach to teaching and learning." Concilium 23, no. 19 (October 11, 2023): 119–32. http://dx.doi.org/10.53660/clm-2074-23p21.
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This article describes the development of the design of a processor based on the RISC architecture, taking the 32-bit MIPS microprocessor as a basis. The RISC architecture, which stands for Reduced Instruction Set Computer, is characterized by having a reduced instruction set, aiming to optimize the processor's overall performance. The designed MIPS processor follows a 5-stage pipeline, which comprises the instruction fetch, instruction decode, execution, preparation and memory access phases. The main objective of this article is to carry out the structural development of the processor, using the hardware description language. This implies the creation of a Verilog representation that will later be used to generate the extraction of the processor's logic circuit. Furthermore, the project involves generating a timing diagram that illustrates the temporal behavior of processor operations and, ultimately, the physical implementation of the processor core. This work seeks to contribute knowledge in the field of computer architecture, providing a practical implementation of a RISC processor based on the 32-bit MIPS architecture, which can be relevant both for educational purposes and for practical applications in embedded systems.
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Saiful Nurdin, Dayana, Mohd Nazrin Md. Isa, Rizalafande Che Ismail, and Muhammad Imran Ahmad. "High Performance Systolic Array Core Architecture Design for DNA Sequencer." MATEC Web of Conferences 150 (2018): 06009. http://dx.doi.org/10.1051/matecconf/201815006009.
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This paper presents a high performance systolic array (SA) core architecture design for Deoxyribonucleic Acid (DNA) sequencer. The core implements the affine gap penalty score Smith-Waterman (SW) algorithm. This time-consuming local alignment algorithm guarantees optimal alignment between DNA sequences, but it requires quadratic computation time when performed on standard desktop computers. The use of linear SA decreases the time complexity from quadratic to linear. In addition, with the exponential growth of DNA databases, the SA architecture is used to overcome the timing issue. In this work, the SW algorithm has been captured using Verilog Hardware Description Language (HDL) and simulated using Xilinx ISIM simulator. The proposed design has been implemented in Xilinx Virtex -6 Field Programmable Gate Array (FPGA) and improved in the core area by 90% reduction.
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Mushtaq, Uzma, Osman Hasan, and Falah Awwad. "NoC-Based Implementation of Free Form Deformations in Medical Imaging Registration." Journal of Circuits, Systems and Computers 26, no. 04 (December 6, 2016): 1750058. http://dx.doi.org/10.1142/s021812661750058x.
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These days, computer-based image registration techniques are increasingly being used in the area of medical imaging as they offer significant benefits for aligning different images together and for visualizing their combined images. However, these techniques require an enormous amount of computation time due to the high resolution and complex nature of the medical images. We propose to alleviate this problem by using a dedicated Network-on-Chip (NoC)-based hardware platform for image registration. This paper describes a novel technique for field-programmable gate array (FPGA) implementation of the B-Spline-based free form deformation (FFD) algorithm, i.e., a widely used algorithm for modeling geometric shapes in a computerized environment. For performance enhancement, we have utilized a lightweight circuit-switched NoC architecture, which is adaptable to most FPGAs. The design description is captured in the Verilog language and implemented using the Xilinx XC2v6000 device at 37[Formula: see text]MHz. The proposed design is parameterizable at the compile time and supports a wide range of the image resolutions and computational precisions. The experimental results have shown a significant improvement in performance when compared with the other existing hardware implementations of the B-spline-based FFD algorithm.
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Balasubramanian, Padmanabhan, Raunaq Nayar, Okkar Min, and Douglas L. Maskell. "Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits." Computers 11, no. 1 (January 8, 2022): 11. http://dx.doi.org/10.3390/computers11010011.
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Approximate arithmetic circuits are an attractive alternative to accurate arithmetic circuits because they have significantly reduced delay, area, and power, albeit at the cost of some loss in accuracy. By keeping errors due to approximate computation within acceptable limits, approximate arithmetic circuits can be used for various practical applications such as digital signal processing, digital filtering, low power graphics processing, neuromorphic computing, hardware realization of neural networks for artificial intelligence and machine learning etc. The degree of approximation that can be incorporated into an approximate arithmetic circuit tends to vary depending on the error resiliency of the target application. Given this, the manual coding of approximate arithmetic circuits corresponding to different degrees of approximation in a hardware description language (HDL) may be a cumbersome and a time-consuming process—more so when the circuit is big. Therefore, a software tool that can automatically generate approximate arithmetic circuits of any size corresponding to a desired accuracy would not only aid the design flow but also help to improve a designer’s productivity by speeding up the circuit/system development. In this context, this paper presents ‘Approximator’, which is a software tool developed to automatically generate approximate arithmetic circuits based on a user’s specification. Approximator can automatically generate Verilog HDL codes of approximate adders and multipliers of any size based on the novel approximate arithmetic circuit architectures proposed by us. The Verilog HDL codes output by Approximator can be used for synthesis in an FPGA or ASIC (standard cell based) design environment. Additionally, the tool can perform error and accuracy analyses of approximate arithmetic circuits. The salient features of the tool are illustrated through some example screenshots captured during different stages of the tool use. Approximator has been made open-access on GitHub for the benefit of the research community, and the tool documentation is provided for the user’s reference.
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Wang, Yu, Xingcheng Liang, Weizhe Xu, Caofan Han, Fei Lyu, Yuanyong Luo, and Yun Li. "An Efficient Hardware Implementation for Complex Square Root Calculation Using a PWL Method." Electronics 12, no. 14 (July 9, 2023): 3012. http://dx.doi.org/10.3390/electronics12143012.
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In this paper, we propose a methodology for computing the square root of a complex number based on a piecewise linear (PWL) approximation method. The proposed method relies on a software-based segmentor that automatically divides the three real square root functions used in complex square root computation into the fewest segments with a predefined fractional bit width and maximum absolute error (MAE). The coefficients, including the start point, end point, slope and y-intercept of each segment, are stored for use in the implementation of the hardware design. The proposed fully pipelined circuit is coded in the Verilog hardware description language (HDL). The results of synthesis in TSMC (Taiwan Semiconductor Manufacturing Company) 65-nm CMOS technology show that our design achieves savings of 64.21% in area, 16.67% in delay and 65.08% in power compared to the existing methods. Moreover, implementation results on an FPGA (Field-Programmable Gate Array) platform (XC7Z020-CLG400) show that the proposed design reduces the number of LUTs by 29.38%, delay by 28.57% and power consumption by 53.47%.
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Favaro, Federico, Ernesto Dufrechou, Pablo Ezzatti, and Juan Pablo Oliver. "Energy-efficient algebra kernels in FPGA for High Performance Computing." Journal of Computer Science and Technology 21, no. 2 (October 21, 2021): e09. http://dx.doi.org/10.24215/16666038.21.e09.
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The dissemination of multi-core architectures and the later irruption of massively parallel devices, led to a revolution in High-Performance Computing (HPC) platforms in the last decades. As a result, Field-Programmable Gate Arrays (FPGAs) are re-emerging as a versatile and more energy-efficient alternative to other platforms. Traditional FPGA design implies using low-level Hardware Description Languages (HDL) such as VHDL or Verilog, which follow an entirely different programming model than standard software languages, and their use requires specialized knowledge of the underlying hardware. In the last years, manufacturers started to make big efforts to provide High-Level Synthesis (HLS) tools, in order to allow a grater adoption of FPGAs in the HPC community.Our work studies the use of multi-core hardware and different FPGAs to address Numerical Linear Algebra (NLA) kernels such as the general matrix multiplication GEMM and the sparse matrix-vector multiplication SpMV. Specifically, we compare the behavior of fine-tuned kernels in a multi-core CPU processor and HLS implementations on FPGAs. We perform the experimental evaluation of our implementations on a low-end and a cutting-edge FPGA platform, in terms of runtime and energy consumption, and compare the results against the Intel MKL library in CPU.
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Wang, J. P., W. Zhou, W. F. Tian, and Z. H. Jin. "Design of an Intelligent Multi-Gyro Measurement Device." Key Engineering Materials 295-296 (October 2005): 589–94. http://dx.doi.org/10.4028/www.scientific.net/kem.295-296.589.
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This paper describes the design of an intelligent multi-gyro measurement device to measure and monitor an inertial unit composed of three dynamically tuned gyros (DTGs). A 16-bit microprogrammed control unit is programmed to fulfill the functions of signal processing, logic control and serial communication with a master computer. An FPGA, designed by using Verilog Hardware Description Language, is used to realize high speed 16-bit reversible counters for output pulses of the DTG digital dynamic balance circuits. The count values represent the angular motion of the inertial unit. A stepping electric bridge is employed to measure the resistance of thermal resistors within the gyros in a wide temperature environment. The resistance represents the working temperature of the gyros. An effective calibration method for the bridge is developed to eliminate the resistance measurement error. A test system is established to examine whether the device meets the user requirements. Results of the tests show that the device has a good performance. A trial use has proved that the device is stable and reliable and that it satisfies the demand of the user.
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N, Nagendra Prasad, Dr Sujatha Hiremath, and Arjumath Farraj. "Design of Double 16_32 –Bit RISC Processor." International Journal for Research in Applied Science and Engineering Technology 11, no. 8 (August 31, 2023): 1739–44. http://dx.doi.org/10.22214/ijraset.2023.55432.
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Abstract: The SOCs built today offer a high level of functionality, serve a variety of applications, and improve in efficiency and cost. Embedded systems also face area and power consumption constraints in addition to real-time challenges. The main objective is to design and implement a 32-bit High-performance RISC (Reduced Instruction Set Computer) Processor architecture. The Processor is designed as an instantiation of submodules using Verilog HDL (Hardware Description Language). a 16-bit compatibility is introduced which makes use of the ISA to execute two 16bit operations at the same time and thus provides the capability to switch and execute both 32-bit and two 16-bit operations using the execution unit. The ISA is modified to meet the requirement to execute both 16-bit operation and 32-bit operations. Each of these instructions are independent of the other instruction and can be executed simultaneously. This enables the RISC based architecture to also enhance the speed of the design by a factor of 2 for 16 bit operations.
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Kamaraju, M., S. Jogesh, V. Sai Teja, P. Venkata Naga Devi, and R. Dinesh. "Verilog-Based Design of AMBA-APB Protocol and Their Verification." Journal of Controller and Converters 8, no. 1 (April 27, 2023): 23–31. http://dx.doi.org/10.46610/jcc.2023.v08i01.002.
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The Advanced Peripheral Bus (APB) is a crucial component of the Advanced Microcontroller Bus Architecture (AMBA), a widely-used standard for designing complex microcontrollers with multiple peripherals. The APB's non-pipelined architecture allows it to connect low-transmission capacity peripherals to the SoC, while minimizing power utilization and interface complexity. The APB is designed to facilitate communication between master and slave devices, supporting multiple slaves in a system. The APB supports three types of transfers: Write, Read, and Idle. The objective of this work is to enable data transfers for Write and Read operations with both No-Wait and Wait states. No-Wait transfers are those that do not require the master to wait for a response from the slave before continuing, while Wait transfers require the master to wait until the slave responds. This allows for efficient and reliable communication between the master and slave devices in the system. To implement this functionality, the Verilog hardware description language (HDL) has been used for design. Verilog offers reusability of Test bench components, allowing for efficient verification of numerous test cases and ensuring the robustness and accuracy of the proposed system. The proposed design and verification methodology with Verilog HDL and a Test bench can thoroughly validate the APB protocol's functionality and performance. This approach enables comprehensive testing of Write and Read operations with No-Wait and Wait states, ensuring that the data transfers occur accurately and efficiently. By utilizing proper simulation and verification using Verilog and a Test bench, the proposed system can be confidently implemented in real-world applications. It provides reliable communication between master and slave devices in a system while minimizing power utilization and interface complexity. The design's reusability enhances the flexibility and adaptability of the system, ensuring that it can be adapted to different applications and scenarios. Overall, the proposed system provides a robust and efficient solution for communication between master and slave devices in an AMBA-based device.
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Kuo, Chao-Tsung. "Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications." Applied Sciences 14, no. 4 (February 12, 2024): 1487. http://dx.doi.org/10.3390/app14041487.
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Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation area and transmission delay for arithmetic computation in DSP. In this study, we propose antilogarithmic converters with efficient error–area–delay products (eADPs) based on the fractional-bit compensation scheme. We propose three mathematical approximations—case 1, case 2, and case 3—to approximate the accurate antilogarithmic curve with different DSP requirements. The maximum percentage errors of conversion for case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with other methods reported in the literature. The proposed eADP-efficient antilogarithmic converters can achieve lower eADP and digitalized circuit implementation. The hardware implementation utilizes Verilog Hardware Description Language and the digital circuits are created via very-large-scale integration by the Taiwan Semiconductor Manufacturing Company with 0.18 µm CMOS technology. This proposed antilogarithmic converter can be efficiently applied in DSP.
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Qiao, Tianbo. "Gait Control of Hexapod Robot Based on Field-Programmable Gate Array and Central Pattern Generator." Journal Européen des Systèmes Automatisés 53, no. 6 (December 23, 2020): 931–37. http://dx.doi.org/10.18280/jesa.530619.
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This paper attempts to improve the terrain adaptability of hexapod robot through gait control. Firstly, the multi-leg coupling in the tripodal gait of the hexapod robot was modeled by Hopf oscillator. Then, annular central pattern generator (CPG) was adopted to simulate the leg movements of hexapod robot between signals. Furthermore, a physical prototype was designed for the gait control test on field-programmable gate array (FPGA), and the algorithm of the rhythmic output of the model was programmed in Verilog, a hardware description language. Finally, the effectiveness of our gait control method was verified through the simulation on Xilinx. The results show that the phase difference of the CPG network remained stable; the designed hexapod robot moved at about 5.15cm/s stably in a tripodal gait, and outperformed wheeled and tracked robots in terrain adaptation. The research findings lay a solid basis for the design of all-terrain multi-leg robots.
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Salauyou, Valery. "Description styles of fault-tolerant finite state machines for unmanned aerial vehicles." Radioelectronic and Computer Systems 2024, no. 1 (February 28, 2024): 196–206. http://dx.doi.org/10.32620/reks.2024.1.15.
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The subject matter of this article is finite state machines (FSMs), which are used as control devices in unmanned aerial vehicles (UAVs). The goal of this study is to develop description styles for fault-tolerant FSMs in hardware description languages (HDLs) that prevent failures in the state register and in the input vector of the FSM. The tasks to be solved are as follows: development of description methods for FSM transitions from illegal states in case of failure in the state register, as well as for FSM transitions from each state in case of failure in the input vector; determination of FSM output vector values in case of the above failures; development of description styles for fault-tolerant FSMs; and investigation of the efficiency of the proposed description styles for fault-tolerant FSMs. The methods used are: the theory of finite state machines, state encoding methods of FSMs, description styles of FSMs, and Verilog hardware description language. The following results were obtained: two styles of describing fault-tolerant FSMs have been developed, safe0 and safe1, which do not increase the area and do not decrease the performance of FSMs, and in some cases allow the area to be reduced (for some examples by a factor of 4.8) and increase the performance (for some examples by a factor of 2.355). In addition, the description styles of fault-tolerant FSMs neutralize design errors when transitions are described in each state but not for all possible values of input variables. Conclusions. In this paper, the problem of designing fault-tolerant FSMs when the values of bits in the state register or in the input vector of the FSM change because of the negative external impact is described. Different ways of solving the problem at the level of FSM description in HDL are considered. Two description styles for fault-tolerant FSMs are proposed: safe0 and safe1. The fault tolerance of FSMs is provided in the following manner. When the input vector is not defined in the FSM specification for a specific state, the FSM will remain in the initial transition state, i.e. the FSM will not transit to another state. If the code of the illegal state is set in the state register, the FSM will transition to the start state. For all these faults, the safe0 style provides a zero output vector at the FSM output, whereas the safe1 style preserves the value of the previous output vector. A promising direction for future research seems to be the development of new styles and methods of FSM description, aimed at improving the FSM parameters (an area, a performance and a power consumption), as well as improving the reliability and fault tolerance of FSMs.
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Rashid, Muhammad, Mohammad Mazyad Hazzazi, Sikandar Zulqarnain Khan, Adel R. Alharbi, Asher Sajid, and Amer Aljaedi. "A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography." Electronics 10, no. 21 (November 4, 2021): 2698. http://dx.doi.org/10.3390/electronics10212698.
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This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.
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An, Hyogeun, Sudong Kang, Guard Kanda, and Kwangki Ryoo. "RISC-V Hardware Synthesizable Processor Design Test and Verification Using User-Friendly Desktop Application." Webology 19, no. 1 (January 20, 2022): 4597–620. http://dx.doi.org/10.14704/web/v19i1/web19305.
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Although the RISC-V ISA has not been around for long, it is a processor architecture that has been highlighted by many businesses and individuals for its low-cost and rapid pace of development. They are open-source-synthesizable hardware processors with minimal functionality that is ideal for current IoT applications involving simple sensors and actuator controls. Due to some qualities of hardware, they can operate in areas where software programs and applications cannot be used whereas, these software programs that run on such hardware equally help in understanding how hardware operates. This paper, therefore, proposes and discusses the design, implementation, and internal verification and test platform for a Reduced Instruction Set Code-V’s (RISC-V) Instruction Set Architecture (ISA), using an interactive desktop program for a 32-bit single-cycle processor. This paper developed a system that functions as interactive assistance to RISC-V's ISA design and debugger using a more user-friendly desktop UI application. The uniqueness of this design is the flexibility of testing and debugging that is possible through either the software interface or through hardware peripherals such as Universal Asynchronous Receiver/Transmitter (UART) protocols in FPGA or even both. These peripherals allow users to view the contents of the register files and RAM being utilized by the implemented processor on the FPGA. The proposed desktop User Interface program monitors and controls the sequential processing and states of a 32-bit single-cycle RISC-V processor’s operation on an FPGA. Contents of the proposed processor’s registers and memory are displayed alongside other temporal or internal data. Internal components such as Program Counters (PC), Random Access Memory (RAM), are displayed all through the proposed User Interface (UI) program and also through various peripherals on the FPGA board. The software program is implemented using C# programing language through Microsoft Visual Studio 2019 Integrated Development Environment (IDE). The proposed hardware synthesizable processor core is implemented using Verilog Hardware Description Language (HDL) and synthesized with Xilinx Integrated Synthesis Environment (ISE) version 14.7. The proposed processor and its corresponding hardware test modules occupy 6476 Look-Up-Tables (LUT) and operate at a maximum frequency of 49MHz and its operation is verified on a Field Programmable Gate Array (FPGA). The proposed processor and its test platform can serve as a good educational tool as well as a help for processor design engineers both experienced and beginners.
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Huang, Wentao, and Lan Chen. "A Compact Model of Carbon Nanotube Field-Effect Transistors for Various Sizes with Bipolar Characteristics." Electronics 13, no. 7 (April 3, 2024): 1355. http://dx.doi.org/10.3390/electronics13071355.
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Carbon nanotubes have excellent electrical properties and can be used as a new generation of semiconductor materials. This paper presents a compact model for carbon nanotube field-effect transistors (CNTFETs). The model uses a semi-empirical approach to model the current–voltage properties of CNTFETs with gate lengths exceeding 100 nm. This study introduces an innovative approach by proposing physical parametric reference lengths (Lref), which facilitate the integration of devices of varying sizes into a unified modeling framework. Furthermore, this paper develops models for the bipolar properties of carbon nanotube devices, employing two distinct sets of model parameters for enhanced accuracy. The model offers a comprehensive analysis of the different capacitances occurring between the electrodes within the device. The simulation of the model shows good agreement with the experimental measurements, confirming the model’s validity. The model is implemented in the Verilog-A hardware description language, with the circuit being subsequently constructed and subjected to simulations via the HSPICE tool. The CNTFET-based inverter exhibits a gain of 7.022 and a delay time of 16.23 ps when operated at a voltage of 1.2 V.
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Shavali, Vennapusapalli, Sreeramareddy Gorlagummanahally Maripareddy, and Patil Ramana Reddy. "Reconfigurable data encoding schemes for on-chip interconnect power reduction in deep submicron technology." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 3 (October 7, 2022): 1330. http://dx.doi.org/10.11591/ijeecs.v28.i3.pp1330-1344.
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With technology scaling, size of both transistor and interconnects are reduced. Power dissipation due to dynamic switching is high in the interconnects. Suitable encoding schemes that reduces transition between data bits are used to minimize interconnect power dissipation. In this paper transition between data bits is minimized based on three novel data encoding schemes identifying the novel methods estimates bit transitions in a pair of data bits and performs half inversion or full inversion on one byte of data thus reducing the switching activity by 50%. The encoder and decoder for the three encoding schemes are modelled in verilog hardware description language (HDL) and implemented using application specefic integrates circuit (ASIC) flow targeting 32 nm. Technology over all power dissipation of encoding scheme is 1.04 μW in addition over head area of 210 cells with encoding delay of 340 ps. Encoder decoder register transfer logic (RTL) code is implemented and the total area required is 34980 units. The data encoding and decoding schemes are suitable for low power applications.
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Wan, Renzhuo, Yuandong Li, Chengde Tian, Fan Yang, Wendi Deng, Siyu Tang, Jun Wang, and Wei Zhang. "Design and Implementation of Sigma-Delta ADC Filter." Electronics 11, no. 24 (December 19, 2022): 4229. http://dx.doi.org/10.3390/electronics11244229.
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This paper presents a digital decimation filter based on a third-order four-bit Sigma-Delta modulator. The digital decimation filter is an important part of the Sigma-Delta ADC and is designed to make the Sigma-Delta ADC (Analog-to-Digital Converter) meets the requirements of Signal-to-Noise Ratio (SNR) not less than 120 dB and Equivalent Number of Bits (ENOB) not less than 20 bits. It adopts a three-stages cascaded structure including a Cascaded Integrator Comb (CIC) decimation filter, a Finite Impulse Response (FIR) compensation filter, and a half-band (HB) filter. This structure effectively reduces about 13% multiplier cells and memory cells. The coefficient symmetry technique and CSD (Canonic Signed Digit) coding technique are used to optimize the parameters of the filter, which further reduces the computational complexity. After optimization, the circuit area is reduced by about 15%, and the logic resources are decreased by about 23%. The Verilog hardware description language is used to describe the behavior of the digital decimation filter, and the simulation is carried out based on the VCS (Verilog Compile Simulator) platform. At the same time, the prototype verification is implemented on the Xilinx Artix-7 series FPGA, and the ADC achieves 113 dB SNR and 18.5 bits ENOB. Finally, the Sigma-Delta ADC is fabricated on SMIC 0.18 μm CMOS process with the layout area of 714.8 μm × 628.4 μm and the power consumption of 11.2 mW. The more tests for the fabricated prototypes will be performed in the future to verify that the Sigma-Delta ADC complies with the design specifications.
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Iroanusi, Kennedy Ahamefula. "FPGA Data Acquisition of Electrical Parameter." European Journal of Engineering and Technology Research 6, no. 4 (June 25, 2021): 105–23. http://dx.doi.org/10.24018/ejers.2021.6.4.1538.
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A data acquisition system using a Programmable Logic Gate Array (FPGA) and Graphical User Interface (GUI) for visual enhancement designed for Personal Computer is shown. The data acquisition of voltage (V), current (A) and temperature ( ) signals and/or parameters transmitted at high frequency in real time via the system-on-chip (SOC) created on Spartan 6 FPGA. The system-on-chip is achieved by programming the FPGA with a high-speed hardware description language (Verilog) code written for the system, Printed Circuit Board (PCB) was designed for the system and the GUI has been created using a graphical approach utilizing LabVIEW to enable data monitoring on Personal Computer (PC) display. The FPGA requires digital input signals; therefore, an analogue to digital convertor (ADC) is required for the convert sensor data from analogue signal from sensors to digital signals. A voltage level shifter is required to normalise the voltage level standards within the circuity in between the 5V from the ADC converter and the 3.3V voltage requirement for the FPGA. The Spartan 6 FPGA receives data from the analogue sensors via the ADC, the data are wrapped up in packets and transmitted through RS-232 serial port to the PC. The three aforementioned parameters are monitored on the GUI on the PC presented in both numerical and graphical format and all data can be store in a file for backup storage, maintenance or reference purposes.
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Iroanusi, Kennedy Ahamefula. "FPGA Data Acquisition of Electrical Parameter." European Journal of Engineering and Technology Research 6, no. 4 (June 25, 2021): 105–23. http://dx.doi.org/10.24018/ejeng.2021.6.4.1538.
Full textAbstract:
A data acquisition system using a Programmable Logic Gate Array (FPGA) and Graphical User Interface (GUI) for visual enhancement designed for Personal Computer is shown. The data acquisition of voltage (V), current (A) and temperature ( ) signals and/or parameters transmitted at high frequency in real time via the system-on-chip (SOC) created on Spartan 6 FPGA. The system-on-chip is achieved by programming the FPGA with a high-speed hardware description language (Verilog) code written for the system, Printed Circuit Board (PCB) was designed for the system and the GUI has been created using a graphical approach utilizing LabVIEW to enable data monitoring on Personal Computer (PC) display. The FPGA requires digital input signals; therefore, an analogue to digital convertor (ADC) is required for the convert sensor data from analogue signal from sensors to digital signals. A voltage level shifter is required to normalise the voltage level standards within the circuity in between the 5V from the ADC converter and the 3.3V voltage requirement for the FPGA. The Spartan 6 FPGA receives data from the analogue sensors via the ADC, the data are wrapped up in packets and transmitted through RS-232 serial port to the PC. The three aforementioned parameters are monitored on the GUI on the PC presented in both numerical and graphical format and all data can be store in a file for backup storage, maintenance or reference purposes.
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Singh, Naginder, and Kapil Parihar. "Comparative study of single precision floating point division using different computational algorithms." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 3 (November 1, 2023): 336. http://dx.doi.org/10.11591/ijres.v12.i3.pp336-344.
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<span>This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast division computation algorithms can apply to all division cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the computational speed of the mantissa module and this module is used to design a 32-bit floating point multiplier which is the crucial feature of this proposed design, which yields a higher computational speed and reduced delay time. The proposed design of floating-point divider using fast computational algorithms synthesized using Verilog hardware description language has a 32-bit floating point multiplier module unit and a 32-bit floating point subtractor module unit. Xilinx Spartan 6 SP605 evaluation platform is used to verify this proposed design on FPGA. Synthesis results provide the device utilization and propagation delay parameters for the proposed design and a comparative study is done with previous work. Input to the divider is provided in IEEE 754 32-bit formats.</span>
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Zhang, Xiaowen. "Design and implementation of UART receiving module based on FPGA." Applied and Computational Engineering 14, no. 1 (October 23, 2023): 81–85. http://dx.doi.org/10.54254/2755-2721/14/20230768.
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In modern electronic systems, data transmission is an essential requirement within and between boards, or between lower and upper computers. To ensure data transmission accuracy, communication protocols are established that must be followed by all parties involved. These protocols include UART (universal asynchronous transmitter and receiver), IIC (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), USB2.0/3.0(Universal Serial Bus), and Ethernet. Among these protocols, UART is the most basic one and is widely used in embedded devices due to its simple circuit structure and low cost. With the exponential growth of information technology, UART-based embedded devices can easily achieve wired and wireless communication through various communication interfaces and wireless modules. In this paper, the author presents an example of a receiving module for UART communication that converts parallel data into string data. The entire module is developed using the hardware description language Verilog HDL. Simulations are performed using ModelSim, and the results demonstrate that the simulation waveform is consistent with the expected receiving data. This approach facilitates the transformation of serial data to parallel data, improving the efficiency and accuracy of data transmission.
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Koppala, Neelima, Nagarajan Ashok Kumar, Satyam Satyam, and Neeruganti Vikram Teja. "Proficient matrix codes for error detection and correctionin 8-port network on chip routers." Indonesian Journal of Electrical Engineering and Computer Science 29, no. 3 (March 1, 2023): 1336. http://dx.doi.org/10.11591/ijeecs.v29.i3.pp1336-1344.
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This paper verifies the applicability of the proposed code to dynamic Network on Chips that have variable faulty blocks with runtime suggesting an online error detection mechanism with adaptive routing algorithm that bypasses faulty components dynamically and the router architecture uses additional diagonal state indications for the reliable network on chip (NoC) operation. In NoC, the permanently faulty routers are disconnected to enable high runtime throughput as data packets are not lost due to self-loopback mechanism. The proposed proficient matrix codes use the capabilities of decimal matrix code technique with minimum check bits for maximum error correction capability. The proposed code is compared with existing codes such as decimal matrix codes, modified decimal matrix codes and parity matrix codes. The codes are developed in verilog hardware description language and simulated in the Xilinx ISE 14.5 tool. This proficient matrix code proves to be efficient for multiple adjacent error detection and correction with trade off in delay. Also 65% code rate is achieved with 22.73% less redundant bits that occupy less area by atleast 11.78%. The codes when used for increased data sizes like 8, 16, 32, and 64 bits, the power delay product decreased by atleast 1.74%.
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Balasubramanian, Padmanabhan, Raunaq Nayar, and Douglas L. Maskell. "Approximate Array Multipliers." Electronics 10, no. 5 (March 9, 2021): 630. http://dx.doi.org/10.3390/electronics10050630.
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This article describes the design of approximate array multipliers by making vertical or horizontal cuts in an accurate array multiplier followed by different input and output assignments within the multiplier. We consider a digital image denoising application and show how different combinations of input and output assignments in an approximate array multiplier affect the quality of the denoised images. We consider the accurate array multiplier and several approximate array multipliers for synthesis. The multipliers were described in Verilog hardware description language and synthesized by Synopsys Design Compiler using a 32/28-nm complementary metal-oxide-semiconductor technology. The results show that compared to the accurate array multiplier, one of the proposed approximate array multipliers viz. PAAM01-V7 achieves a 28% reduction in critical path delay, 75.8% reduction in power, and 64.6% reduction in area while enabling the production of a denoised image that is comparable in quality to the image denoised using the accurate array multiplier. The standard design metrics such as critical path delay, total power dissipation, and area of the accurate and approximate multipliers are given, the error parameters of the approximate array multipliers are provided, and the original image, the noisy image, and the denoised images are also depicted for comparison.
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Kuo, Chao-Tsung, and Yao-Cheng Wu. "Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array." Electronics 13, no. 2 (January 10, 2024): 311. http://dx.doi.org/10.3390/electronics13020311.
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A multi-modulus architecture based on the radix-8 Booth encoding of a modulo (2n − 1) multiplier, a modulo (2n) multiplier, and a modulo (2n + 1) multiplier is proposed in this paper. It uses the original single circuit and shares many common circuit characteristics with a small extra circuit to carry out multi-modulus operations. Compared with a previous radix-4 study, the radix-8 architecture can increase the modulation multiplication encoding selection from three codes to four codes. This reduces the use of partial products from ⌊n/2⌋ to ⌊n/3⌋ + 1, but it increases the operation complexity for multiplication by three circuits. A hard multiple generator (HMG) is used to address this problem. Two judgment signals in the multi-modulus circuit can be used to perform three operations of the modulo (2n − 1) multiplier, modulo (2n) multiplier, and modulo (2n + 1) multiplier at the same time. The weighted representation is used to reduce the number of partial products. Compared with previously reported methods in the literature, the proposed approach can achieve better performance by being more area-efficient, being faster, consuming low power, and having a lower area-delay product (ADP) and power-delay product (PDP). With the multi-modulus HMG, the proposed modified architecture can save 34.48–55.23% of hardware area. Compared with previous studies on the multi-modulus multiplier, the proposed architecture can save 22.78–35.46%, 4.12–11.15%, 12.59–24.73%, 27.88–38.88%, and 20.49–27.85% of hardware area, delay time, dissipation power, ADP, and PDP, respectively. Xilinx field programmable gate array (FPGA) Vivado 2019.2 tools and the Verilog hardware description language are used for synthesis and implementation. The Xilinx Artix-7 XC7A35T-CSG324-1 chipset is adopted to evaluate the performance.
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Kumar Ramachandragowda, Santhosh, Devaraju Ramakrishna, and Rajashree Narendra. "An efficient ultra-wideband digital transceiver for wireless applications on the field-programmable gate array platform." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 4 (August 1, 2023): 4432. http://dx.doi.org/10.11591/ijece.v13i4.pp4432-4440.
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<p>The ultra-wideband (UWB) technology is a promising short-range communication technology for most wireless applications. The UWB works at higher frequencies and is affected by interferences with the same frequency standards. This manuscript has designed an efficient and low-cost implementation of IEEE 802.15.4a-based UWB-digital transceiver (DTR). The design module contains UWB transmitter (TX), channel, and UWB-receiver (RX) units. Convolutional encoding and modulation units like burst position modulation and binary phase-shift keying modulation are used to construct the UWB-TX. The synchronization and Viterbi decoder units are used to recover the original data bits and are affected by noise in UWB-RX. The UWB-DTR is synthesized using Xilinx ISE<sup>®</sup> environment with Verilog hardware description language (HDL) and implemented on Artix-7 field-programmable gate array (FPGA). The UWB-DTR utilizes less than 2% (slices and look-up table/LUTs), operates at 268 MHz, and consumes 91 mW of total power on FPGA. The transceiver achieves a 6.86 Mbps data rate, which meets the IEEE 802.15.4a standard. The UWB-DTR module obtains the bit error rate (BER) of 2×10<sup>-4</sup> by transmitting 105 data bits. The UWB-DTR module is compared with similar physical layer (PHY) transceivers with improvements in chip area (slices), power, data rate, and BER. </p>
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Patil, Trupti, and Anuradha M. Sandi. "Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA." International Journal of Reconfigurable and Embedded Systems (IJRES) 13, no. 2 (July 1, 2024): 296. http://dx.doi.org/10.11591/ijres.v13.i2.pp296-306.
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The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.
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Sung, Guo-Ming, Li-Fen Tung, Chong-Cheng Huang, and Hong-Yuan Huang. "Modified Predictive Direct Torque Control ASIC with Multistage Hysteresis and Fuzzy Controller for a Three-Phase Induction Motor Drive." Electronics 11, no. 11 (June 6, 2022): 1802. http://dx.doi.org/10.3390/electronics11111802.
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This paper proposes a modified predictive direct torque control (MPDTC) application-specific integrated circuit (ASIC) with multistage hysteresis and fuzzy controller to address the ripple problem of hysteresis controllers and to have a low power consumption chip. The proposed MPDTC ASIC calculates the stator’s magnetic flux and torque by detecting three-phase currents, three-phase voltages, and the rotor speed. Moreover, it eliminates large ripples in the torque and flux by passing through the modified discrete multiple-voltage vector (MDMVV), and four voltage vectors were obtained on the basis of the calculated flux and torque in a cycle. In addition, the speed error was converted into a torque command by using the fuzzy PID controller, and rounding-off calculation was employed to decrease the calculation error of the composite flux. The proposed MDMVV switching table provides 294 combined voltage vectors to the following inverter. The proposed MPDTC scheme generates four voltage vectors in a cycle that can quickly achieve DTC function. The Verilog hardware description language (HDL) was used to implement the hardware architecture, and an ASIC was fabricated with a TSMC 0.18 μm 1P6M CMOS process by using a cell-based design method. Measurement results revealed that the proposed MPDTC ASIC performed with operating frequency, sampling rate, and dead time of 10 MHz, 100 kS/s, and 100 ns, respectively, at a supply voltage of 1.8 V. The power consumption and chip area of the circuit were 2.457 mW and 1.193 mm × 1.190 mm, respectively. The proposed MPDTC ASIC occupied a smaller chip area and exhibited a lower power consumption than the conventional DTC system did in the adopted FPGA development board. The robustness and convenience of the proposed MPDTC ASIC are especially advantageous.
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Bonament, Alexi, Alexis Prel, Jean-Michel Sallese, Christophe Lallement, and Morgan Madec. "Analytic modelling of passive microfluidic mixers." Mathematical Biosciences and Engineering 19, no. 4 (2022): 3892–908. http://dx.doi.org/10.3934/mbe.2022179.
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<abstract> <p>This paper deals with a new analytical model for microfluidic passive mixers. Two common approaches already exist for such a purpose. On the one hand, the resolution of the advection-diffusion-reaction equation (ADRE) is the first one and the closest to physics. However, ADRE is a partial differential equation that requires finite element simulations. On the other hand, analytical models based on the analogy between microfluidics and electronics have already been established. However, they rely on the assumption of homogeneous fluids, which means that the mixer is supposed to be long enough to obtain a perfect mixture at the output. In this paper, we derive an analytical model from the ADRE under several assumptions. Then we integrate these equations within the electronic-equivalent models. The resulting models computed the relationship between pressure and flow rate in the microfluidic circuit but also takes the concentration gradients that can appear in the direction perpendicular to the channel into account. The model is compared with the finite element simulation performed with COMSOL Multiphysics in several study cases. We estimate that the global error introduced by our model compared to the finite element simulation is less than 5% in every use case. In counterparts, the cost in terms of computational resources is drastically reduced. The analytical model can be implemented in a large range of modelling and simulation languages, including SPICE and hardware description language such as Verilog-AMS. This feature is very interesting in the context of the <italic>in silico</italic> prototyping of large-scale microfluidic devices or multi-physics devices involving microfluidic circuits, <italic>e.g.</italic> lab-on-chips.</p> </abstract>
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Sai, Thulasi Venkata, Sunku Vinay, Reddyvari Tharun, Vidyalavaru Subhash Reddy, Sadhu Vinay Kumar, and G. Padma Priya. "Implementation of 64-Bit RISC Processor Using Vedic Multiplier." International Journal for Research in Applied Science and Engineering Technology 12, no. 2 (February 29, 2024): 367–73. http://dx.doi.org/10.22214/ijraset.2024.58332.
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Abstract: In this project, 64 bit RISC processor designed with Vedic multiplier design. Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is mux- based full adders for building higher bit adders in an area and speed efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. A 64 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx Vivado 2018.3. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. Vedic Multiplier design is based on “Urdhva Triyakbhyam” which is among the 16 Vedic Sutras and MUX-Based Full Adders The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that savings in power in case of MAC and ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced in MAC and ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 64-bit Vedic processor is developed. This reduces the delay and saves area compared to conventional processor. Hence the improvement in speed of operation, and less area utilization are the key features of designed RISC processor.
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Chen, Qinlin, Nairen Zhang, Jinpeng Wang, Tian Tan, Chang Xu, Xiaoxing Ma, and Yue Li. "The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog." Proceedings of the ACM on Programming Languages 7, OOPSLA2 (October 16, 2023): 234–63. http://dx.doi.org/10.1145/3622805.
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With the increasing need to apply modern software techniques to hardware design, Verilog, the most popular Hardware Description Language (HDL), plays an infrastructure role. However, Verilog has several semantic pitfalls that often confuse software and hardware developers. Although prior research on formal semantics for Verilog exists, it is not comprehensive and has not fully addressed these issues. In this work, we present a novel scheme inspired by previous work on defining core languages for software languages like JavaScript and Python. Specifically, we define the formal semantics of Verilog using a core language called λ V , which captures the essence of Verilog using as few language structures as possible. λ V not only covers the most complete set of language features to date, but also addresses the aforementioned pitfalls. We implemented λ V with about 27,000 lines of Java code, and comprehensively tested its totality and conformance with Verilog. As a reliable reference semantics, λ V can detect semantic bugs in real-world Verilog simulators and expose ambiguities in Verilog’s standard specification. Moreover, as a useful core language, λ V has the potential to facilitate the development of tools such as a state-space explorer and a concolic execution tool for Verilog.
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PEISCHL, BERNHARD, NAVEED RIAZ, and FRANZ WOTAWA. "AUTOMATED DEBUGGING OF VERILOG DESIGNS." International Journal of Software Engineering and Knowledge Engineering 22, no. 05 (August 2012): 695–723. http://dx.doi.org/10.1142/s0218194012500209.
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In this article we report on novel insights in model-based software debugging of hardware description languages (HDLs). Today's simulation driven working process emphasizes the need for exploiting test suites not only for detecting but also for localizing the root cause of misbehavior. We discuss the modeling approaches for the various artifacts of the Verilog hardware description language (blocking and non-blocking statements, expressions, execution ordering) and present a novel model incorporating test suites. The evaluation of our approach on the well-known ISCAS89 benchmarks concerning single and double-fault diagnoses clearly indicates that incorporating test suites into the fault localization technique (and development process) considerably improves the accuracy of the obtained diagnosis candidates.
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KumarN, Naveen, Rohith S, and H. Venkatesh Kumar. "FPGA Implementation of OFDM Transceiver using Verilog - Hardware Description Language." International Journal of Computer Applications 102, no. 6 (September 18, 2014): 8–13. http://dx.doi.org/10.5120/17817-8752.
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Duley, Adam, Chris Spandikow, and Miryung Kim. "Vdiff: a program differencing algorithm for Verilog hardware description language." Automated Software Engineering 19, no. 4 (May 9, 2012): 459–90. http://dx.doi.org/10.1007/s10515-012-0107-6.
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Khan, Wilayat, Basim Azam, Noman Shahid, Abdul Moeed Khan, and Ahtisham Shaheen. "Formal Verification of Digital Circuits Using Simulator with Mathematical Foundation." Applied Mechanics and Materials 892 (June 2019): 134–42. http://dx.doi.org/10.4028/www.scientific.net/amm.892.134.
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To ease hardware design process, circuits are normally designed in description languages such as Verilog and VHDL. The correctness of circuits is normally checked by exhaustive simulation in simulators such as Icarus and VCS. Both the description languages Verilog/VHDL and simulators Icarus/VCS do not have mathematical foundations and hence are not reliable and cannot be used to mathematically prove correctness of circuit designs. Hardware description languages with mathematical (formal) foundation such as VeriFormal, on the other hand, are more reliable, trustworthy and can be used for robust design. In this paper, we report our results of formal verifications of two simple hardware circuits designed in the formal description language VeriFormal. Using the VeriFormal simulator and the accompanied type checker tools, we prove reliability properties type safety, functional correctness and functional equivalence of the digital circuits.
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Salauyou, Valery. "Structural models of Mealy finite state machines detecting faults in control systems." Radioelectronic and Computer Systems, no. 3 (September 29, 2023): 173–86. http://dx.doi.org/10.32620/reks.2023.3.14.
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The subject matter of this article is a control system for unmanned aerial vehicles (UAVs) whose mathematical model is a finite state machine (FSM). The goal is to develop FSM structural models that enable (1) detection of multiple faults of FSM elements caused by an electromagnetic pulse or laser beam, and (2) prevent negative impacts on the controlled object. The tasks to be solved are as follows: to develop FSM structural models to detect invalid input vector X for the whole FSM and in each state, to detect invalid output vector Y for the whole FSM, at each transition and in each state, invalid code of the present (current) state, invalid code of the next state, and invalid transition between states; to determine the possible causes of the faults, which can be the failure in the logic Φ of forming the code of the next state, the invalid input vector X, the failure in the feedback circuit, the failure in the logic Ψ of forming the output vector, the failure in the state register R, the failure in the wire between the FSM input and the input of the logic Ψ; development of a combined structural model for the detection of all listed faults with a minimum number of additional combinational circuits, as well as a structural model that combines all additional combinational circuits. The methods used are: the theory of finite state machines, structural models of FSMs, state encoding methods of FSMs, representation methods of FSMs, and Verilog hardware description language. The following results were obtained: (1) the Mealy FSM structural models were developed to detect all the above mentioned faults, (2) the combined FSM structural models were developed, and (3) the possible causes of faults detected by each FSM structural model were identified. Experimental studies have shown that for the presented FSM structural models, the area overhead averages 3-23%, for one-hot encoding of FSM states, and 2-8%, for binary encoding of FSM states. Conclusions. The scientific novelty of the obtained results consists in the following for the first time FSM faults that are not caused by radiation and cosmic rays but by an electromagnetic pulse affecting the control device are considered; the number of faults is not limited for the state codes as well as for the input and output vectors; the faults can be detected not only in the state register R but also in the input vector X, in the logic Φ of generating the next state code, in the logic Ψ of generating the output signals, and in the feedback circuit; the invalid transitions of FSMs and the transitions to invalid states are also detected; the proposed structural models not only detect FSM failures but also prevent their negative impact on the controlled object; combined structural models allow simultaneous detection of faults in all elements of the FSM. Future research will focus on developing structural models for correcting FSM failures.