Relevant bibliographies by topics / Verilog hardware description language

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
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Academic literature on the topic 'Verilog hardware description language'

Author: Grafiati
Published: 5 June 2025
Last updated: 16 July 2025

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Journal articles on the topic "Verilog hardware description language"

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Chen, Qinlin, Nairen Zhang, Jinpeng Wang, et al. "The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog." Proceedings of the ACM on Programming Languages 7, OOPSLA2 (2023): 234–63. http://dx.doi.org/10.1145/3622805.

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With the increasing need to apply modern software techniques to hardware design, Verilog, the most popular Hardware Description Language (HDL), plays an infrastructure role. However, Verilog has several semantic pitfalls that often confuse software and hardware developers. Although prior research on formal semantics for Verilog exists, it is not comprehensive and has not fully addressed these issues. In this work, we present a novel scheme inspired by previous work on defining core languages for software languages like JavaScript and Python. Specifically, we define the formal semantics of Veri
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PEISCHL, BERNHARD, NAVEED RIAZ, and FRANZ WOTAWA. "AUTOMATED DEBUGGING OF VERILOG DESIGNS." International Journal of Software Engineering and Knowledge Engineering 22, no. 05 (2012): 695–723. http://dx.doi.org/10.1142/s0218194012500209.

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In this article we report on novel insights in model-based software debugging of hardware description languages (HDLs). Today's simulation driven working process emphasizes the need for exploiting test suites not only for detecting but also for localizing the root cause of misbehavior. We discuss the modeling approaches for the various artifacts of the Verilog hardware description language (blocking and non-blocking statements, expressions, execution ordering) and present a novel model incorporating test suites. The evaluation of our approach on the well-known ISCAS89 benchmarks concerning sin
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Yan, Ziqi. "The application of Verilog in the development of casual games." Applied and Computational Engineering 76, no. 1 (2024): 245–49. http://dx.doi.org/10.54254/2755-2721/76/20240600.

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Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and inte
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KumarN, Naveen, Rohith S, and H. Venkatesh Kumar. "FPGA Implementation of OFDM Transceiver using Verilog - Hardware Description Language." International Journal of Computer Applications 102, no. 6 (2014): 8–13. http://dx.doi.org/10.5120/17817-8752.

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Duley, Adam, Chris Spandikow, and Miryung Kim. "Vdiff: a program differencing algorithm for Verilog hardware description language." Automated Software Engineering 19, no. 4 (2012): 459–90. http://dx.doi.org/10.1007/s10515-012-0107-6.

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Khan, Wilayat, Basim Azam, Noman Shahid, Abdul Moeed Khan, and Ahtisham Shaheen. "Formal Verification of Digital Circuits Using Simulator with Mathematical Foundation." Applied Mechanics and Materials 892 (June 2019): 134–42. http://dx.doi.org/10.4028/www.scientific.net/amm.892.134.

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To ease hardware design process, circuits are normally designed in description languages such as Verilog and VHDL. The correctness of circuits is normally checked by exhaustive simulation in simulators such as Icarus and VCS. Both the description languages Verilog/VHDL and simulators Icarus/VCS do not have mathematical foundations and hence are not reliable and cannot be used to mathematically prove correctness of circuit designs. Hardware description languages with mathematical (formal) foundation such as VeriFormal, on the other hand, are more reliable, trustworthy and can be used for robust
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Ho, Chia-Tung, Haoxing Ren, and Brucek Khailany. "VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool." Proceedings of the AAAI Conference on Artificial Intelligence 39, no. 1 (2025): 300–307. https://doi.org/10.1609/aaai.v39i1.32007.

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Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using coll
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Mekala, Priyanka, Jeffrey Fan, Wen-Cheng Lai, and Ching-Wen Hsue. "Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform." Advances in Software Engineering 2013 (February 24, 2013): 1–13. http://dx.doi.org/10.1155/2013/707248.

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Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design. To accelerate the computation of the gesture recognition technique, an HW/SW implementation using field programmable gate array (FPGA) technology is presented in this paper. The major contributions of this work are: (1) a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL) to reduce memory consumption and load on the p
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Azhari, Zul Imran, Samsul Setumin, Emilia Noorsal, and Mohd Hanapiah Abdullah. "Digital image enhancement by brightness and contrast manipulation using Verilog hardware description language." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1346. http://dx.doi.org/10.11591/ijece.v13i2.pp1346-1357.

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A foggy environment may cause digitally captured images to appear blurry, dim, or low in contrast. This will impact computer vision systems that rely on image information. With the need for real-time image information, such as a plate number recognition system, a simple yet effective image enhancement algorithm using a hardware implementation is very much needed to fulfil the need. To improve images that suffer from low exposure and hazy, the hardware implementations are usually based on complex algorithms. Hence, the aim of this paper is to propose a less complex enhancement algorithm for har
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Zul, Imran Azhari, Setumin Samsul, Noorsal Emilia, and Hanapiah Abdullah Mohd. "Digital image enhancement by brightness and contrast manipulation using Verilog hardware description language." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1346–57. https://doi.org/10.11591/ijece.v13i2.pp1346-1357.

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A foggy environment may cause digitally captured images to appear blurry, dim, or low in contrast. This will impact computer vision systems that rely on image information. With the need for real-time image information, such as a plate number recognition system, a simple yet effective image enhancement algorithm using a hardware implementation is very much needed to fulfil the need. To improve images that suffer from low exposure and hazy, the hardware implementations are usually based on complex algorithms. Hence, the aim of this paper is to propose a less complex enhancement algorithm for har
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Dissertations / Theses on the topic "Verilog hardware description language"

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Pace, Gordon G. "Hardware design based on Verilog HDL." Thesis, University of Oxford, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.298555.

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Chen, Adam Y. (Adam Yu-Chih). "Implementation of the Intel 486 SX microprocessor in Verilog hardware description language." Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/79470.

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Ou, Jen-Chieh. "HARDWARE DESCRIPTION LANGUAGE PROGRAM SLICING AND WAY TO REDUCE BOUNDED MODEL CHECKING SEARCH OVERHEAD." Case Western Reserve University School of Graduate Studies / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=case1159738055.

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GURUMURTHY, ARAVIND. "COMPARISON OF BEHAVIOR OF MOSFET TRANSISTORS DESCRIBED IN HARDWARE DESCRIPTION LANGUAGES." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1141363591.

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Feng, Zhiming Niu Guofu. "Compact modeling of SiGe HBTs using VERILOG-A." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Summer/Theses/FENG_ZHIMING_19.pdf.

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Leija, Carlos Ivan. "An artificial neural network with reconfigurable interconnection network." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2008. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.

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Bäck, Carl. "Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments." Thesis, Luleå tekniska universitet, Institutionen för system- och rymdteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-78738.

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FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. Developing code for FPGA applications usually requires knowledge about special languages, which are not common knowledge in the signal processing domain. High-level synthesis is an approach where high-level languages, as MATLAB or C++, can be used together with a code generation tool, to directly generate an FPGA ready output. This thesis uses the development of a histog
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Kasarabada, Yasaswy. "A Verilog Description and Efficient Hardware Implementation of the Baillie-PSW Primality Test." University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1471347471.

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Park, Su-Hyun. "ADH, Aspect Described Hardware-Description-Language." Thesis, University of Canterbury. Electrical and Computer Engineering, 2006. http://hdl.handle.net/10092/1113.

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Currently, many machine vision, signal and image processing problems are solved on personal computers due to the low cost involved in these computers and the many excellent software tools that exist, such as MATLAB. However, computationally expensive tasks require the use of multi-processor computers that are expensive and difficult to use efficiently due to communications between the processors. In these cases, FPGAs (Field Programmable Gate Arrays) are the best choice but they are not as widely used because of lack of experience in using these devices, difficulties with algorithmic translati
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Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

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Books on the topic "Verilog hardware description language"

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1953-, Moorby Philip R., ed. The Verilog hardware description language. Kluwer Academic Publishers, 1991.

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1953-, Moorby Philip R., ed. The Verilog hardware description language. 5th ed. Kluwer Academic Publishers, 2002.

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Thomas, D. E. The Verilog hardware description language. 2nd ed. Kluwer Academic Pub., 1995.

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1953-, Moorby Philip R., ed. The Verilog hardware description language. 3rd ed. Kluwer Academic Publishers, 1996.

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1953-, Moorby Philip R., ed. The Verilog hardware description language. 4th ed. Kluwer Academic Publishers, 1998.

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Thomas, Donald E., and Philip R. Moorby. The Verilog® Hardware Description Language. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2896-5.

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Thomas, Donald E., and Philip R. Moorby. The Verilog® Hardware Description Language. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6.

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Thomas, Donald E., and Philip R. Moorby. The Verilog® Hardware Description Language. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4757-2365-6.

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Thomas, Donald E., and Philip R. Moorby. The Verilog® Hardware Description Language. Springer US, 1996. http://dx.doi.org/10.1007/978-1-4757-2464-6.

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Engineers, Institute Of Electrical and Electronics. IEEE standard Verilog hardware description language. Institute of Electrical and Electronics Engineers, 2001.

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Book chapters on the topic "Verilog hardware description language"

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Thomas, Donald E., and Philip R. Moorby. "Verilog -- A Tutorial Introduction." In The Verilog® Hardware Description Language. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_1.

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Thomas, Donald E., and Philip R. Moorby. "Verilog — A Tutorial Introduction." In The Verilog® Hardware Description Language. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4757-2365-6_1.

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Thomas, Donald E., and Philip R. Moorby. "Verilog — A Tutorial Introduction." In The Verilog® Hardware Description Language. Springer US, 1996. http://dx.doi.org/10.1007/978-1-4757-2464-6_1.

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Thomas, Donald E., and Philip R. Moorby. "Verilog—A Tutorial Introduction." In The Verilog® Hardware Description Language. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2896-5_1.

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Bhargava, Cherry, and Gaurav Mani Khanal. "Verilog Hardware Descriptive Language." In Basic VLSI Design Technology. River Publishers, 2022. http://dx.doi.org/10.1201/9781003337300-4.

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Thomas, Donald E., and Philip R. Moorby. "Behavioral Modeling Constructs." In The Verilog® Hardware Description Language. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_2.

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Thomas, Donald E., and Philip R. Moorby. "Concurrent Process Statements." In The Verilog® Hardware Description Language. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_3.

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Thomas, Donald E., and Philip R. Moorby. "Logic Level Modeling." In The Verilog® Hardware Description Language. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_4.

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Thomas, Donald E., and Philip R. Moorby. "Defining Gate Level Primitives." In The Verilog® Hardware Description Language. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_5.

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Thomas, Donald E., and Philip R. Moorby. "Switch Level Modeling." In The Verilog® Hardware Description Language. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3992-6_6.

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Conference papers on the topic "Verilog hardware description language"

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Pang, Wai Leong, Tania Khatun, Swee King Phang, Ajay Kumar Singh, Angie See Tien Ng, and Kah Yoong Chan. "Optimizing Multiplier Performance Through Verilog Hardware Description Language Design." In 2024 Multimedia University Engineering Conference (MECON). IEEE, 2024. https://doi.org/10.1109/mecon62796.2024.10776217.

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Majeed, Bilal, Jack McEllin, Rajkumar Sarma, Ayman Youssef, Douglas Dias, and Conor Ryan. "Grammatical Evolution of Synthesizable Finite State Machine-Based Behavioural Level Hardware Description Language Codes." In 16th International Conference on Evolutionary Computation Theory and Applications. SCITEPRESS - Science and Technology Publications, 2024. http://dx.doi.org/10.5220/0012948300003837.

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Meacci, Valentino, Alessandro Dallai, Stefano Ricci, Enrico Boni, Piero Tortoli, and Alessandro Ramalli. "Hardware description language versus high-level synthesis for the FPGA implementation of ultrasound beamformers: a comparative analysis." In 2024 IEEE Ultrasonics, Ferroelectrics, and Frequency Control Joint Symposium (UFFC-JS). IEEE, 2024. https://doi.org/10.1109/uffc-js60046.2024.10793737.

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Ebeling, Carl, and Brian French. "Abstract Verilog: A Hardware Description Language for Novice Students." In 2007 IEEE International Conference on Microelectronic Systems Education. IEEE, 2007. http://dx.doi.org/10.1109/mse.2007.16.

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Patidar, Jitendra, Rajesh Khatri, and R. C. Gurjar. "Precision Agriculture System Using Verilog Hardware Description Language to Design an ASIC." In 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech). IEEE, 2019. http://dx.doi.org/10.1109/iementech48150.2019.8981128.

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Power, James F., and John Waldron. "Calibration and Analysis of Source Code Similarity Measures for Verilog Hardware Description Language Projects." In SIGCSE '20: The 51st ACM Technical Symposium on Computer Science Education. ACM, 2020. http://dx.doi.org/10.1145/3328778.3366928.

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Payal, Ravi, Akanksha Saxena, and Beena Chanda. "Implementation of Smart Home through FPGA using Verilog Hardware Descriptive Language." In 2020 IEEE International Conference on Advent Trends in Multidisciplinary Research and Innovation (ICATMRI). IEEE, 2020. http://dx.doi.org/10.1109/icatmri51801.2020.9398499.

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Guo, Xiaolong, Raj Gautam Dutta, Jiaji He, Mark M. Tehranipoor, and Yier Jin. "QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment." In 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2019. http://dx.doi.org/10.1109/hst.2019.8740840.

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Egorov, Nikolay, and Vasil Khisamov. "Low-Cost and Low-Power Radiofrequency Module with Small Dimensions Based on Wireless Protocol 6LoWPAN and Application of Hardware Description Language Verilog in IT." In 2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). IEEE, 2019. http://dx.doi.org/10.1109/eiconrus.2019.8657277.

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Zhen, Zhang, and Zhang Hui. "The Hardware Interface Design In SoC with Verilog Language." In 2009 IITA International Conference on Services Science, Management and Engineering (SSME). IEEE, 2009. http://dx.doi.org/10.1109/ssme.2009.65.

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Reports on the topic "Verilog hardware description language"

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Aylor, James, Robert Klenke, Ron Waxman, Paul Menchini, Jack Stinson, and Bill Anderson. VHSIC Hardware Description Language (VHDL) 200X Requirements Report/Survey. Defense Technical Information Center, 1999. http://dx.doi.org/10.21236/ada406178.

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Chung, Moon Jung. Parallel Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) Simulation for Performance Modeling. Defense Technical Information Center, 1999. http://dx.doi.org/10.21236/ada372678.

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Yang, Lian. The object-oriented design of a hardware description language analyser for the DIADES silicon compiler system. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.6144.

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Mills, Michael T. A Key Element Toward Concurrent Engineering of Hardware and Software: Binding Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) with Ada 95. Defense Technical Information Center, 1994. http://dx.doi.org/10.21236/ada294469.

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Mills, Michael T. Proposed Object Oriented Programming (OOP) Enhancements to the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada274004.

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Federal Information Processing Standards Publication: VHSIC hardware description language (VHDL). National Institute of Standards and Technology, 1995. http://dx.doi.org/10.6028/nist.fips.172-1-1995.

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