Dissertations / Theses on the topic 'Verilog hardware description language'
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Pace, Gordon G. "Hardware design based on Verilog HDL." Thesis, University of Oxford, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.298555.
Full textChen, Adam Y. (Adam Yu-Chih). "Implementation of the Intel 486 SX microprocessor in Verilog hardware description language." Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/79470.
Full textOu, Jen-Chieh. "HARDWARE DESCRIPTION LANGUAGE PROGRAM SLICING AND WAY TO REDUCE BOUNDED MODEL CHECKING SEARCH OVERHEAD." Case Western Reserve University School of Graduate Studies / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=case1159738055.
Full textGURUMURTHY, ARAVIND. "COMPARISON OF BEHAVIOR OF MOSFET TRANSISTORS DESCRIBED IN HARDWARE DESCRIPTION LANGUAGES." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1141363591.
Full textFeng, Zhiming Niu Guofu. "Compact modeling of SiGe HBTs using VERILOG-A." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Summer/Theses/FENG_ZHIMING_19.pdf.
Full textLeija, Carlos Ivan. "An artificial neural network with reconfigurable interconnection network." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2008. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.
Full textBäck, Carl. "Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments." Thesis, Luleå tekniska universitet, Institutionen för system- och rymdteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-78738.
Full textKasarabada, Yasaswy. "A Verilog Description and Efficient Hardware Implementation of the Baillie-PSW Primality Test." University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1471347471.
Full textPark, Su-Hyun. "ADH, Aspect Described Hardware-Description-Language." Thesis, University of Canterbury. Electrical and Computer Engineering, 2006. http://hdl.handle.net/10092/1113.
Full textWang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.
Full textBlumenthal, Carl. "Development of the NoGAP CL Hardware Description Language and its Compiler." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8865.
Full textCosti, Claudio. "A methodology for analyzing hardware description language specifications of legacy designs." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/NQ58564.pdf.
Full textDailey, David M. "Integration of VHDL simulation and test verification into a Process Model Graph design environment." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-11242009-020247/.
Full textShah, Sandeep R. "A framework for synthesis from VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-03022010-020143/.
Full textWright, Philip A. "Rapid development of VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-11102009-020056/.
Full textSama, Anil. "Behavior modeling of RF systems with VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-10102009-020211/.
Full textRao, Sanat R. "A hierarchical approach to effective test generation for VHDL behavioral models." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-08042009-040513/.
Full textMacklin, Kendrick R. "Suitability of the SRC-6E reconfigurable computing system for generating false radar image." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2004. http://library.nps.navy.mil/uhtbin/hyperion/04Jun%5FMacklin.pdf.
Full textKoelmans, Albertus Maria. "STRICT : a language and tool set for the design of very large scale integrated circuits." Thesis, University of Newcastle Upon Tyne, 1996. http://hdl.handle.net/10443/2076.
Full textRead, Simon. "Formal methods for VLSI design." Thesis, University of Manchester, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239786.
Full textWilhelm, Kyle. "Aspects of hardware methodologies for the NTRU public-key cryptosystem /." Online version of thesis, 2008. http://hdl.handle.net/1850/7774.
Full textChadha, Vikrampal. "Simulation of large-scale system-level models." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12162009-020334/.
Full textHoncharik, Alexander J. "Generation of VHDL from conceptual graphs of informal specifications." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-06162009-063028/.
Full textEdwards, Carleen Marie. "Representation and simulation of a high level language using VHDL." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-11242009-020306/.
Full textManek, Meenakshi. "Natural language interface to a VHDL modeling tool." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-06232009-063212/.
Full textVan, Tassel John Peter. "Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistant." Thesis, University of Cambridge, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.308190.
Full textYang, Lian. "The object-oriented design of a hardware description language analyser for the DIADES silicon compiler system." PDXScholar, 1990. https://pdxscholar.library.pdx.edu/open_access_etds/4260.
Full textGuthrie, Thomas G. "Design, implementation, and testing of a software interface between the AN/SPS-65(V)1 radar and the SRC-6E reconfigurable computer." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2005. http://library.nps.navy.mil/uhtbin/hyperion/05Mar%5FGuthrie.pdf.
Full textGoeke, James A. "Design of a hardware efficient key generation algorithm with a VHDL implementation /." Online version of thesis, 1993. http://hdl.handle.net/1850/11664.
Full textYang, Ming-Jie. "Design and Implementation of a Compiler for an XML-based Hardware Description Language to Support Energy Optimization." Thesis, Linköpings universitet, Programvara och system, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-143655.
Full textMacklin, Kendrick R. "Benchmarking and analysis of the SRC-6E reconfigurable computing system." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Dec%5FMacklin.pdf.
Full textBarton, Jonathan L. "Hardware implementation of a synchronization state buffer in VHDL." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 67 p, 2008. http://proquest.umi.com/pqdweb?did=1459924801&sid=13&Fmt=2&clientId=8331&RQT=309&VName=PQD.
Full textCosta, Richard Maciel. "Metodologia e projeto de ferramenta para co-simulação entre VHDL e SystemC." [s.n.], 2008. http://repositorio.unicamp.br/jspui/handle/REPOSIP/276135.
Full textArdeishar, Raghu. "Automatic verification of VHDL models." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/.
Full textShrivastava, Vikram M. "Mapping conceptual graphs to primitive VHDL processes." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-05022009-040536/.
Full textChu, Ming-Cheung. "Hazard detection with VHDL in combinational logic circuits with fixed delays." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10062009-020040/.
Full textNouman, Ziad. "Užití programovatelných hradlových polí v systémech průmyslové automatizace." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-234615.
Full textPoetter, Alexandra Vanessa. "JHDLBits: An Open-Source Model for FPGA Design Automation." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/10121.
Full textPan, Bi-Yu. "Hierarchical test generation for VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-09052009-040449/.
Full textPalanisamy, Karthikeyan. "High Level Preprocessor of a VHDL-based Design System." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4776.
Full textSprunger, Steven J. "UML modeling for VHDL designs." Virtual Press, 2008. http://liblink.bsu.edu/uhtbin/catkey/1399192.
Full textFanelli, Paul. "VHDL modeling and design of an asynchronous version of the MIPS R3000 microprocessor /." Online version of thesis, 1994. http://hdl.handle.net/1850/11157.
Full textGiannopoulos, Vassilis. "Efficient VHDL models for various PLD architectures /." Online version of thesis, 1995. http://hdl.handle.net/1850/12238.
Full textSingh, Balraj. "A parametrized CAD tool for VHDL model development with X Windows." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03242009-040819/.
Full textGadagkar, Ashish. "Timing distribution in VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10102009-020318/.
Full textMoustakas, Evangelos. "Design and simulation of a primitive RISC architecture using VHDL /." Online version of thesis, 1991. http://hdl.handle.net/1850/11229.
Full textFrandina, Peter. "VHDL modeling and synthesis of the JPEG-XR inverse transform /." Online version of thesis, 2009. http://hdl.handle.net/1850/10755.
Full textOliveira, Alexandre Tomazati. "Detecção do complexo QRS em sinais cardiacos utilizando FPGA." [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/264060.
Full textChen, Wei-chun. "Simulation of a morphological image processor using VHDL. mathematical components /." Online version of thesis, 1993. http://hdl.handle.net/1850/11872.
Full textChen, Hao. "Simulation of a morphological image processor using VHDL. control mechanism /." Online version of thesis, 1993. http://hdl.handle.net/1850/11744.
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