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Journal articles on the topic 'Verilog hardware description language'

Author: Grafiati

Published: 5 June 2025

Last updated: 16 July 2025

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1

Chen, Qinlin, Nairen Zhang, Jinpeng Wang, et al. "The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog." Proceedings of the ACM on Programming Languages 7, OOPSLA2 (2023): 234–63. http://dx.doi.org/10.1145/3622805.

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With the increasing need to apply modern software techniques to hardware design, Verilog, the most popular Hardware Description Language (HDL), plays an infrastructure role. However, Verilog has several semantic pitfalls that often confuse software and hardware developers. Although prior research on formal semantics for Verilog exists, it is not comprehensive and has not fully addressed these issues. In this work, we present a novel scheme inspired by previous work on defining core languages for software languages like JavaScript and Python. Specifically, we define the formal semantics of Veri

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PEISCHL, BERNHARD, NAVEED RIAZ, and FRANZ WOTAWA. "AUTOMATED DEBUGGING OF VERILOG DESIGNS." International Journal of Software Engineering and Knowledge Engineering 22, no. 05 (2012): 695–723. http://dx.doi.org/10.1142/s0218194012500209.

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In this article we report on novel insights in model-based software debugging of hardware description languages (HDLs). Today's simulation driven working process emphasizes the need for exploiting test suites not only for detecting but also for localizing the root cause of misbehavior. We discuss the modeling approaches for the various artifacts of the Verilog hardware description language (blocking and non-blocking statements, expressions, execution ordering) and present a novel model incorporating test suites. The evaluation of our approach on the well-known ISCAS89 benchmarks concerning sin

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Yan, Ziqi. "The application of Verilog in the development of casual games." Applied and Computational Engineering 76, no. 1 (2024): 245–49. http://dx.doi.org/10.54254/2755-2721/76/20240600.

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Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and inte

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KumarN, Naveen, Rohith S, and H. Venkatesh Kumar. "FPGA Implementation of OFDM Transceiver using Verilog - Hardware Description Language." International Journal of Computer Applications 102, no. 6 (2014): 8–13. http://dx.doi.org/10.5120/17817-8752.

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Duley, Adam, Chris Spandikow, and Miryung Kim. "Vdiff: a program differencing algorithm for Verilog hardware description language." Automated Software Engineering 19, no. 4 (2012): 459–90. http://dx.doi.org/10.1007/s10515-012-0107-6.

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Khan, Wilayat, Basim Azam, Noman Shahid, Abdul Moeed Khan, and Ahtisham Shaheen. "Formal Verification of Digital Circuits Using Simulator with Mathematical Foundation." Applied Mechanics and Materials 892 (June 2019): 134–42. http://dx.doi.org/10.4028/www.scientific.net/amm.892.134.

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To ease hardware design process, circuits are normally designed in description languages such as Verilog and VHDL. The correctness of circuits is normally checked by exhaustive simulation in simulators such as Icarus and VCS. Both the description languages Verilog/VHDL and simulators Icarus/VCS do not have mathematical foundations and hence are not reliable and cannot be used to mathematically prove correctness of circuit designs. Hardware description languages with mathematical (formal) foundation such as VeriFormal, on the other hand, are more reliable, trustworthy and can be used for robust

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Ho, Chia-Tung, Haoxing Ren, and Brucek Khailany. "VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool." Proceedings of the AAAI Conference on Artificial Intelligence 39, no. 1 (2025): 300–307. https://doi.org/10.1609/aaai.v39i1.32007.

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Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using coll

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Mekala, Priyanka, Jeffrey Fan, Wen-Cheng Lai, and Ching-Wen Hsue. "Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform." Advances in Software Engineering 2013 (February 24, 2013): 1–13. http://dx.doi.org/10.1155/2013/707248.

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Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design. To accelerate the computation of the gesture recognition technique, an HW/SW implementation using field programmable gate array (FPGA) technology is presented in this paper. The major contributions of this work are: (1) a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL) to reduce memory consumption and load on the p

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Azhari, Zul Imran, Samsul Setumin, Emilia Noorsal, and Mohd Hanapiah Abdullah. "Digital image enhancement by brightness and contrast manipulation using Verilog hardware description language." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1346. http://dx.doi.org/10.11591/ijece.v13i2.pp1346-1357.

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A foggy environment may cause digitally captured images to appear blurry, dim, or low in contrast. This will impact computer vision systems that rely on image information. With the need for real-time image information, such as a plate number recognition system, a simple yet effective image enhancement algorithm using a hardware implementation is very much needed to fulfil the need. To improve images that suffer from low exposure and hazy, the hardware implementations are usually based on complex algorithms. Hence, the aim of this paper is to propose a less complex enhancement algorithm for har

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Zul, Imran Azhari, Setumin Samsul, Noorsal Emilia, and Hanapiah Abdullah Mohd. "Digital image enhancement by brightness and contrast manipulation using Verilog hardware description language." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1346–57. https://doi.org/10.11591/ijece.v13i2.pp1346-1357.

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A foggy environment may cause digitally captured images to appear blurry, dim, or low in contrast. This will impact computer vision systems that rely on image information. With the need for real-time image information, such as a plate number recognition system, a simple yet effective image enhancement algorithm using a hardware implementation is very much needed to fulfil the need. To improve images that suffer from low exposure and hazy, the hardware implementations are usually based on complex algorithms. Hence, the aim of this paper is to propose a less complex enhancement algorithm for har

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Pelton, Blake, Adam Sapek, Ken Eguro, et al. "Wavefront Threading Enables Effective High-Level Synthesis." Proceedings of the ACM on Programming Languages 8, PLDI (2024): 1066–90. http://dx.doi.org/10.1145/3656420.

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Digital systems are growing in importance and computing hardware is growing more heterogeneous. Hardware design, however, remains laborious and expensive, in part due to the limitations of conventional hardware description languages (HDLs) like VHDL and Verilog. A longstanding research goal has been programming hardware like software, with high-level languages that can generate efficient hardware designs. This paper describes Kanagawa, a language that takes a new approach to combine the programmer productivity benefits of traditional High-Level Synthesis (HLS) approaches with the expressibilit

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Fernando, Martínez Santa, Jacinto Edwar, and Montiel Holman. "Hardware description of a simplified 4-bit softcore processor with bcd capabilities." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1570–76. https://doi.org/10.11591/ijece.v10i2.pp1570-1576.

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The objective of the work reported in this paper is to improve a 4-bit softcore processor previously designed in Verilog language, keeping its compact size. This processor was thought to be used as academic and didactic tool for teaching as computers architecture subject as digital circuits subject in the technology faculty of the Universidad Distrital. The new features include arithmetic instruction with input carry, BCD operations enabling, rotating instructions, implementation of input and output register banks, increase of the number of general purpose registers of the data memory, and the

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Kukenska, Valentina, Petar Minev, Ilian Varbov, and Matyo Dinev. "A Model for Online Learning in Digital Hardware Design." Innovative STEM Education 5, no. 1 (2023): 103–11. http://dx.doi.org/10.55630/stem.2023.0513.

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The report presents a model of a calculator with a stack architecture. It is developed in the hardware description language TL-Verilog. The model is designed for online learning in a development environment for digital hardware design. It is part of a set of models used for training students and doctoral students at Technical University - Gabrovo.

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Ibrahimy, Muhammad Ibn. "FPGA Implementation of Multiplier for Floating-Point Numbers Based on IEEE 754-2008 Standard." Journal of Communications Technology, Electronics and Computer Science 1 (October 22, 2015): 1. http://dx.doi.org/10.22385/jctecs.v1i0.2.

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This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis etc. Implementation of floating-point multiplication is handy and easy for high level language. However it is a challenging task to implement a floating-point multiplication in hardware level/low level language due to the complexity of algorithm. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floati

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Zhang, Ming, Hao Ting Liu, and Yu Wang. "The Design of the Multifunctional Electronic Timing System Based on the Verilog HDL Language." Applied Mechanics and Materials 182-183 (June 2012): 763–67. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.763.

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Verilog is the most widely used hardware description language. It can be used in the modeling, synthesis, and simulation stages of the hardware system designing. This thesis is about applying Verilog HDL to design the multifunctional electronic timing system. This system has brought about the timing function, the Alarm clock function, the time checking module, the stop clock module, the exact hour alarming module, the alarm clock’s shielding and alarming function module and the stop clock Prompting function module. The modules which have applied this design can be transplanted to other kinds o

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Janson, T., and U. Kebschull. "Modern C++17 data pre-processing HLS Datflow Template Library." Journal of Instrumentation 18, no. 02 (2023): C02050. http://dx.doi.org/10.1088/1748-0221/18/02/c02050.

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Abstract Developing and implementing algorithms for detector read-out using FPGAs is traditionally done by using a hardware description language like VHDL, Verilog, or System Verilog. In the proposed approach here, we discuss an alternative way using higher level languages like the Intel HLS Compiler. Intel HLS supports C++17 standard and is ideal to apply methods from Modern C++ to implement complex algorithms more easily. In this work, we have developed a dataflow template library. This enables a shorter development time for increasingly complex algorithm requirements, which is also importan

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Wisniewski, Remigiusz. "Design of Petri Net-Based Cyber-Physical Systems Oriented on the Implementation in Field Programmable Gate Arrays." Energies 14, no. 21 (2021): 7054. http://dx.doi.org/10.3390/en14217054.

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Two design flows of the Petri net-based cyber-physical systems oriented towards implementation in an FPGA are presented in the paper. The first method is based on the behavioural description of the system. The control part of the cyber-physical system is specified by an interpreted Petri net, and is described directly in the synthesisable Verilog hardware language for further implementation in the programmable device. The second technique involves splitting the design into sequential modules. In particular, adequate decomposition and synchronisation algorithms are proposed. The resulting modul

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Sumathi, M., D. Nirmala, and R. Immanuel Rajkumar. "Study of Data Security Algorithms using Verilog HDL." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 5 (2015): 1092. http://dx.doi.org/10.11591/ijece.v5i5.pp1092-1101.

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This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using Mod

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H. Lai, Phuong. "Analysis and implementation of SDF Radix-2 FFT processor using VERILOG Hardware Description Language." International Journal of Advanced Trends in Computer Science and Engineering 9, no. 4 (2020): 5185–89. http://dx.doi.org/10.30534/ijatcse/2020/144942020.

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Dang, Hieu V. "Design and Verification of novel classical error control codes using VERILOG Hardware Description Language." International Journal of Advanced Trends in Computer Science and Engineering 9, no. 4 (2020): 5762–67. http://dx.doi.org/10.30534/ijatcse/2020/232942020.

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Lee, Yung-Chong, Yee Kit Chan, and Voon Chet Koo. "DESIGN AND IMPLEMENTATION OF FPGA-BASED FFT CO-PROCESSOR USING VERILOG HARDWARE DESCRIPTION LANGUAGE." Progress In Electromagnetics Research B 92 (2021): 47–70. http://dx.doi.org/10.2528/pierb20122806.

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22

Preeti, S. Bellerimath, Shirakol Shrikanth, Vadiraj Gunari Laxmi, Rachana N, P. Mahat Sahil, and Arali Chirag. "Design and Implementation of AHB to APB Bridge using Verilog." International Journal of Engineering and Management Research 15, no. 2 (2025): 199–203. https://doi.org/10.5281/zenodo.15478857.

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Efficient on-chip communication is vital in modern embedded and System-on-Chip (SoC) architectures. This project presents the design and implementation of an AHB (Advanced High-performance Bus) to APB (Advanced Peripheral Bus) bridge using Verilog Hardware Description Language (HDL). The bridge serves as an interface between high-speed AHB masters and low-speed APB peripherals, with a Finite State Machine (FSM) governing the control flow—including address decoding, data transfer, and handshake signal management. The Verilog-based design emphasizes modularity, timing accuracy, and hardwar

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Santa, Fernando Martínez, Edwar Jacinto, and Holman Montie. "Hardware description of a simplified 4-bit softcore processor with BCD capabilities." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1570. http://dx.doi.org/10.11591/ijece.v10i2.pp1570-1576.

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The objective of the work reported in this paper is to improve a 4-bit softcore processor previously designed in Verilog language, keeping its compact size. This processor was thought to be used as academic and didactic tool for teaching as computers architecture subject as digital circuits subject in the technology faculty of the Universidad Distrital. The new features include arithmetic instruction with input carry, BCD operations enabling, rotating instructions, implementation of input and output register banks, increase of the number of general purpose registers of the data memory, and the

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Krishna, B. Murali, B. T. Krishna, and K. Babulu. "Hardware Implementation of Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution Transform on FPGA using CORDIC Algorithm." International Journal of Recent Technology and Engineering (IJRTE) 10, no. 5 (2022): 57–60. http://dx.doi.org/10.35940/ijrte.e6705.0110522.

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A comparison of linear and quadratic transform implementation on field programmable gate array (FPGA) is presented. Popular linear transform namely Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution (SPWVD) transform from Quadratic transforms is considered for the implementation on FPGA. Both the transforms are coded in Verilog hardware description language (Verilog HDL). Complex calculations of transformation are performed by using CORDIC algorithm. From FPGA family, Spartan-6 is chosen as hardware device to implement. Synthetic chirp signal is taken as input to test the both d

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B, Murali Krishna, Krishna B.T., and Babulu K. "Hardware Implementation of Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution Transform on FPGA using CORDIC Algorithm." International Journal of Recent Technology and Engineering (IJRTE) 10, no. 5 (2022): 57–60. https://doi.org/10.35940/ijrte.E6705.0110522.

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A comparison of linear and quadratic transform implementation on field programmable gate array (FPGA) is presented. Popular linear transform namely Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution (SPWVD) transform from Quadratic transforms is considered for the implementation on FPGA. Both the transforms are coded in Verilog hardware description language (Verilog HDL). Complex calculations of transformation are performed by using CORDIC algorithm. From FPGA family, Spartan-6 is chosen as hardware device to implement. Synthetic chirp signal is taken as input to test the both d

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Renuka, G., V. Usha Shree, and P. Chandra Sekhar Reddy. "Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microblaze Soft Core Processor." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 5 (2018): 3544. http://dx.doi.org/10.11591/ijece.v8i5.pp3544-3549.

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Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.

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G., Renuka, Usha Shree V., and Chandra Sekhar Reddy P. "Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microblaze Soft Core Processor." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 5 (2018): 3544–49. https://doi.org/10.11591/ijece.v8i5.pp3544-3549.

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Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.

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M P, Ranganatha. "Implementation of SPI Protocol using Verilog." International Journal for Research in Applied Science and Engineering Technology 13, no. 2 (2025): 1619–30. https://doi.org/10.22214/ijraset.2025.67182.

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The implementation of communication protocols using Verilog presents a novel approach to digital communication system design. This project explores the development and integration of various communication protocols within the Verilog hardware description language (HDL) framework. The primary focus lies in the synthesis of protocols such as SPI (Serial Peripheral Interface). The report begins by discussing the fundamental concepts behind Verilog HDL and its relevance in digital system design. It then explores into the detailed architecture and functionality of each communication protocol target

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Shinde, Vaishnavi, Zeba Karpude, Pooja Kolhe, and Alpesh Wadte. "Design and Simulation of 32-Bit RISC Architecture Based on MIPS using Verilog." International Scientific Journal of Engineering and Management 04, no. 03 (2025): 1–7. https://doi.org/10.55041/isjem02553.

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VERILOG Very High-Speed Integrated Circuits Hardware Description Language) is widely used for ASIC (Application Specific Integrated Circuits) emulation, as well as a solution for applications with high volatility. FPGA (Field Programmable Gate Array) give quick time to market, and its feature of re-programmability often makes them the main part of the system. This paper presents the design of a RISC (Reduced Instruction Set Computer) CPU architecture based on MIPS (Microprocessor Interlock Pipeline Stages) using Verilog. It also describes the instruction set, architecture and timing diagram of

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Huang, Xiang Sheng. "Design of AD Controller Customized IP Core Based on FPGA." Applied Mechanics and Materials 727-728 (January 2015): 859–62. http://dx.doi.org/10.4028/www.scientific.net/amm.727-728.859.

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This design elaborates thedevelopment process of the custom IP core AD9280 controller based on FPGA. Thedesign uses FPGA as the core of the microcontroller, realizes the function ofAD controller by adopting the hardware description language,Verilog HDL and encapsulates it to the custom IP core in the SOPCBuilder. In the NIOS II, the application program interface (API) function ofthe AD controller software is used to access and control the hardware, thesoftware is written by using C language. The experimental results show thatthis custom IP core is feasible and flexible, fully reflects the adva

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Rifqie, Dary Mochamad, Yasser Abd Djawad, Faizal Arya Samman, Ansari Saleh Ahmar, and M. Miftach Fakhri. "Design of Quantized Deep Neural Network Hardware Inference Accelerator Using Systolic Architecture." Journal of Applied Science, Engineering, Technology, and Education 6, no. 1 (2024): 27–33. https://doi.org/10.35877/454ri.asci2689.

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This paper presents a hardware inference accelerator architecture of quantized deep neural networks (DNN). The proposed accelerator implements all computation in a quantize version of DNN including linear transformations like matrix multiplications, nonlinear activation functions such as ReLU, quantization and dequantization operation. The hardware accelerator of quantized DNN consists of matrix multiplication core which is implemented in systolic array architecture, and the QDR core for computing the operation of quantization, dequantization, and ReLU. This proposed hardware architecture is i

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Vidya, Sagar Potharaju*. "FPGA IMPLEMENTATION OF ELLIPTIC CURVE DISCRETE LOGARITHMUSING VERILOG HDL." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 4, no. 11 (2017): 151–62. https://doi.org/10.5281/zenodo.1067986.

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Elliptic Curve Discrete Logarithm (ECDL) are most popular choice Elliptic Curve Cryptography (ECC),which gives provision for shorter key lengths as compared to as compared to its counterpart public key cryptosystems, and it can be used for security in embedded systems,wirless communications and personal communication systems. In this paper Elliptic Curve Discrete Logarithm code has been written in Verilog Hardware Description Language (HDL) and implemented on Xilinx Spartan3E Field Programmable Gate Array (FPGA),has taken 403 encoders, decoders with minimum period of 5.043 ns,maximum frequency

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Alidoust Aghdam, Farid, and Siamak Saeidi Haghi. "Implementation of High Performance Microstepping Driver Using FPGA with the Aim of Realizing Accurate Control on a Linear Motion System." Chinese Journal of Engineering 2013 (December 18, 2013): 1–8. http://dx.doi.org/10.1155/2013/425093.

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This paper presents an FPGA-based microstepping driver which drives a linear motion system with a smooth and precise way. Proposed driver built on a Spartan3 FPGA (XC3S400 core) development board from Xilinx. Implementation of driver realized by an FPGA and using Verilog hardware description language in the Xilinx ISE environment. The driver’s control behavior can be adapted just by altering Verilog scripts. In addition, a linear motion system developed (with 4 mm movement per motor revolution) and coupled it to the stepper motor. The performance of the driver is tested by measuring the distan

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B. Ravi kumar, Kunta Nikhitha, Punnami Manogna, and Begampeta Nanda kishore. "Implement I2C Protocol for Secure Data Transfer Using Verilog." International Research Journal on Advanced Science Hub 7, no. 01 (2025): 51–59. https://doi.org/10.47392/irjash.2025.007.

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Digital The I2C (Inter-Integrated Circuit) protocol is widely used in embedded systems for enabling communication between various devices such as sensors, microcontrollers, and other peripherals. However, early implementations of the I2C protocol focused primarily on data transfer efficiency rather than security This project aims to implement a secure data transfer mechanism for the I2C protocol using Verilog, a hardware description language widely used for designing and modelling electronic systems. Our implementation enhances the traditional I2C protocol by integrating security features that

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Silaparasetti, Kumar Vara Prasad* DP Raju. "AREA OPTIMIZED ROUTER ARCHITECTURE." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 4 (2017): 477–80. https://doi.org/10.5281/zenodo.556369.

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This Paper is proposing implementation of Router and verifies the functionality of the three port router with latest verification methodologies. This Router design contains three output ports and one input port, and this design implemented based on packet based Protocol. This proposed router contains Registers and FIFO with error checking. The proposed structure implemented using Verilog hardware description language and on Xilinx 14.7.

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Zheng, Hua Qiang, Li Fu Ma, Yang Liu, and Fei Cai. "Real-Time Video Convert System Design Based on LVDS." Advanced Materials Research 159 (December 2010): 514–21. http://dx.doi.org/10.4028/www.scientific.net/amr.159.514.

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In this paper, we designed a real-time video convert system for the imaging devices which used digital precision progressive scan monochrome camera or the similar camera and as video signal sensor. System hardware circuit design based on LVDS transmission chip, multiformat video decoder chip: ADV718X and the Cyclone II series FPGA. System software design based on hardware description language, verilog HDL and VHDL. The system could real-time capture, process CVBS and output LVDS video data without the system computer.

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Herklotz, Yann, James D. Pollard, Nadesh Ramanathan, and John Wickerson. "Formal verification of high-level synthesis." Proceedings of the ACM on Programming Languages 5, OOPSLA (2021): 1–30. http://dx.doi.org/10.1145/3485494.

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High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language such as Verilog, while maintaining the convenience and the rich ecosystem of software development. However, current HLS tools cannot always guarantee that the hardware designs they produce are equivalent to the software they were given, thus undermining any

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Kumar, Dr B. Ravi, Katte Srisha, and Boppana Akhila. "Realization of Advanced Peripheral Bus(APB) Protocol using Verilog." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–9. https://doi.org/10.55041/ijsrem40283.

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This project details the Verilog implementation of the Advanced Peripheral Bus (APB) protocol, focusing on a configuration with one master and multiple slaves. As part of the Advanced Microcontroller Bus Architecture (AMBA), the APB protocol plays a crucial role in facilitating communication between a master, such as a microcontroller, and various peripheral devices (slaves) within System-on-Chip (SoC) designs. The design, created using Verilog—a prominent hardware description language—follows industry standards with an emphasis on modularity and scalability. Key aspects of the APB protocol ar

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Yudachev, S. S., S. S. Sitnikov, and P. A. Monakhov. "Random-access memory coding in the Verilog description language for solving problems in radio electronics and mechanical engineering." Glavnyj mekhanik (Chief Mechanic), no. 6 (May 25, 2021): 74–79. http://dx.doi.org/10.33920/pro-2-2106-06.

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The article proposes a variant of writing an algorithm for the operation of a device used in a field-programmable gate array on the example of random-access memory coding using the Verilog hardware description language. When performing the work, the Xilinx software is used, which allows working with the project at all stages of creating and describing the operation of the device logic. The practical significance of the work is the study and solution of the simplest problems in the development of modern radioelectronic rapid response devices in the Verilog hardware description language, such as

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Reddy, Bharathi, D. Leela Rani, and Prof S. Varadarajan. "HIGH SPEED CARRY SAVE MULTIPLIER BASED LINEAR CONVOLUTION USING VEDIC MATHAMATICS." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 4, no. 2 (2013): 284–87. http://dx.doi.org/10.24297/ijct.v4i2a2.3173.

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VLSI applications include Digital Signal Processing, Digital control systems, Telecommunications, Speech and Audio processing for audiology and speech language pathology. The latest research in VLSI is the design and implementation of DSP systems which are essential for above applications. The fundamental computation in DSP Systems is convolution. Convolution and LTI systems are the heart and soul of DSP. The behavior of LTI systems in continuous time is described by Convolution integral whereas the behavior in discrete-time is described by Linear convolution. In this paper, Linear convolution

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Bindal, Kirti, Mukul Sharma, and Rachit Agarwal. "Design and Implementation of SRAM Using Verilog." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (2024): 117–24. http://dx.doi.org/10.22214/ijraset.2024.58708.

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Abstract: This comprehensive review delves into the intricate realm of the Static Random-Access Memory (SRAM) design and implementation, elucidating its pivotal role in shaping the performance, efficiency, and reliability of contemporary electronic systems, involving applications in ASIC devices. With a primary focus on the integration of Verilog, a hardware description language (HDL), the paper provides an in-depth background on SRAM, meticulously detailing its architecture, operation, and overall significance in electronic systems. The review meticulously addresses challenges inherent in SRA

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Lian, Ji Hong, and Kai Chen. "Implementation of DES Encryption Algorithm Based on FPGA and Performance Analysis." Applied Mechanics and Materials 130-134 (October 2011): 2953–56. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.2953.

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This paper introduced the principle of DES encryption algorithm, designed and realized the DES encryption algorithm with verilog hardware description language, realized module simulation with Quartus II. Two comprehensive considerations from the resources and performance, one pipeline stage control is set in round function to improve the processing speed, Synchronous pipeline architecture of data XOR key round function and Key transformation function is realized on hardware to reducing logic complexity of the adjacent pipeline, round function multiplexing is realized by setting the round count

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Zhou, Qing Fang, Qian Huang, Ying Yuan, and Jun Yang. "Design and Implementation of Reconfigurable Encryption and Decryption System Based on SOPC." Applied Mechanics and Materials 347-350 (August 2013): 2979–82. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.2979.

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The system is based on DES/3DES, AES cipher algorithm as the research object.According to the characteristics of the algorithm, designs a configuration mode which can share resource in space and configurate algorithm in time. Then it uses hardware description language Verilog HDL to realize and optimize the design, and completes a custom reconfigurable DES/3DES/AES encryption/decryption IP core. By SOPC technology, the IP core, Nios II processor, network controller and other function. The design hardware structureis simple, flexibility, security, which can be widely used in the field of inform

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Wang, Lie, and Yi Jie Wang. "Implementation of CRC by Using FPGA in Data Communication." Applied Mechanics and Materials 325-326 (June 2013): 1805–8. http://dx.doi.org/10.4028/www.scientific.net/amm.325-326.1805.

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By introducing the basic principle of ordinary CRC algorithm, the paper develops an algorithm which can be used to analyze data communication structure and construct design process. At the same time, it can be quickly implemented in the data communication process. The algorithm uses Verilog HDL hardware description language to complete all the design on ISE development platform. And it uses Xilinxs development board Virtex-II Pro to achieve the final realization. Compared with traditional methods, the algorithm is simple and intuitive, which reduces computational the delays and saves space. It

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Zhang, Song, Yi Zhang, Lian Fa Bai, and Wen Jiang Li. "Design on Embedded Processor with Configurable Divider." Applied Mechanics and Materials 336-338 (July 2013): 1504–9. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1504.

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By analyzing Cortex-M3 Instruction Set and AHB Bus protocol, a Cortex-M3 Instruction Set compatible 32-bit RISC embedded microprocessor with built-in an optimized 5+2-stage pipeline was realized in this paper. The performance of the 32-bit RISC processor is optimized by deepening pipeline and optimizing functional modules compared with Cortex-M3. According to division instructions, a configurable hardware divider in different realization ways was realized for different applications. The design of the system architecture was completed using Verilog hardware description language (Verilog HDL) an

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Zhao, Lin Hui, and Zhi Yuan Liu. "Vehicle State and Friction Force Estimation Based on FPGA." Applied Mechanics and Materials 336-338 (July 2013): 999–1002. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.999.

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In order to improve the computational performance of the nonlinear observer for vehicle state and friction force estimation, two novel implementation schemes in Verilog Hardware Description Language (HDL) and System on Programmable Chip (SoPC) is proposed based on Field Programmable Gate Array (FPGA). Firstly, the parallelism analysis of the vehicle state and friction force estimation algorithm is provided. Then, the Verilog HDL and SoPC implementation schemes are presented respectively based on the analysis results. Finally, a testing platform is built to evaluate the functionality and the co

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Mohammad, Sohana Parveen1 Poonam Swami2 &. C.Deepika3. "AN FPGA IMPLEMENTATION OF PARALLEL 2-D MRI IMAGE FILTERING ALGORITHM USING QUARTUS-II." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 5, no. 6 (2018): 258–65. https://doi.org/10.5281/zenodo.1309261.

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In implementing parallel multi-dimensional image filtering algorithms, field programmable gate array (FPGA) provide beyond the low-level line-by-line hardware description language programming. High level abstract hardware-oriented parallel programming method can structurally bridge this gap. Currently, power is a major factor for implementing any algorithm. In this paper, image filtering algorithm is implemented on cyclone-IV FPGA device. By this, lower power consumption of 0.97W down to 0.39W respectively at maximum sampling frequency of up to 230 MHZ .the functional implementation of all pro

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T, Manikyala Rao, Praveen Chakravarthy B. H, Sushma R, and Parameswara Rao G. "Enhanced Optimization of Edge Detection for High Resolution Images Using Verilog Hardware Description Language with Low Power Consumption and Less Hardware Technology." International Journal on Cybernetics & Informatics 5, no. 4 (2016): 363–73. http://dx.doi.org/10.5121/ijci.2016.5439.

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G.W.A.D. "VLSI chip design with the hardware description language verilog An introduction based on a large RISC processor design." Microelectronics Reliability 36, no. 9 (1996): 1316–17. http://dx.doi.org/10.1016/0026-2714(96)82937-4.

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Hwang, Dong Hyun, Chang Yeop Han, Hyun Woo Oh, and Seung Eun Lee. "ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator." Micromachines 12, no. 7 (2021): 838. http://dx.doi.org/10.3390/mi12070838.

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Artificial intelligence algorithms need an external computing device such as a graphics processing unit (GPU) due to computational complexity. For running artificial intelligence algorithms in an embedded device, many studies proposed light-weighted artificial intelligence algorithms and artificial intelligence accelerators. In this paper, we propose the ASimOV framework, which optimizes artificial intelligence algorithms and generates Verilog hardware description language (HDL) code for executing intelligence algorithms in field programmable gate array (FPGA). To verify ASimOV, we explore the

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