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Journal articles on the topic 'VerilogHardware Description Language (HDL)'

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Published: 3 June 2025

Last updated: 31 July 2025

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1

Vidya, Sagar Potharaju*. "FPGA IMPLEMENTATION OF ELLIPTIC CURVE DISCRETE LOGARITHMUSING VERILOG HDL." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 4, no. 11 (2017): 151–62. https://doi.org/10.5281/zenodo.1067986.

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Elliptic Curve Discrete Logarithm (ECDL) are most popular choice Elliptic Curve Cryptography (ECC),which gives provision for shorter key lengths as compared to as compared to its counterpart public key cryptosystems, and it can be used for security in embedded systems,wirless communications and personal communication systems. In this paper Elliptic Curve Discrete Logarithm code has been written in Verilog Hardware Description Language (HDL) and implemented on Xilinx Spartan3E Field Programmable Gate Array (FPGA),has taken 403 encoders, decoders with minimum period of 5.043 ns,maximum frequency

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Antigha, Richard E.E*. "APPLICATION OF AUTO REGRESSIVE INTEGRATED MOVING AVERAGE (ARIMA) IN URBAN STORMWATER DRAINAGE SYSTEMS MODELLING FOR THE CALABAR CATCHMENT, SOUTH-SOUTH, NIGERIA." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 4, no. 11 (2017): 163–74. https://doi.org/10.5281/zenodo.1068882.

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Mathematical analyses were used to develop a stochastic model that predicts the influence of some hydraulic and hydrologic parameters on the perennial flooding of some parts of the Calabar Metropolis.  The model was developed based on rainfall data, cross sectional area of drains, artificial drainage density, degree imperviousness and the gradient (slope). Incorrect sizing and spread of drains as well as the existing slopes employed in the generation of the drains’ invert during construction have been seen as some of the key factors that foster flooding in the Metropolis. Malalignme

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Alves, Nélio Muniz Mendes, and Sérgio Schneider. "Implementation of an Embedded Hardware Description Language Using Haskell." JUCS - Journal of Universal Computer Science 9, no. (8) (2003): 795–812. https://doi.org/10.3217/jucs-009-08-0795.

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This paper describes an ongoing implementation of an embedded hardware description language (HDL) using Haskell as a host language. Traditionally, functional HDL s are made using lazy lists to model signals, so circuits are functions from lists of input values to lists of output values. We use another known approach for embedded languages, in which circuits are data structures rather than functions. This style of implementation permits one to inspect the structure of the circuit, allowing one to perform different interpretations for the same description. The approach we present can also be app

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Neelima, Koppala, and Subhas Chennapalli. "Low overhead optimal parity codes." TELKOMNIKA (Telecommunication, Computing, Electronics and Control) 20, no. 3 (2022): 501–9. https://doi.org/10.12928/telkomnika.v20i3.23301.

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The error detecting and correcting codes are used in critical applications like in intensive care units, defense applications, and require highly reliable data. This brief focuses on codes to detect and correct adjacent errors within a single clock cycle by using modulo-2 addition of data bits for parity generation, syndrome calculation, error location identification and correction by improving code rate and minimizing bit overhead. The optimal parity codes devised can correct odd number of adjacent errors upto (N/2)-1 data bits when compared with the existing codes with less delay. Four optim

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Zhu, Yong. "Study on the Framework of ASIP Executable Specification." Applied Mechanics and Materials 263-266 (December 2012): 1768–72. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.1768.

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The research in accordance with the “description - synthesize” methodology to describe ASIP model is put forward. The executable specification described by the ADL drives the entire design process, and will be synthesized for HDL (Hardware Description Language) logic in EDA software framework to generate automatic design tools.

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BUTKO, Vladyslav, Kostiantyn KASIAN, and KASIAN. "COMPARISON OF COMPILERS FOR GENERATING A HARDWARE DESCRIPTION BASED ON AN IMPERATIVE PROGRAM: HDL CODER AND VITIS HLS." cientific papers of Donetsk National Technical University. Series: Informatics, Cybernetics and Computer Science 2, no. 39 (2024): 49–56. https://doi.org/10.31474/1996-1588-2024-2-39-49-56.

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A mathematical formula was chosen, the hardware implementation of which ensures sufficient the result accuracy of the compilers comparison. Based on it, a graph-scheme of the algorithm (GSA) was composed. According to GSA, programs were created in high-level languages (HLL): Matlab and C++. The HLL programs is not adapted to the generation of descriptions in the hardware description language (HDL) with HLS (high level synthesis) optimizations. To confirm the functional equivalence of the HLL programs, they were tested with the HLL test functions. Based on the Matlab and C++ programs, HDL was g

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Мірошник, Марина Анатоліївна, Юрій Васильович Пахомов, Кирило Юрійович Пшеничний та Андрій Вікторович Шафранський. "Асерційна верифікація моделей пристроїв реального часу з недетермінованими зовнішніми подіями". Інформаційно-керуючі системи на залізничному транспорті 29, № 1 (2024): 37–44. http://dx.doi.org/10.18664/ikszt.v29i1.300988.

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Запропоновано метод верифікації моделей пристроїв реального часу з обробкою зовнішніх подій із недермінованою тривалістю, що описані з використанням мов опису апаратури (Hardware Description Language, HDL). У методології використано апарат асерцій для опису темпоральної природи вищезазначених моделей.

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Ng, L. S., K. Y. Phan, and Patrick W. C. Ho. "Novel logic and memory synthesis algorithm for Memristive Hardware Description Language (HDL)." Integration 96 (May 2024): 102140. http://dx.doi.org/10.1016/j.vlsi.2024.102140.

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K. Sagar Vivek, SK. Farooq Abdulla, S. Pavan, P. Manikanta, and G. Sudheer Kumar. "Development of Mechanized Hardware Description Language Signal Processing For Unmanned Aircraft System Applications." International Journal of Scientific Research in Science and Technology 12, no. 1 (2025): 388–94. https://doi.org/10.32628/ijsrst2512137.

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Future Department of Defense needs include rapid implementation and testing of signal processing algorithms on forward deployed unmanned autonomous hardware systems. Various signal processing algorithms can be designed to test the feasibility of using MATLAB with the hardware description language (HDL) Coder toolbox for rapid implementation and their use in signal processing hardware for real time aerospace and missile applications. This documents the signal processing algorithms and test inputs, MATLAB implementation, and performance and implementation results for generated very high-speed in

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Nhi Ho. T, To, Giao N. Pham, Quang Hung Nguyen, Binh A.Nguyen, Ngoc T. Le, and Hoanh Su Le. "Digital System Design for Traffic Light Controller System: A Systematic Approach." International Journal of Emerging Technology and Advanced Engineering 11, no. 11 (2021): 169–75. http://dx.doi.org/10.46338/ijetae1121_19.

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In this paper, we are going to present the finite state machine, how to implement it via hardware description language (HDL), and how to use it in a real application. At first, the specification and requirements of traffic light controller are stated. Then, the system architecture based on finite state machine (FSM) are conducted. Finally, the way of using HDL as well as the test-bench simulation are given in detail. Keywords : Digital system design, System on chip, Finite State Machine, Digital Design Education, Smart Classroom.

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Brown, A. D. "The Language is Irrelevant: It's What You Do with it That Counts." International Journal of Electrical Engineering & Education 38, no. 4 (2001): 305–15. http://dx.doi.org/10.7227/ijeee.38.4.4.

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This paper presents a brief comment on the role of hardware description languages (HDLs) in the design process, and attempts to look past the semantics of an HDL and identify the semantic constructs that must be supported if a language is to be of practical use. Some brief remarks on the capabilities of state-of-the-art optimisation techniques are also presented.

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Sumathi, M., D. Nirmala, and R. Immanuel Rajkumar. "Study of Data Security Algorithms using Verilog HDL." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 5 (2015): 1092. http://dx.doi.org/10.11591/ijece.v5i5.pp1092-1101.

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This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using Mod

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Shariff, Muneeb Ulla, Vineeth Kumar Veepuri, Nancy Dimri, and Mahadevaswamy B. N. "Mighty Macros and Powerful Parameters: Maximizing Efficiency and Flexibility in HDL Programming." International Journal of VLSI Design & Communication Systems 14, no. 1/2 (2023): 01–18. http://dx.doi.org/10.5121/vlsic.2023.14201.

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This paper explores the use of macros and parameters in Hardware Description Language (HDL) programming. Macros and parameters are powerful tools that allow for efficient and reusable code, yet their full potential is often underutilized. By examining the advantages of macros and parameters, this paper aims to demonstrate how these features can enhance the flexibility, readability, and maintainability of HDL code. Additionally, the paper discusses the use cases of mixing macros and parameters in HDL programming, highlighting their applicability in a range of scenarios. Furthermore, the paper a

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Sayudzi, Mohd Faris Izzwan Mohd, Irni Hamiza Hamzah, Azman Ab Malik, et al. "FPGA in hardware description language based digital clock alarm system with 24-hr format." International Journal of Reconfigurable and Embedded Systems (IJRES) 13, no. 2 (2024): 244. http://dx.doi.org/10.11591/ijres.v13.i2.pp244-252.

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Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 bo

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Bazydło, Grzegorz. "Designing Reconfigurable Cyber-Physical Systems Using Unified Modeling Language." Energies 16, no. 3 (2023): 1273. http://dx.doi.org/10.3390/en16031273.

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Technological progress in recent years in the Cyber-Physical Systems (CPSs) area has given designers unprecedented possibilities and computational power, but as a consequence, the modeled CPSs are becoming increasingly complex, hierarchical, and concurrent. Therefore, new methods of CPSs design (especially using abstract modeling) are needed. The paper presents an approach to the CPS control part modeling using state machine diagrams from Unified Modelling Language (UML). The proposed design method attempts to combine the advantages of graphical notation (intuitiveness, convenience, readabilit

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Purraji, Marziye, Elyas Zamiri, and Angel de Castro. "Easy and Straightforward FPGA Implementation of Model Predictive Control Using HDL Coder." Electronics 14, no. 3 (2025): 419. https://doi.org/10.3390/electronics14030419.

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Model Predictive Control (MPC) is widely adopted for power electronics converters due to its ability to optimize system performance under dynamic constraints. However, its FPGA implementation remains challenging due to the complexity of Hardware Description Language (HDL) programming. This paper addresses this challenge by introducing a straightforward methodology that simplifies FPGA implementation using MATLAB R2022b Simulink HDL Coder. It is shown that HDL Coder yields favorable synthesis outcomes, both in terms of area and time, compared to hand-coded HDL. Notably, the proposed method achi

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Azura Othman, Kama, Nur Ayuni Binti Nor Sobri, Ahmad Haziq Umar, et al. "Intelligent Management System for Home Appliances A conceptual approach using Hardware Description Language." International Journal of Engineering & Technology 7, no. 3.7 (2018): 76. http://dx.doi.org/10.14419/ijet.v7i3.7.16216.

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IoT (Internet of Things) is an emerging trend in the market and smart appliances are a subset of IoT. The IoT helps integrate digital and wireless technologies in home or kitchen appliances. Furthermore, M2M (Machine to Machine) communication is likely to create a key opportunity in the smart appliances market. Smart appliances are the next generation of home appliances that have the ability to receive, interpret, and act on a signal received from a user. This paper is a demonstration of designing a multipurpose remotely controlled system for electrical household appliances. The project simula

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Zhao, Lin Hui, and Zhi Yuan Liu. "Vehicle State and Friction Force Estimation Based on FPGA." Applied Mechanics and Materials 336-338 (July 2013): 999–1002. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.999.

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In order to improve the computational performance of the nonlinear observer for vehicle state and friction force estimation, two novel implementation schemes in Verilog Hardware Description Language (HDL) and System on Programmable Chip (SoPC) is proposed based on Field Programmable Gate Array (FPGA). Firstly, the parallelism analysis of the vehicle state and friction force estimation algorithm is provided. Then, the Verilog HDL and SoPC implementation schemes are presented respectively based on the analysis results. Finally, a testing platform is built to evaluate the functionality and the co

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Huang, Xiang Sheng. "Design of AD Controller Customized IP Core Based on FPGA." Applied Mechanics and Materials 727-728 (January 2015): 859–62. http://dx.doi.org/10.4028/www.scientific.net/amm.727-728.859.

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This design elaborates thedevelopment process of the custom IP core AD9280 controller based on FPGA. Thedesign uses FPGA as the core of the microcontroller, realizes the function ofAD controller by adopting the hardware description language,Verilog HDL and encapsulates it to the custom IP core in the SOPCBuilder. In the NIOS II, the application program interface (API) function ofthe AD controller software is used to access and control the hardware, thesoftware is written by using C language. The experimental results show thatthis custom IP core is feasible and flexible, fully reflects the adva

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Zhang, Ming, Hao Ting Liu, and Yu Wang. "The Design of the Multifunctional Electronic Timing System Based on the Verilog HDL Language." Applied Mechanics and Materials 182-183 (June 2012): 763–67. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.763.

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Verilog is the most widely used hardware description language. It can be used in the modeling, synthesis, and simulation stages of the hardware system designing. This thesis is about applying Verilog HDL to design the multifunctional electronic timing system. This system has brought about the timing function, the Alarm clock function, the time checking module, the stop clock module, the exact hour alarming module, the alarm clock’s shielding and alarming function module and the stop clock Prompting function module. The modules which have applied this design can be transplanted to other kinds o

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Miriampally, Venkata Raghavendra. "Simulation of PCI Express™ Transaction Layer Using Hardware Description Language." International Journal of Informatics and Communication Technology (IJ-ICT) 4, no. 1 (2015): 7. http://dx.doi.org/10.11591/ijict.v4i1.pp7-12.

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<p>PCI Express is a high-speed serial connection that operates more like a network than a bus.<strong> </strong>PCI Express will serve as a general purpose I/O interconnects for a wide variety of future computing and communications platforms.<strong> </strong>PCI Express (PCIe) is implemented with a split-transaction protocol that provides more bandwidth and is compatible with existing operating systems. PCI Express has three discrete logical layers: the Transaction Layer, the Data Link Layer, and the Physical Layer. This paper analyze and simulates the function o

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Narendran, S., and J. Selvakumar. "Digital Simulation of Superconductive Memory System Based on Hardware Description Language Modeling." Advances in Condensed Matter Physics 2018 (May 27, 2018): 1–5. http://dx.doi.org/10.1155/2018/2683723.

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We have modeled a memory system using Josephson Junction to attain low power consumption using low input voltage compared to conventional Complementary Metal Oxide Semiconductor-Static Random Access Memory (CMOS-SRAM). We attained the low power by connecting a shared/common bit line and using a 1-bit memory cell. Through our design we may attain 2.5–3.5 microwatts of power using lower input voltage of 0.6 millivolts. Comparative study has been made to find which memory system will attain low power consumption. Conventional SRAM techniques consume power in the range of milliwatts with the suppl

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Saralegui, Roberto, Alberto Sanchez, and Angel de Castro. "Efficient Hardware-in-the-Loop Models Using Automatic Code Generation with MATLAB/Simulink." Electronics 12, no. 13 (2023): 2786. http://dx.doi.org/10.3390/electronics12132786.

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Hardware-in-the-loop testing is usually a part of the design cycle of control systems. Efficient and fast models can be created in a Hardware Description Language (HDL), which is implemented in a Field-Programmable Gate Array (FPGA). Control engineers are more skilled in higher-level approaches. HDL models derived automatically from schematics have noticeably lower performance, while HDL models derived from their equations are faster and smaller. However, even models translated automatically into HDL using the equations might be worse than manually coded models. A design workflow is proposed t

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Hwang, Dong Hyun, Chang Yeop Han, Hyun Woo Oh, and Seung Eun Lee. "ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator." Micromachines 12, no. 7 (2021): 838. http://dx.doi.org/10.3390/mi12070838.

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Artificial intelligence algorithms need an external computing device such as a graphics processing unit (GPU) due to computational complexity. For running artificial intelligence algorithms in an embedded device, many studies proposed light-weighted artificial intelligence algorithms and artificial intelligence accelerators. In this paper, we propose the ASimOV framework, which optimizes artificial intelligence algorithms and generates Verilog hardware description language (HDL) code for executing intelligence algorithms in field programmable gate array (FPGA). To verify ASimOV, we explore the

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Memon, Farida, Aamir Hussain Memon, Shahnawaz Talpur, Fayaz Ahmed Memon, and Rafia Naz Memon. "Design and Co-Simulation of Depth Estimation Using Simulink HDL Coder and Modelsim." July 2016 35, no. 3 (2016): 473–82. http://dx.doi.org/10.22581/muet1982.1603.17.

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In this paper a novel VHDL design procedure of depth estimation algorithm using HDL (Hardware Description Language) Coder is presented. A framework is developed that takes depth estimation algorithm described in MATLAB as input and generates VHDL code, which dramatically decreases the time required to implement an application on FPGAs (Field Programmable Gate Arrays). In the first phase, design is carriedout in MATLAB. Using HDL Coder, MATLAB floating- point design is converted to an efficient fixed-point design and generated VHDL Code and test-bench from fixed point MATLAB code. Further, the

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Tsoeunyane, Lekhobola, Simon Winberg, and Michael Inggs. "Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language." International Journal of Reconfigurable Computing 2017 (2017): 1–28. http://dx.doi.org/10.1155/2017/3925961.

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This paper reports on the design and implementation of an open-source library of parameterizable and reusable Hardware Description Language (HDL) Intellectual Property (IP) cores designed for the development of Software-Defined Radio (SDR) applications that are deployed on FPGA-based reconfigurable computing platforms. The library comprises a set of cores that were chosen, together with their parameters and interfacing schemas, based on recommendations from industry and academic SDR experts. The operation of the SDR cores is first validated and then benchmarked against two other cores librarie

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Zheng, Hua Qiang, Li Fu Ma, Yang Liu, and Fei Cai. "Real-Time Video Convert System Design Based on LVDS." Advanced Materials Research 159 (December 2010): 514–21. http://dx.doi.org/10.4028/www.scientific.net/amr.159.514.

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In this paper, we designed a real-time video convert system for the imaging devices which used digital precision progressive scan monochrome camera or the similar camera and as video signal sensor. System hardware circuit design based on LVDS transmission chip, multiformat video decoder chip: ADV718X and the Cyclone II series FPGA. System software design based on hardware description language, verilog HDL and VHDL. The system could real-time capture, process CVBS and output LVDS video data without the system computer.

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Prathap, Joseph Anthony, Mrinal Raj, and Ritu Patnaik. "Design of decryption process for advanced encryption standard algorithm in system-on-chip." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 6 (2024): 6838. http://dx.doi.org/10.11591/ijece.v14i6.pp6838-6845.

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This paper concentrates on the development of system-on-chip for the decryption algorithm in the advanced encryption standard (AES). This method includes the transformation of cipher text into plain text and consists of 4 sub-tasks based on the resolution. In this work, the 128-bit resolution is utilized to perform 10 rounds of transformation with the round key added at every round generated by the key expansion algorithm. Though there are many cryptography algorithms, the AES is simple, secure, faster in operation, and easy to develop compared to the others. The system-on-chip (SOC) design fo

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Miroshnyk, M. A., S. I. Shmatkov, O. S. Shkil, А. М. Miroshnyk, and K. Y. Pshenychnyi. "TEMPORAL EVENTS PROCESSING MODELS IN FINITE STATE MACHINES." Radio Electronics, Computer Science, Control, no. 4 (December 23, 2023): 49. http://dx.doi.org/10.15588/1607-3274-2023-4-5.

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Context. The issue of a synthesizable finite state machine with temporal events processing using hardware description language pattern. The object of this study is external event processing in real-time systems. Objective. The goal of this work is to introduce methods to express external temporal events on finite state machine state diagrams and corresponding HDL patterns of such events processing in control systems. Method. The classification of external events in real-time systems is analyzed. A device class that changes its internal state depending on the temporal external event

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Gao, Li, Runmei Zhang, and Guangbin Zhang. "Development of Intelligent Building Energy-saving Temperature Control System Based on FPGA." E3S Web of Conferences 136 (2019): 02033. http://dx.doi.org/10.1051/e3sconf/201913602033.

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The ideal energy-saving building should meet the environmental quality of living space in different seasons with the least energy consumption. The indoor temperature of the building is an important consideration. However, most temperature control systems have certain problems. In order to improve the stability and accuracy of the temperature control system, a system based on FPGA+Verilog HDL for intelligent adjustment of indoor temperature is designed. The purpose of the system design is to achieve the dual effect of comfortable and energy-saving living environment. The system uses an integrat

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Sisco, Zachary D., Jonathan Balkind, Timothy Sherwood, and Ben Hardekopf. "Loop Rerolling for Hardware Decompilation." Proceedings of the ACM on Programming Languages 7, PLDI (2023): 420–42. http://dx.doi.org/10.1145/3591237.

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We introduce the new problem of hardware decompilation . Analogous to software decompilation, hardware decompilation is about analyzing a low-level artifact—in this case a netlist , i.e., a graph of wires and logical gates representing a digital circuit—in order to recover higher-level programming abstractions, and using those abstractions to generate code written in a hardware description language (HDL). The overall problem of hardware decompilation requires a number of pieces. In this paper we focus on one specific piece of the puzzle: a technique we call hardware loop rerolling . Hardware l

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Zhou, Qing Fang, Qian Huang, Ying Yuan, and Jun Yang. "Design and Implementation of Reconfigurable Encryption and Decryption System Based on SOPC." Applied Mechanics and Materials 347-350 (August 2013): 2979–82. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.2979.

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The system is based on DES/3DES, AES cipher algorithm as the research object.According to the characteristics of the algorithm, designs a configuration mode which can share resource in space and configurate algorithm in time. Then it uses hardware description language Verilog HDL to realize and optimize the design, and completes a custom reconfigurable DES/3DES/AES encryption/decryption IP core. By SOPC technology, the IP core, Nios II processor, network controller and other function. The design hardware structureis simple, flexibility, security, which can be widely used in the field of inform

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Wang, Lie, and Yi Jie Wang. "Implementation of CRC by Using FPGA in Data Communication." Applied Mechanics and Materials 325-326 (June 2013): 1805–8. http://dx.doi.org/10.4028/www.scientific.net/amm.325-326.1805.

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By introducing the basic principle of ordinary CRC algorithm, the paper develops an algorithm which can be used to analyze data communication structure and construct design process. At the same time, it can be quickly implemented in the data communication process. The algorithm uses Verilog HDL hardware description language to complete all the design on ISE development platform. And it uses Xilinxs development board Virtex-II Pro to achieve the final realization. Compared with traditional methods, the algorithm is simple and intuitive, which reduces computational the delays and saves space. It

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Jin, Lin, and Qiang Liu. "Study on Mechanical and Electrical Automation with System Design of Frequency Meter Based on EDA Technology." Applied Mechanics and Materials 387 (August 2013): 356–59. http://dx.doi.org/10.4028/www.scientific.net/amm.387.356.

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Frequency meter as a kind of electronic measuring instruments, have been widely applied in the field of Mechanical and Electrical automation. The design of a frequency meter based on EDA technology, is implemented in EDA software platform of Quartus II, using hardware description language (HDL) editor can also be seasonal schematic, design, system hardware circuit compiler, simulation, system is divided into five modules: frequency module, control module, counting module, range switching module and display module, the hardware design requires a download chip EPM7128S and input and output circu

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Cui, Xiaofang. "Research and Application of FPGA Function Verification Methods." Academic Journal of Science and Technology 9, no. 1 (2024): 30–32. http://dx.doi.org/10.54097/txyvq493.

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FPGA functional verification methods include simulation and timing simulation. Simulation and testing of digital circuits through mathematical models before physical implementation can help reduce development risks. Time series simulation focuses on evaluating the time behavior of FPGA design to ensure that the signal meets the timing requirements. Hardware Description Language (HDL) plays a crucial role in FPGA design, supporting design reuse and improving efficiency. The application areas include communication systems, image processing, automotive electronics, and industrial control systems.

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Ciangottini, Diego, Giulio Bianchini, Mirko Mariotti, Daniele Spiga, Loriano Storchi, and Giacomo Surace. "KServe inference extension for an FPGA vendor-free ecosystem." EPJ Web of Conferences 295 (2024): 11012. http://dx.doi.org/10.1051/epjconf/202429511012.

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Field Programmable Gate Arrays (FPGAs) are playing an increasingly important role in the sampling and data processing industry due to their intrinsically highly parallel architecture, low power consumption, and flexibility to execute custom algorithms. In particular, the use of FPGAs to perform Machine Learning (ML) inference is increasingly growing thanks to the development of High-Level Synthesis (HLS) projects that abstract the complexity of Hardware Description Language (HDL) programming. In this work we will describe our experience extending KServe predictors, an emerging standard for ML

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Rodriguez Pinto, Father Alexander, Felipe Restrepo-Calle, and Jhon Jairo Ramírez-Echeverry. "Evaluation of the effects of a hybrid laboratory for learning a hardware description language: Insights into student motivation and academic performance." Research and Practice in Technology Enhanced Learning 21 (May 8, 2025): 010. https://doi.org/10.58459/rptel.2026.21010.

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This research paper presents a study that investigates the effects of hybrid laboratories on learning Hardware Description Language (HDL) in digital electronics, focusing on student motivation and academic performance. With the advancement of telecommunications and computer applications in education, initiatives such as hybrid laboratories, which combine remote and on-site learning environments, have emerged. Despite this, the literature shows a lack of empirical evidence on the effect of these initiatives on students’ learning process in digital electronics. To address this gap, this study im

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Reddy, Bharathi, D. Leela Rani, and Prof S. Varadarajan. "HIGH SPEED CARRY SAVE MULTIPLIER BASED LINEAR CONVOLUTION USING VEDIC MATHAMATICS." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 4, no. 2 (2013): 284–87. http://dx.doi.org/10.24297/ijct.v4i2a2.3173.

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VLSI applications include Digital Signal Processing, Digital control systems, Telecommunications, Speech and Audio processing for audiology and speech language pathology. The latest research in VLSI is the design and implementation of DSP systems which are essential for above applications. The fundamental computation in DSP Systems is convolution. Convolution and LTI systems are the heart and soul of DSP. The behavior of LTI systems in continuous time is described by Convolution integral whereas the behavior in discrete-time is described by Linear convolution. In this paper, Linear convolution

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Rifqie, Dary Mochamad, Yasser Abd Djawad, Faizal Arya Samman, Ansari Saleh Ahmar, and M. Miftach Fakhri. "Design of Quantized Deep Neural Network Hardware Inference Accelerator Using Systolic Architecture." Journal of Applied Science, Engineering, Technology, and Education 6, no. 1 (2024): 27–33. https://doi.org/10.35877/454ri.asci2689.

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This paper presents a hardware inference accelerator architecture of quantized deep neural networks (DNN). The proposed accelerator implements all computation in a quantize version of DNN including linear transformations like matrix multiplications, nonlinear activation functions such as ReLU, quantization and dequantization operation. The hardware accelerator of quantized DNN consists of matrix multiplication core which is implemented in systolic array architecture, and the QDR core for computing the operation of quantization, dequantization, and ReLU. This proposed hardware architecture is i

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Ohkawa, Takeshi, Daichi Uetake, Takashi Yokota, and Kanemitsu Ootsu. "Component-Based FPGA Circuit Design and Verification for Robotic Systems Using JavaRock and ORB Engine - A Case Study." Applied Mechanics and Materials 433-435 (October 2013): 1849–52. http://dx.doi.org/10.4028/www.scientific.net/amm.433-435.1849.

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In order to improve flexibility and productivity of designing complex robot systems which consists of a number of sensors, actuators and processors for control, component-based design methodology is a key issue. Meanwhile, an FPGA (Field Programmable Gate Array) is a potential candidate for controlling real-time system like a robot, because it can achieve shorter response time and higher performance-power efficiency by its parallel processing of hardwired digital circuits. However, it is difficult to introduce an FPGA for robot systems because designing an FPGA requires implementation of the u

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Ibrahimy, Muhammad Ibn. "FPGA Implementation of Multiplier for Floating-Point Numbers Based on IEEE 754-2008 Standard." Journal of Communications Technology, Electronics and Computer Science 1 (October 22, 2015): 1. http://dx.doi.org/10.22385/jctecs.v1i0.2.

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This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis etc. Implementation of floating-point multiplication is handy and easy for high level language. However it is a challenging task to implement a floating-point multiplication in hardware level/low level language due to the complexity of algorithm. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floati

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Mohammad, Sohana Parveen1 Poonam Swami2 &. C.Deepika3. "AN FPGA IMPLEMENTATION OF PARALLEL 2-D MRI IMAGE FILTERING ALGORITHM USING QUARTUS-II." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 5, no. 6 (2018): 258–65. https://doi.org/10.5281/zenodo.1309261.

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In implementing parallel multi-dimensional image filtering algorithms, field programmable gate array (FPGA) provide beyond the low-level line-by-line hardware description language programming. High level abstract hardware-oriented parallel programming method can structurally bridge this gap. Currently, power is a major factor for implementing any algorithm. In this paper, image filtering algorithm is implemented on cyclone-IV FPGA device. By this, lower power consumption of 0.97W down to 0.39W respectively at maximum sampling frequency of up to 230 MHZ .the functional implementation of all pro

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Baghdadi, Mohamed, Elmostafa Elwarraki, and Imane Ait Ayad. "FPGA-Based Hardware-in-the-Loop (HIL) Emulation of Power Electronics Circuit Using Device-Level Behavioral Modeling." Designs 7, no. 5 (2023): 115. http://dx.doi.org/10.3390/designs7050115.

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Accurate models of power electronic converters can greatly enhance the accuracy of hardware-in-the-loop (HIL) simulators. This can result in faster and more cost-effective design cycles in industrial applications. This paper presents a detailed hardware model of the IGBT and power diode at the device level suggested for emulating power electronic converters on a field programmable gate array (FPGA). The static visualization of the IGBT component involves an arrangement of equivalent models for both the MOSFET and bipolar transistor in a cascading configuration. The dynamic aspect is represente

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M.K.Safie. "Digital System Identification Controller for Adaptive Feedback Control in Closed-Loop FES." Journal of Information Systems Engineering and Management 10, no. 28s (2025): 86–99. https://doi.org/10.52783/jisem.v10i28s.4295.

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Functional Electrical Stimulation (FES) devices are widely used for spinal cord injury patients but often face challenges with nonlinearity effects, leading to premature muscle fatigue due to feedback controller discrepancies. Therefore, this research proposes a digital system identification controller (SIC) to determine the patient's condition by extracting important information from the patient’s knee trajectory response, which includes time delay, rise time, overshoot, steady-state time, steady-state value, and steady-state error. The extracted information is beneficial in enabling real-tim

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Marcus, Lloyde George, and Joseph Brandon. "Development of a control path VHDL code generator for hardware development." i-manager’s Journal on Software Engineering 16, no. 3 (2022): 16. http://dx.doi.org/10.26634/jse.16.3.18660.

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The Very High-Speed Integration Circuit HDL (VHDL) is widely used to implement digital electronic systems. The VHDL language can be difficult to learn, so it is necessary to simplify and speed up the process of implementing digital electronic components through a hardware description with a minimal understanding of the VHDL language. This paper entails the design and development of a Graphical User Interface (GUI) capable of generating VHDL code for ControlPaths using specified state transition tables and state diagrams. This application was created using the Matrix Laboratory (MATLAB). Applic

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Baungarten-Leon, Emilio Isaac, Susana Ortega-Cisneros, Mohamed Abdelmoneum, Ruth Yadira Vidana Morales, and German Pinedo-Diaz. "The Genesis of AI by AI Integrated Circuit: Where AI Creates AI." Electronics 13, no. 9 (2024): 1704. http://dx.doi.org/10.3390/electronics13091704.

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The typical Integrated Circuit (IC) development process commences with formulating specifications in natural language and subsequently proceeds to Register Transfer Level (RTL) implementation. RTL code is traditionally generated through manual efforts, using Hardware Description Languages (HDL) such as VHDL or Verilog. High-Level Synthesis (HLS), on the other hand, converts programming languages to HDL; these methods aim to streamline the engineering process, minimizing human effort and errors. Currently, Electronic Design Automation (EDA) algorithms have been improved with the use of AI, with

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Kumar, Dasari Mahesh. "Single Bit Alu Using Reversible Logic Gates." INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 06 (2025): 1–9. https://doi.org/10.55041/ijsrem49514.

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Abstract— In this digital world, technology depends on the operations of A.L.U to decide the system performance. The need for an Arithmetic Logic Unit (ALU) is as important as the computer, simply because ALU forms the fundamental part of any Central Processing Unit (CPU). And so the encryption of an ALU is highly mandatory for the safety of the device as there are hardly any device without an ALU. This paper deals with the design of an single-bit ALU using a hardware description language, HDL that is structurally modelled. The results are verified and synthesized through Xilinx. Keywords- ALU

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Wei Chun, Quek, Pang Wai Leong, Chan Kah Yoong, Lee It Ee, and Chung Gwo Chin. "HDL Modelling of Low-CostMemory Fault Detection Tester." Journal of Engineering Technology and Applied Physics 2, no. 2 (2020): 17–23. http://dx.doi.org/10.33093/jetap.2020.2.2.3.

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Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE)to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly(at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has in spired us to desi

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Wang, Xin, and Jari Nurmi. "Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network." VLSI Design 2007 (April 5, 2007): 1–14. http://dx.doi.org/10.1155/2007/18372.

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Two network-on-chip (NoC) designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA) connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS) scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, data transfer principles, network node structures, and their asynchronous designs. Both the synchronous

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Majeed, Bilal, Rajkumar Sarma, Ayman Youssef, Douglas Mota Dias, and Conor Ryan. "Automatic Generation of Synthesisable Hardware Description Language Code of Multi-Sequence Detector Using Grammatical Evolution." Algorithms 18, no. 6 (2025): 345. https://doi.org/10.3390/a18060345.

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Quickly designing digital circuits that are both correct and efficient poses significant challenges. Electronics, especially those incorporating sequential logic circuits, are complex to design and test. While Electronic Design Automation (EDA) tools aid designers, they do not fully automate the creation of synthesisable circuits that can be directly translated into hardware. This paper introduces a system that employs Grammatical Evolution (GE) to automatically generate synthesisable Hardware Description Language (HDL) code for the Finite State Machine (FSM) of a Multi-Sequence Detector (MSD)

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