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Relevant bibliographies by topics / Very Large Scale Integrated Circuit (VLSI)

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Academic literature on the topic 'Very Large Scale Integrated Circuit (VLSI)'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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Journal articles on the topic "Very Large Scale Integrated Circuit (VLSI)"

1

Madhura, S. "A Review on Low Power VLSI Design Models in Various Circuits." Journal of Electronics and Informatics 4, no. 2 (2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.

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Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the pe

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M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M, and Rahul S.G. "Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits." ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.

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High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal

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Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.

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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits bec

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CHEN, JIANLI, and WENXING ZHU. "A PLACEMENT FLOW FOR VERY LARGE-SCALE MIXED-SIZE CIRCUIT PLACEMENT." Journal of Circuits, Systems and Computers 23, no. 02 (2014): 1450016. http://dx.doi.org/10.1142/s0218126614500169.

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The very large-scale integrated circuit (VLSI) placement problem is to determine the exact location of each movable circuit element within a given region. It is a crucial process in physical design, since it affects performance, power consumption, routability, and heat distribution of a design. In this paper, we propose a VLSI placement flow to handle the large-scale mixed-size placement problem. The main idea of our placement flow is using a floorplanning algorithm to guide the placement of circuit elements. It consists of four steps: (1) With the multilevel framework, circuit elements are cl

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Wong, C. P. "An Overview of Integrated Circuit Device Encapsulants." Journal of Electronic Packaging 111, no. 2 (1989): 97–107. http://dx.doi.org/10.1115/1.3226528.

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The rapid development of integrated circuit technology from small-scale integration (SSI) to very large scale integration (VLSI) has had great technological and economical impact on the electronics industry. The exponential growth of the number of components per IC chip, the exponential decrease of device dimensions, and the steady increase in IC chip size have imposed stringent requirements, not only on the IC physical design and fabrication, but also on IC encapsulants. This report addresses the purpose of encapsulation, encapsulation techniques, and a general overview of the application of

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MOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (2021): 505–11. http://dx.doi.org/10.6036/10214.

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Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit

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Maskowitz, J. V., W. E. Rhoden, D. R. Kitchen, R. E. Omlor, and P. F. Lloyd. "In situ STEM observations of electromigration on thin aluminum stripes." Proceedings, annual meeting, Electron Microscopy Society of America 44 (August 1986): 740–41. http://dx.doi.org/10.1017/s0424820100145078.

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The existence of electromigration in thin films has been acknowledged since the early sixties. Electromigration is described as the main transport for atoms in a conductor under a current stress. Initial interest had been of a theoretical nature as electromigration had little impact on circuit reliability. With the maturing of Very Large Scale Integrated Circuit (VLSI) technology, current densities are exceeding 106 Amps/cm2 while linestripes are reaching into the submicron range. In this environment, electromigration can cause unwanted open or short circuits in thin films. This has serious im

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Katircioglu, Haluk, JohnA De Beule, Debaditya Mukherjee, and GaryC Whitlock. "4932028 Error log system for self-testing in very large scale integrated circuit (VLSI) units." Microelectronics Reliability 31, no. 2-3 (1991): viii. http://dx.doi.org/10.1016/0026-2714(91)90267-b.

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Zhang, Ai Rong. "The Integration on Electrical Control Systems Based on Optimized Method." Advanced Materials Research 490-495 (March 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.

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Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity a

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Rajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics." Journal of Circuits, Systems and Computers 27, no. 13 (2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.

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Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write

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Dissertations / Theses on the topic "Very Large Scale Integrated Circuit (VLSI)"

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Liu, Yansong. "Passivity checking and enforcement in VLSI model reduction exercise." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290690.

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Voo, Thart Fah. "Tunable techniques for robust high frequency analogue VLSI." Thesis, Imperial College London, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.369050.

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Voranantakul, Suwan 1962. "CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/277037.

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Liu, Yansong, and 劉岩松. "Passivity checking and enforcement in VLSI model reduction exercise." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B41290690.

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Matsumori, Barry Alan. "QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275313.

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Cooke, Bradly James. "S-parameter VLSI transmission line analysis." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184876.

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This dissertation investigates the implementation of S-parameter based network techniques for the analysis of multiconductor, high speed VLSI integrated circuit and packaging interconnects. The S-parameters can be derived from three categories of input parameters: (1) lossy quasi-static R,L,C and G, (2) lossy frequency dependent (dispersive) R,L,C,G and (3) the propagation constants, Γ, the characteristic impedance, Z(c) and the conductor eigencurrents, I, derived from full wave analysis. The S-parameter network techniques developed allow for: the analysis of periodic waveform excitation, the

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Jafar, Mutaz 1960. "THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276959.

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Buchanan, Brent E. "A mixed-signal CMOS VLSI image convolution circuit using error spectrum shaping." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15420.

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Chabbi, Charef. "VLSI NMOS hardware design of a linear phase FIR low pass digital filter." Ohio University / OhioLINK, 1985. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183749814.

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高雲龍 and Wan-lung Ko. "A new optimization model for VLSI placement." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B29812938.

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Books on the topic "Very Large Scale Integrated Circuit (VLSI)"

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Litovski, V. VLSI circuit simulation and optimization. Chapman & Hall, 1997.

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Bhattacharya, Debashis. Hierarchical modeling for VLSI circuit testing. Kluwer Academic Publishers, 1990.

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1962-, Sharaf Khaled M., and Elmasry Mohamed I. 1943-, eds. High-performance digital VLSI circuit design. Kluwer Academic Publishers, 1996.

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Xiu, Liming. VLSI Circuit Design Methodology Demystified. John Wiley & Sons, Ltd., 2007.

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5

VLSI analog signal processing circuits: Algorithm, architecture, modeling, and circuit implementation. Xlibris Corp, 2009.

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6

VLSI engineering. Prentice-Hall International, 1988.

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Dillinger, Thomas E. VLSI engineering. Prentice-Hall, 1988.

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8

1936-, Chen Wai-Kai, ed. The VLSI handbook. 2nd ed. CRC/Taylor & Francis, 2007.

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1936-, Chen Wai-Kai, ed. The VLSI handbook. CRC Press, 1999.

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D, Tan Sheldon X., and Cheng Chung-Kuan, eds. Symbolic analysis and reduction of VLSI circuits. Springer, 2005.

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Book chapters on the topic "Very Large Scale Integrated Circuit (VLSI)"

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Weik, Martin H. "very-large-scale integrated circuit." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_20746.

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Golanbari, Mohammad Saber, Mojtaba Ebrahimi, Saman Kiamehr, and Mehdi B. Tahoori. "Selective Flip-Flop Optimization for Circuit Reliability." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_14.

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AbstractThis chapter proposes a selective flip-flop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flip-flop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are improved by optimizing the timing-critical components under severe impact of runtime variations. As flip-flops are vulnerable to aging and supply voltage fluctuation, it is necessary to address these reliability issues in order to improve the overall system lifetime. In the proposed method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe Bias Temperature Instability (BTI) impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop critical flip-flops of the circuit with optimized versions to improve the timing and reliability of the entire circuit in a cost-effective way. Simulation results show that incorporating the optimized flip-flops in a processor can prolong the circuit lifetime by 36.9%, which translates into better reliability.This chapter is organized as follows. Section 1 introduces wide-voltage operation reliability issues and motivates the proposed selective flip-flop optimization approach. The impacts of runtime variations on flip-flops are explained in Sect. 2. Consequently, Sect. 3 presents cell-level optimization of the flip-flops. The proposed selective flip-flop optimization methodology is described in Sect. 4, and optimization results are discussed in Sect. 5. Finally, Sect. 7 concludes the chapter.

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Gebregiorgis, Anteneh, Rajendra Bishnoi, and Mehdi B. Tahoori. "Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) Caches." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_13.

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AbstractNear-threshold computing (NTC) has significant role in reducing the energy consumption of modern very large-scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This chapter presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near-threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this chapter, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture-level analysis.

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MOHSEN, AMR, SAI WAI FU, and CARL SIMONSEN. "Fundamental Principles of Very Large Scale Integrated Circuit Design." In Vlsi Handbook. Elsevier, 1985. http://dx.doi.org/10.1016/b978-0-12-234100-7.50008-3.

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Kiran B., Raghu N., and Manjunatha K. N. "VLSI Implementation of a High-Speed Pipeline A/D Converter." In Role of 6G Wireless Networks in AI and Blockchain-Based Applications. IGI Global, 2023. http://dx.doi.org/10.4018/978-1-6684-5376-6.ch005.

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In very large-scale-integrated (VLSI) design, a challenge is to increase the speed without compromising the power consumption in an analog and mixed mode signal circuit. This research work is carried out to design a 12-bit pipeline A/D converter (ADC) of 400MS/s sampling rate to meet the high computing requirements. The design is focused to determine high speed and resolution in pipeline ADC to cater different applications. The main advantages of pipeline method are simple to implement, more flexible to improve the speed, and makes layout design simple. A proposed technique holds sample and hold circuit (S/H), multiplying DAC, comparator, and operational transconductance amplifier (OTA) to design the pipeline ADC architecture. OTA is used to convert differential input voltage into current with the help of a switched capacitor integrator module.

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Capmany, José, and Daniel Pérez. "Practical Implementation of Programmable Photonic Circuits." In Programmable Integrated Photonics. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198844402.003.0006.

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In covering the fundamentals and ideal implementation of integrated multi-port interferometers and waveguide meshes, we saw that solutions with larger integration density of programmable unit cells enables the synthesis of more complex circuits. However, photonic integrated circuits (PICs) generally suffer from design and fabrication errors and other non-ideal working conditions, which compromises performance and scalability. In addition, PICs require the development of two additional tiers (electronic hardware and software) to allow their programmability, optimisation and (re)configuration. This chapter introduces basic practical considerations of programmable PIC design and reviews experimental demonstrations of both multi-port interferometers and waveguide mesh arrangements. It analyses the main error sources and their impact on circuit performance and investigates the most challenging evolution obstacles for very large-scale programmable PICs. It introduces an analytical method for arbitrary waveguide mesh analysis. Finally, it presents a general architecture for the control subsystem and introduces the software framework and main algorithms.

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Dardano, Principia, Mario Battisti, Selene De Martino, et al. "Theranostic Microneedle Devices: Innovative Biosensing and Transdermal Drugs Administration." In Biosensor - Current and Novel Strategies for Biosensing [Working Title]. IntechOpen, 2020. http://dx.doi.org/10.5772/intechopen.95050.

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Biosensing systems based on microneedles can overcome the stratum corneum of the skin, i. e. the outer natural barrier of the human body, without any pain and detect the target analytes directly in the interstitial fluid. Moreover, microneedle-based devices (MNDs) can combine diagnostic sensing and therapeutic administration of drugs in one single tool. From this point of view, more than a painless door to the human body, a MND represents the a perfect example of theranostic instrument, since a single device could quantify the real value of a relevant biomolecule, such as glucose, and accurately deliver a drug, the insulin, if needed. MNDs could be integrated on printed circuit boards, flexible electronics and microfluidic channels, thus allowing a continuous monitoring of the physiological parameters with very low invasiveness, together with sustained and localized administration of drugs. MNDs can be designed for very specific applications, from the detection of skin cancer to the monitoring of metabolic pathways. Moreover, several fabrication approaches have been introduced, from laboratories to large-scale production. Finally MNDs can be properly functionalized to enhance analytical performances.

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Conference papers on the topic "Very Large Scale Integrated Circuit (VLSI)"

1

Clymer, B. D., and J. W. Goodman. "Detection of optically distributed clock signals for very large scale integrated circuits." In OSA Annual Meeting. Optica Publishing Group, 1985. http://dx.doi.org/10.1364/oam.1985.tue1.

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The miniaturization of integrated circuit elements by scaling in very large scale integrated circuits (VLSI) has created a great deal of interest in the timing skew associated with transmitting signals via circuit lines to remote locations on a chip. As device sizes decrease and chip sizes increase with technological advances, the speed of the circuits on a VLSI chip becomes limited by signal transmission delays rather than device switching delays. Of particular interest is the clock signal that allows the system operations to be timed synchronously with one another. Parasitic transmission lin

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Michailidis, Anastasios, Thomas Noulis, and Kostas Siozios. "Linear and Periodic State Integrated Circuits Noise Simulation Benchmarking." In 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2022. http://dx.doi.org/10.1109/vlsi-soc54400.2022.9939575.

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Gunti, Nagendra Babu, Aman Khatri, and Karthikeyan Lingasubramanian. "Realizing a security aware triple modular redundancy scheme for robust integrated circuits." In 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-soc.2014.7004183.

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Chusseau, Laurent, Rachid Omarouayache, Jeremy Raoult, et al. "Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI)." In 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-soc.2014.7004189.

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Xiang, Dong, Gang Liu, Krishnendu Chakrabarty, and Hideo Fujiwara. "Thermal-aware test scheduling for NOC-based 3D integrated circuits." In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2013. http://dx.doi.org/10.1109/vlsi-soc.2013.6673257.

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Brik, Adil, Lioua Labrak, Laurent Carrel, Ian O'Connor, and Ramy Iskander. "Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts." In 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2019. http://dx.doi.org/10.1109/vlsi-soc.2019.8920305.

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Livramento, Vinícius Dos Santos, and José Luís Güntzel. "Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits." In XXX Concurso de Teses e Dissertações da SBC. Sociedade Brasileira de Computação - SBC, 2017. http://dx.doi.org/10.5753/ctd.2017.3465.

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The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit

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Hartman, Nile F., Timothy J. Drabik, Thomas K. Gaylord, and Mark A. Handschy. "Optical characterization of ferroelectric liquid-crystal/silicon VLSI spatial light modulator." In OSA Annual Meeting. Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.fv1.

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Two-dimensional spatial light modulators (SLMs) are critically important in optical computing systems. A particularly promising type of SLM consists of a ferroelectric liquid-crystal (FLC) light-modulating layer on top of a silicon complementary metal-oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit.1

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Kiamilev, F., J. Fan, B. Catanzaro, S. Esener, and S. H. Lee. "Computer-aided design for optoelectronic computing." In OSA Annual Meeting. Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.fj6.

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Over the last decade there has been a dramatic increase in the use of computer-aided design (CAD) tools in the design of very-large-scale integrated (VLSI) electronic systems. This increase has been driven by the increasing complexity and fabrication cost of VLSI systems. On the other hand, optoelectronic technology is emerging as a way to build high-performance computer systems. In optoelectronic computers, electronic circuitry is used for local processing, and free-space optical interconnects are used for global communication. Optoelectronic computers will be packaged by means of the same pl

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Clymer, Bradley D. "Surface-relief grating structures for photodetectors for optical interconnects in VLSI." In OSA Annual Meeting. Optica Publishing Group, 1988. http://dx.doi.org/10.1364/oam.1988.fx3.

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The miniaturization of integrated circuit elements and the expansion of chip sizes leading to very large-scale integration (VLSI) and wafer scale integration (WSI) have created a situation in which the speed of information processing for modern computing systems has become limited by communication delays rather than gate propagation delays for logic devices. The data communication limitation on processing speed has led to considerable interest in new methods for interconnection at nearly every level of computer hierarchy. While many researchers have proposed optical solutions to interconnectio

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Reports on the topic "Very Large Scale Integrated Circuit (VLSI)"

1

Clark, Kay E. VLSI/VHSIC (Very Large Scale Integrated/Very High Speed Integrated Circuits) Package Test Development. Defense Technical Information Center, 1986. http://dx.doi.org/10.21236/ada182360.

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Cohen, Seymour. Quality Procedures for VLSI/VHSIC (Very Large Scale Integrated and Very High Speed Integrated Circuits) Type Devices. Defense Technical Information Center, 1985. http://dx.doi.org/10.21236/ada164885.

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Collier, Wiehrs L. VLSI (Very Large Scale Integrated Circuits) Implementation of a Quantized Sinusoid Filter Algorithm and Its Use to Compute the Discrete Fourier Transform. Defense Technical Information Center, 1986. http://dx.doi.org/10.21236/ada168605.

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Leighton, F. T. Theoretical Aspects of VLSI (Very Large Scale Integration) Circuit Design. Defense Technical Information Center, 1986. http://dx.doi.org/10.21236/ada175051.

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