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Relevant bibliographies by topics / Very Large Scale Integrated Circuit (VLSI) / Dissertations / Theses

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Dissertations / Theses on the topic 'Very Large Scale Integrated Circuit (VLSI)'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Liu, Yansong. "Passivity checking and enforcement in VLSI model reduction exercise." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290690.

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2

Voo, Thart Fah. "Tunable techniques for robust high frequency analogue VLSI." Thesis, Imperial College London, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.369050.

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3

Voranantakul, Suwan 1962. "CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/277037.

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4

Liu, Yansong, and 劉岩松. "Passivity checking and enforcement in VLSI model reduction exercise." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B41290690.

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5

Matsumori, Barry Alan. "QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275313.

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6

Cooke, Bradly James. "S-parameter VLSI transmission line analysis." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184876.

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This dissertation investigates the implementation of S-parameter based network techniques for the analysis of multiconductor, high speed VLSI integrated circuit and packaging interconnects. The S-parameters can be derived from three categories of input parameters: (1) lossy quasi-static R,L,C and G, (2) lossy frequency dependent (dispersive) R,L,C,G and (3) the propagation constants, Γ, the characteristic impedance, Z(c) and the conductor eigencurrents, I, derived from full wave analysis. The S-parameter network techniques developed allow for: the analysis of periodic waveform excitation, the

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7

Jafar, Mutaz 1960. "THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276959.

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8

Buchanan, Brent E. "A mixed-signal CMOS VLSI image convolution circuit using error spectrum shaping." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15420.

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9

Chabbi, Charef. "VLSI NMOS hardware design of a linear phase FIR low pass digital filter." Ohio University / OhioLINK, 1985. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183749814.

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10

高雲龍 and Wan-lung Ko. "A new optimization model for VLSI placement." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B29812938.

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11

Wilson, Denise M. "Analog VLSI architecture for chemical sensing microsystems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13322.

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12

KRISHT, MUHAMMED HUSSEIN, and MUHAMMED HUSSEIN KRISHT. "LPCVD TUNGSTEN MULTILAYER METALLIZATION FOR VLSI SYSTEMS." Diss., The University of Arizona, 1985. http://hdl.handle.net/10150/187983.

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Advances in microlithography, dry etching, scaling of devices, ion-implantation, process control, and computer aid design brought the integrated circuit technology into the era of VLSI circuits. Those circuits are characterized by high packing density, improved performance, complex circuits, and large chip sizes. Interconnects and their spacing dominate the chip area of VLSI circuits and they degrade the circuit performance through the unacceptable high time delays. Multilayer metallization enables shorter interconnects, ease of design and yet higher packing density for VLSI circuits. It was s

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13

Morris, Tonia Gay. "Analog VLSI visual attention systems." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/15010.

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14

Măndoiu, Ion I. "Approximation algorithms for VLSI routing." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/9128.

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15

Tang, Maolin. "Intelligent approaches to VLSI routing." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2000. https://ro.ecu.edu.au/theses/1375.

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Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to 'combinatorial explosion' in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today's VLSI routing system. This thesis strives to use intelligent approaches, including s

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16

Chu, Chung-kwan, and 朱頌君. "Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B38719551.

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17

Al-Mahmood, Saiyid Jami Islah Ahmad. "A distributed design rule checker for VLSI layouts." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-11012008-063423/.

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18

Kelley, Brian T. "VLSI computing architectures for high speed seismc migration." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13919.

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19

Zhang, Zheng, and 张政. "Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2010. http://hub.hku.hk/bib/B44909056.

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The Best MPhil Thesis in the Faculties of Dentistry, Engineering, Medicine and Science (University of Hong Kong), Li Ka Shing Prize,2009-2010<br>published_or_final_version<br>Electrical and Electronic Engineering<br>Master<br>Master of Philosophy

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20

Chen, Ing-yi 1962. "Efficient reconfiguration by degradation in defect-tolerant VLSI arrays." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277195.

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This thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI array consists of identical cells such as memory cells or processors. In contrast to the redundancy approach in which some cells are dedicated as spares, all the cells in the degradation approach are treated in a uniform way. Each cell can be either fault-free or defective and a subarray which contains no faulty cell is derived under constraints of switching and routing mechanisms. Although extensive literatures exist concerning spare allocation and reconfiguration in arrays with redundancy, little

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21

Narayanan, Prakash. "Analytical modeling and simulation of bicmos for VLSI circuits." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/42199.

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Interest in BiCMOS technology has been generated recently due to the potential advantages this technology offers over conventional CMOS which enjoys widespread use in today’s semiconductor industry. However, before BiCMOS can be readily adopted by the VLSI community, an understanding of the design issues and tradeoffs involved when utilizing it, must be achieved. The principal focus of this research is to move towards such an understanding through the means of analytical modeling and circuit simulation using PSPICE [1]. The device chosen for the modeling approach is the basic BiCMOS Invertin

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22

Shope, David Allen 1958. "Thermal characterization of VLSI packaging." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276686.

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With electronic packaging becoming more complex, simple hand methods to model the thermal performance of the package are insufficient. As computer aided modeling methods came into use, a test system was developed to verify the predictions produced by such modeling methods. The test system is evaluated for operation and performance. Further, the premise of this type of test (the accurate calibration of packaged temperature-sensitive-parameter devices can be done) is investigated using a series of comparative tests. From this information, causes of possible/probable errors in calibration are ide

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23

Geller, Ronnie Dee. "A VLSI architecture for a neurocomputer using higher-order predicates." Full text open access at:, 1987. http://content.ohsu.edu/u?/etd,137.

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24

Bragg, Julian Alexander. "A biomorphic analog VLSI implementation of a mammalian motor unit." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/20693.

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25

Moini, Alireza. "Synthesis of biological vision models using analog VLSI /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09phm712.pdf.

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26

Tan, Wei-Siong. "A VLSI parallel processor structure for scientific computing." Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/13455.

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27

Koelmans, Albertus Maria. "STRICT : a language and tool set for the design of very large scale integrated circuits." Thesis, University of Newcastle Upon Tyne, 1996. http://hdl.handle.net/10443/2076.

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An essential requirement for the design of large VLSI circuits is a design methodology which would allow the designer to overcome the complexity and correctness issues associated with the building of such circuits. We propose that many of the problems of the design of large circuits can be solved by using a formal design notation based upon the functional programming paradigm, that embodies design concepts that have been used extensively as the framework for software construction. The design notation should permit parallel, sequential, and recursive decompositions of a design into smaller comp

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28

Dickinson, Alex. "Complexity management and modelling of VLSI systems." Title page, contents and abstract only, 1988. http://web4.library.adelaide.edu.au/theses/09PH/09phd553.pdf.

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29

袁志勤 and Chi-kan Yuen. "A double-track greedy algorithm for VLSI channel routing." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1997. http://hub.hku.hk/bib/B31220241.

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30

Holland, Kenneth Chris. "Probability of latching single event upset errors in VLSI circuits." Thesis, Virginia Tech, 1991. http://hdl.handle.net/10919/41980.

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The ability of radiation to cause transient faults in space borne as well as ground based computers is well known. with the density of VLSI circuits increasing every year, the probability of an upset by radiation is becoming more likely. However, research in this area has matured over the last decade, and the mechanisms which cause such faults are better understood. This understanding enables us to propose ideas to eliminate or lessen the effects of radiation on VLSI circuits. <p>Most of the research to date has concentrated on the effect of transient faults on flip-flops rather than combinati

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31

Whipple, Thomas Driggs 1961. "Design and implementation of an integrated VLSI packaging support software environment." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277105.

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An interactive software shell has been developed which integrates several packaging simulation tools developed at the University of Arizona which are used to analyze electro-magnetic coupling between interconnects in an integrated circuit. This software shell uses experimental frames to manage this simulation process. Through the experimental frames, the model descriptions and the model inputs are separated, and input data is verified for correctness. This model/input separation allows several model variations to be tested based on several input variations. The results of these simulations are

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32

Ahderom, Selam T. "Opto-VLSI based WDM multifunction device." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2004. https://ro.ecu.edu.au/theses/772.

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The tremendous expansion of telecommunication services in the past decade, in part due to the growth of the Internet, has made the development of high-bandwidth optical net-works a focus of research interest. The implementation of Dense-Wavelength Division Multiplexing (DWDM) optical fiber transmission systems has the potential to meet this demand. However, crucial components of DWDM networks – add/drop multiplexers, filters, gain equalizers as well as interconnects between optical channels – are currently not implemented as dynamically reconfigurable devices. Electronic cross-connects, the tr

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33

Anbalagan, Pranav. "Limitations and opportunities for wire length prediction in gigascale integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22670.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.<br>Committee Chair: Dr. Jeff Davis; Committee Member: Dr. James D. Meindl; Committee Member: Dr. Paul Kohl; Committee Member: Dr. Scott Wills; Committee Member: Dr. Sung Kyu Lim.

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34

Boudreault, Yves 1959. "Design of a VLSI convolver for a robot vision system." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65342.

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35

雷應春 and Ying-chun Lui. "Lattice algorithms for multidimensional fields suitable for VLSI implementation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1989. http://hub.hku.hk/bib/B31208757.

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36

Blum, Richard Alan. "An analog VLSI centroid imager." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14826.

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37

Chen, Zheng. "Very large scaled integrated circuit (VLSI) implementation of a high-speed delta-sigma analog to digital converter." Ohio : Ohio University, 1997. http://www.ohiolink.edu/etd/view.cgi?ohiou1177445405.

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38

Ali, Faridah M. "Parallel pipelined VLSI arrays for real-time image processing." Diss., Virginia Polytechnic Institute and State University, 1988. http://hdl.handle.net/10919/49914.

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Real-time image processing involves processing a wide spectrum of algorithms on huge data sets. Processing at the pixel data rate demands more powerful parallel machines than those developed for conventional image processing. This research takes advantage of current VLSI technology to examine a new approach for processing arbitrary algorithms at real-time data rate. It is based on embedding the algorithms, expressed by their dependency graphs, into two dimensional regularly connected processing arrays. Each node in a graph represents an operation which can be processed by an individual proces

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39

Johnson, Timothy E. "MOSSTAT An interactive static rule checker for MOS VLSI designs." Full text open access at:, 1986. http://content.ohsu.edu/u?/etd,109.

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40

Bagchi, Tanuj. "An Efficient Hybrid Heuristic and Probabilistic Model for the Gate Matrix Layout Problem in VLSI Design." Thesis, University of North Texas, 1993. https://digital.library.unt.edu/ark:/67531/metadc500878/.

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In this thesis, the gate matrix layout problem in VLSI design is considered where the goal is to minimize the number of tracks required to layout a given circuit and a taxonomy of approaches to its solution is presented. An efficient hybrid heuristic is also proposed for this combinatorial optimization problem, which is based on the combination of probabilistic hill-climbing technique and greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test cases, five benchmark problems from the literature as well as randomly generated problem instances are

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41

Raisi, Mehrdad. "Adaptive applications of OPTO-VLSI processors in WDM networks." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2004. https://ro.ecu.edu.au/theses/840.

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Communication is an inseparable part of human life and its nature continues to evolve and improve. The advent of laser was a herald to the new possibilities in the communication world. In recent years technologies such as Wavelength Division Multiplexing (WDM) and Erbium Doped Fiber Amplifiers (EDFA) have afforded significant boost to the practice of optical communication. At the heart of this brave new world is the need to dynamically/ adaptively steer/route beams of light carrying very large amounts of data. In recent years many techniques have been proposed for this purpose by various resea

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42

Mao, Hsein-Jung Joey. "VLSI design and implementation of a parallel sorter." Ohio : Ohio University, 1988. http://www.ohiolink.edu/etd/view.cgi?ohiou1182865325.

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43

Lei, Chi-un, and 李志遠. "VLSI macromodeling and signal integrity analysis via digital signal processing techniques." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45700588.

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44

Chen, Quan, and 陈全. "Efficient high-frequency electromagnetic simulation in VLSI: rough surface effects and electromagnetic-semiconductor coupled simulation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2010. http://hub.hku.hk/bib/B44904940.

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45

Lacy, William Stephen. "Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/14690.

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46

Park, Jun Cheol. "Sleepy Stack: a New Approach to Low Power VLSI and Memory." Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-07132005-131806/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2006.<br>Mooney, Vincent J., Committee Chair ; Chatterjee, Abhijit, Committee Member ; Hasler, Paul, Committee Member ; Dorsey, John, Committee Member ; Niemier, Michael, Committee Member.

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47

Robinson, David Lyle. "Automatic Synthesis of VLSI Layout for Analog Continuous-time Filters." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4913.

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Automatic synthesis of digital VLSI layout has been available for many years. It has become a necessary part of the design industry as the window of time from conception to production shrinks with ever increasing competition. However, automatic synthesis of analog VLSI layout remains rare. With digital circuits, there is often room for signal drift. In a digital circuit, a signal can drift within a range before hitting the threshold which triggers a change in logic state. The effect of parasitic capacitances for the most part, hinders the timing margins of the signal, but not its functionality

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48

劉志宏 and Zhihong Liu. "A study of thermally nitrided silicon dioxide thin films for metal-oxide-silicon VLSI techology." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1990. http://hub.hku.hk/bib/B31231895.

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49

Shiang, Jyue-Jon 1956. "APTMC: AN INTERFACE PROGRAM FOR USE WITH ANSYS FOR THERMAL AND THERMALLY INDUCED STRESS MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/291399.

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ANSYS Packaging Thermal/Mechanical Calculator (APTMC) is an interface program developed for use with ANSYS and specially designed to handle thermal and thermally induced stress modeling/simulation of Level 1 and Level 2 VLSI packaging structures and assemblies. APTMC is written in PASCAL and operates in an interactive I/O format mode. This user-friendly tool leads an analyst/designer through the process of creating appropriate thermal and thermally induced stress models and other operations necessary to run ANSYS. It includes such steps as the following: (1) construction of ANSYS commands thro

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50

Adamo, Oluwayomi Bamidele. "VLSI Architecture and FPGA Prototyping of a Secure Digital Camera for Biometric Application." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5393/.

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This thesis presents a secure digital camera (SDC) that inserts biometric data into images found in forms of identification such as the newly proposed electronic passport. However, putting biometric data in passports makes the data vulnerable for theft, causing privacy related issues. An effective solution to combating unauthorized access such as skimming (obtaining data from the passport's owner who did not willingly submit the data) or eavesdropping (intercepting information as it moves from the chip to the reader) could be judicious use of watermarking and encryption at the source end of t

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