Relevant bibliographies by topics / Very Large Scale Integrated (VLSI) Circuits

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Very Large Scale Integrated (VLSI) Circuits'

Author: Grafiati
Published: 3 June 2025
Last updated: 1 August 2025

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Journal articles on the topic "Very Large Scale Integrated (VLSI) Circuits"

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M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M, and Rahul S.G. "Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits." ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.

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High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal
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Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.

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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits bec
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Madhura, S. "A Review on Low Power VLSI Design Models in Various Circuits." Journal of Electronics and Informatics 4, no. 2 (2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.

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Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the pe
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Yang, Boyu. "Very Large-Scale Integration Circuit and Its Current Status Analysis." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 421–27. http://dx.doi.org/10.54097/hset.v71i.14627.

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The development of Very Large Scale Integration (VLSI) has become very relevant to our lives, and although many of the technologies have matured, scientists are still actively exploring and innovating them. This article is a basic introduction to the composition and advanced technology of large-scale integrated circuits, focusing on transistors and the basic components it consists of, as well as the design of integrated circuits, manufacturing and measurement technology. Very Large Scale Integration Circuit, the transistor is the most basic component of the original, to the low-power CMOS tube
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Wölcken, Klaus. "Skill Needs in VLSI Circuits." Industry and Higher Education 6, no. 1 (1992): 50. http://dx.doi.org/10.1177/095042229200600113.

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The forecast need for designers of Very Large Scale Integrated Circuits is described. The article then goes on to outline the support being provided for academic institutions involved with VLSI design training by the European Commission's Directorate General XIII.
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Zolnikov, Vladimir, Konstantin Zolnikov, Nadezhda Ilina, and Kirill Grabovy. "Verification methods for complex-functional blocks in CAD for chips deep submicron design standards." E3S Web of Conferences 376 (2023): 01090. http://dx.doi.org/10.1051/e3sconf/202337601090.

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The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used.
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Rahman, Tasnim Ikra. "Fault Diagnosis Methods in Analog and Mixed Signal Circuits." DIU Journal of Science & Technology 14, no. 1 (2024): 23–27. https://doi.org/10.5281/zenodo.13770923.

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Fault identification of analog and mixed signal circuits is very difficult topics for previous few decades. Localization of hard and soft faults in analog circuit is often a troublesome task without a transparent cut methodology. For manufacturing process of Very Large Scale Integration (VLSI) Application Specific Integrated Circuits (ASICs) both fault diagnosis and localization are mandatory. The importance of such analog test has become important due to enhancement of networking and communication sector. This paper gives a brief review on the faults present in analog circuits and different d
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Boychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky, and Pavel Nekrasov. "Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices." Facta universitatis - series: Electronics and Energetics 28, no. 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.

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Total ionizing dose (TID) effects and radiation tests of complex multifunctional Very-large-scale integration (VLSI) integrated circuits (ICs) rise up some particularities as compared to conventional ?simple? ICs. The main difficulty is to organize informative and quick functional tests directly under irradiation. Functional tests approach specified for complex multifunctional VLSI devices is presented and the basic radiation test procedure is discussed in application to some typical examples.
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Shur, Michael. "(Invited) Industrial Face of Nanotechnology." ECS Meeting Abstracts MA2023-01, no. 16 (2023): 1452. http://dx.doi.org/10.1149/ma2023-01161452mtgabs.

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Ever since the proposal and demonstration of quantum dots in 1980 by Drs. A. Efros, Al. Efros and A. Ekimov, the relentless progress of nanotechnology has been unstoppable. And nowhere this progress is more evident than in the Si Very Large Scale Integrated Circuits (VLSI) and Thin Film Transistor (TFT) technologies. The minimum feature size of the Si VLSI with up to 2.6 trillion transistors on a chip was reduced to 3 nm in 2022 with plans for the 2 nm technology. TFTs fabricated on glass or even on cloth or paper enable integrated circuits with 50 nm tolerances over square meter sizes. These
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Gonsai, Sima K., Kinjal Ravi Sheth, Dhavalkumar N. Patel, et al. "Exploring the synergy: AI and ML in very large scale integration design and manufacturing." Bulletin of Electrical Engineering and Informatics 13, no. 6 (2024): 3993–4001. http://dx.doi.org/10.11591/eei.v13i6.8594.

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With the rapid advancements in very large scale integration (VLSI) and integrated circuit (IC) technology, the complexity of devices has escalated significantly. Designing a VLSI chip is essential for scaling up the capabilities of chips to meet the growing demands of modern applications, like artificial intelligence (AI), IoT, and high-performance computing. Chip testing and verification also emerges as crucial tasks to ensure optimal device functionality. Testing verifies the integrity of a circuit’s gates and connections, ensuring accurate operation. Throughout the chip’s design and develop
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Dissertations / Theses on the topic "Very Large Scale Integrated (VLSI) Circuits"

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Voo, Thart Fah. "Tunable techniques for robust high frequency analogue VLSI." Thesis, Imperial College London, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.369050.

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Voranantakul, Suwan 1962. "CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/277037.

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Matsumori, Barry Alan. "QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275313.

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Liu, Yansong. "Passivity checking and enforcement in VLSI model reduction exercise." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290690.

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Jafar, Mutaz 1960. "THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276959.

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Wilson, Denise M. "Analog VLSI architecture for chemical sensing microsystems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13322.

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KRISHT, MUHAMMED HUSSEIN, and MUHAMMED HUSSEIN KRISHT. "LPCVD TUNGSTEN MULTILAYER METALLIZATION FOR VLSI SYSTEMS." Diss., The University of Arizona, 1985. http://hdl.handle.net/10150/187983.

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Advances in microlithography, dry etching, scaling of devices, ion-implantation, process control, and computer aid design brought the integrated circuit technology into the era of VLSI circuits. Those circuits are characterized by high packing density, improved performance, complex circuits, and large chip sizes. Interconnects and their spacing dominate the chip area of VLSI circuits and they degrade the circuit performance through the unacceptable high time delays. Multilayer metallization enables shorter interconnects, ease of design and yet higher packing density for VLSI circuits. It was s
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Tang, Maolin. "Intelligent approaches to VLSI routing." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2000. https://ro.ecu.edu.au/theses/1375.

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Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to 'combinatorial explosion' in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today's VLSI routing system. This thesis strives to use intelligent approaches, including s
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Al-Mahmood, Saiyid Jami Islah Ahmad. "A distributed design rule checker for VLSI layouts." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-11012008-063423/.

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Narayanan, Prakash. "Analytical modeling and simulation of bicmos for VLSI circuits." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/42199.

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Interest in BiCMOS technology has been generated recently due to the potential advantages this technology offers over conventional CMOS which enjoys widespread use in today’s semiconductor industry. However, before BiCMOS can be readily adopted by the VLSI community, an understanding of the design issues and tradeoffs involved when utilizing it, must be achieved. The principal focus of this research is to move towards such an understanding through the means of analytical modeling and circuit simulation using PSPICE [1]. The device chosen for the modeling approach is the basic BiCMOS Invertin
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Books on the topic "Very Large Scale Integrated (VLSI) Circuits"

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Fco, López José, Pavlidis Dimitris, Montiel-Nelson Juan A, and Society of Photo-optical Instrumentation Engineers., eds. VLSI circuits and systems. SPIE, 2003.

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Dillinger, Thomas E. VLSI engineering. Prentice-Hall, 1988.

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J, Offen R., ed. VLSI image processing. Collins, 1985.

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Chen, Wai-Kai. VLSI technology. CRC Press, 2003.

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IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration (1987 Vancouver, Canada). VLSI 87: VLSI design of digital systems. North-Holland, 1988.

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Hurst, S. L. Custom VLSI microelectronics. Prentice Hall, 1992.

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Shih-Chii, Liu, ed. Analog VLSI: Circuits and principles. MIT Press, 2002.

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P, Pirsch, ed. VLSI implementations for image communications. Elsevier, 1993.

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Churiwala, Sanjay. Principles of VLSI RTL design: A practical guide. Springer, 2011.

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Hartmut, Grabinski, ed. Interconnects in VLSI design. Kluwer Academic Publishers, 2000.

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Book chapters on the topic "Very Large Scale Integrated (VLSI) Circuits"

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Ghate, P. B. "Metallization for Very Large-Scale Integrated Circuits." In Handbook of Advanced Semiconductor Technology and Computer Systems. Springer Netherlands, 1988. http://dx.doi.org/10.1007/978-94-011-7056-7_6.

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Ghavami, Behnam, and Mohsen Raji. "GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits." In Soft Error Reliability of VLSI Circuits. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-51610-9_4.

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Rachmuth, Guy, and Chi-Sang Poon. "In-Silico Model of NMDA and Non-NMDA Receptor Activities Using Analog Very-Large-Scale Integrated Circuits." In Advances in Experimental Medicine and Biology. Springer US, 2004. http://dx.doi.org/10.1007/0-387-27023-x_26.

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Golanbari, Mohammad Saber, Mojtaba Ebrahimi, Saman Kiamehr, and Mehdi B. Tahoori. "Selective Flip-Flop Optimization for Circuit Reliability." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_14.

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AbstractThis chapter proposes a selective flip-flop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flip-flop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are improved by optimizing the timing-critical components under severe impact of runtime variations. As flip-flops are vulnerable to aging and supply voltage fluctuation, it is necessary to address these reliability issues in order to improve the ove
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Gebregiorgis, Anteneh, Rajendra Bishnoi, and Mehdi B. Tahoori. "Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) Caches." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_13.

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AbstractNear-threshold computing (NTC) has significant role in reducing the energy consumption of modern very large-scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This chapter presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near-threshold voltage caches. The ob
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MOHSEN, AMR, SAI WAI FU, and CARL SIMONSEN. "Fundamental Principles of Very Large Scale Integrated Circuit Design." In Vlsi Handbook. Elsevier, 1985. http://dx.doi.org/10.1016/b978-0-12-234100-7.50008-3.

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Bhardwaj, Shivam, Mr Shivam, Jay Varshney, Inderpreet Kaur, and Hari Kumar Singh. "INTEGRATED CIRCUITS FABRICATION TECHNIQUES FOR C-MOS, N-MOS AND BJT." In Futuristic Trends in Network & Communication Technologies Volume 2 Book 19. Iterative International Publishers, Selfypage Developers Pvt Ltd, 2023. http://dx.doi.org/10.58532/v2bs19p3ch4.

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Integrated Circuit designs will be realised in one of a number of possible fabrication processes. The circuit fabricated on a die will then be packaged within a suitable protective housing. The particular fabrication process to use will be dependent on a number of issues including cost, availability, experience in the use of, and circuit component capabilities. Complex processes and technology utilizing minute dimensions are essential to the fabrication of today’s high density integrated circuits. The key unit processes for circuit fabrication outlined within this paper are chemical vapor depo
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Majeed, Mohammed Rasheed, Aqeel Ali, Ali Selman Hatem, and Ahmad Alkhayyat. "VLSI Solutions for Real-Time Financial Risk Management." In Advances in Computational Intelligence and Robotics. IGI Global, 2024. https://doi.org/10.4018/979-8-3693-7367-5.ch007.

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With a specific emphasis on the necessity of rapid-fire data processing and decision-making in the context of fiscal requests, it discusses how the discoveries of VLSI can significantly increase the speed and efficacy of threat assessment algorithms. Specifically, it focuses on how these algorithms can be more effective. The design and implementation of very large-scale integrated circuits (VLSI) that are optimized for financial computations are being researched as part of this investigation. Specifically, the circuits' capacity to process complex, high-frequency trade data with a minimum of d
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Isam, Mustafa, Najlaa Nasrulaah Faris, Abdullatef Mohammad Alfara, and Ahmad Alkhayyat. "VLSI-Based Real-Time Banking Security Systems." In Advances in Computational Intelligence and Robotics. IGI Global, 2024. https://doi.org/10.4018/979-8-3693-7367-5.ch008.

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The process of incorporating technology that is founded now being carried out. To improve the efficiency of security measures that are essential for the protection of sensitive financial data, the purpose of this study is to investigate the implementation of modern VLSI techniques. More specifically, the purpose of this work will be to enhance the efficiency of the security measures taking place. To provide dependable encryption, secure authentication methods, and efficient data processing in real-time scripts, the study explores the approaches that are now in use and provides novel alternativ
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Singh, Bhupinder, and Anjali Raghav. "Artificial Intelligence and Machine Learning in VLSI." In Advances in Computational Intelligence and Robotics. IGI Global, 2024. https://doi.org/10.4018/979-8-3693-7367-5.ch022.

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The revolution of energy management in Very Large Scale Integration (VLSI) can be realized for lower power and sustainability with Artificial Intelligence (AI) and Machine Learning (ML) as an essential tool to maintain the smart city. Reduction of size is the origin of very-scale integrated (VLSI) technology that permits as usual more complex circuit building and also achieves higher densities in electronics systems. AI and ML machines optimize the performance of these systems resulting in a higher clean energy yield, solving for some or all supporting smart cities with equitable access is tou
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Conference papers on the topic "Very Large Scale Integrated (VLSI) Circuits"

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Ayache, Mouadh, Enkele Rama, Saleh Mulhem, Mladen Berekovic, and Matthias Korb. "Holistic Framework for Evaluating the Trustworthiness of Integrated Circuits." In 2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2024. https://doi.org/10.1109/vlsi-soc62099.2024.10767800.

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Prieto, Arturo, and Joachim Rodrigues. "High-Density Standard Cell Library for Sequential 3D Integrated Circuits." In 2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2024. https://doi.org/10.1109/vlsi-soc62099.2024.10767816.

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Kelly, R. G., J. Yuan, S. H. Jones, et al. "Embeddable Microinstruments for Corrosion Monitoring." In CORROSION 1997. NACE International, 1997. https://doi.org/10.5006/c1997-97294.

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Abstract The design and development of an embeddable corrosion measurement microsystem which takes advantage of the increased availability of Application Specific Integrated Circuit (ASIC) development and Very Large Scale Integrated (VLSI) circuit manufacturing is described. Key elements of the system (micropotentiostat with zero resistance ammeter (ZRA) and analog-to-digital (A/D) and digital-to-analog (D/A) converters were tested electronically and found to perform satisfactorily. The micropotentiostat/ZRA combination was also tested on steel electrodes exposed to 0.6 M NaCl, saturated Ca(OH
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Kolluru, Sumanth, and Kenneth S. Stevens. "Behavioral Simulation of Relative Timed Asynchronous Circuits." In 2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2024. https://doi.org/10.1109/vlsi-soc62099.2024.10767832.

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Bathalapalli, Venkata K. V. V., Aakarshan Kumar, Saraju P. Mohanty, Elias Kougianos, and Venkata P. Yanambaka. "BlockShield: A TPM-Integrated Blockchain-Based Framework for Shielding Against Deepfakes." In 2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2024. https://doi.org/10.1109/vlsi-soc62099.2024.10767827.

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Chen, Rui, Virat Tara, Minho Choi, et al. "Toward very-large-scale nonvolatile electrically programmable photonic integrated circuits with deterministic multilevel operation." In CLEO: Applications and Technology. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/cleo_at.2024.am1j.5.

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We present a scalable platform for very-large-scale programmable photonics by marrying 300-mm-wafer-scale fab with in-house phase-change material integration, showcasing reversible electrical tuning. We further demonstrate a deterministic multilevel scheme with 2N optical levels.
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Pan, James N. "A new era of sub-1nm microwave photonics nano-wireless ultra large scale integration (Nano Wireless ULSI): very low power and superior performance advantages for millimeter wave photonics computing." In Smart Photonic and Optoelectronic Integrated Circuits 2025, edited by Sailing He and Laurent Vivien. SPIE, 2025. https://doi.org/10.1117/12.3034215.

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Jahanian, Shahriar, and Jamshid Goshtasbi-G. "On the Reliability Analysis of VLSI Chips When Subjected to Thermal Cycling." In ASME 1997 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 1997. http://dx.doi.org/10.1115/imece1997-1353.

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Abstract Elevated temperature has been considered as a dominant factor of stress which lowers the reliability and life expectancy of the microelectronics devices. Arrhenius model is commonly used for predicting the reliability and failure rate of the microelectronics devices as a function of ambient temperature. Arrhenuis model extrapolates life data, obtained from units tested at constant elevated temperatures, to the working temperatures. Generally, the temperature of microelectronics devices are lowered using an appropriate cooling method to achieve a desired reliability and life expectancy
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Michailidis, Anastasios, Thomas Noulis, and Kostas Siozios. "Linear and Periodic State Integrated Circuits Noise Simulation Benchmarking." In 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2022. http://dx.doi.org/10.1109/vlsi-soc54400.2022.9939575.

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Clymer, B. D., and J. W. Goodman. "Detection of optically distributed clock signals for very large scale integrated circuits." In OSA Annual Meeting. Optica Publishing Group, 1985. http://dx.doi.org/10.1364/oam.1985.tue1.

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The miniaturization of integrated circuit elements by scaling in very large scale integrated circuits (VLSI) has created a great deal of interest in the timing skew associated with transmitting signals via circuit lines to remote locations on a chip. As device sizes decrease and chip sizes increase with technological advances, the speed of the circuits on a VLSI chip becomes limited by signal transmission delays rather than device switching delays. Of particular interest is the clock signal that allows the system operations to be timed synchronously with one another. Parasitic transmission lin
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Reports on the topic "Very Large Scale Integrated (VLSI) Circuits"

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Clark, Kay E. VLSI/VHSIC (Very Large Scale Integrated/Very High Speed Integrated Circuits) Package Test Development. Defense Technical Information Center, 1986. http://dx.doi.org/10.21236/ada182360.

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Cohen, Seymour. Quality Procedures for VLSI/VHSIC (Very Large Scale Integrated and Very High Speed Integrated Circuits) Type Devices. Defense Technical Information Center, 1985. http://dx.doi.org/10.21236/ada164885.

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Collier, Wiehrs L. VLSI (Very Large Scale Integrated Circuits) Implementation of a Quantized Sinusoid Filter Algorithm and Its Use to Compute the Discrete Fourier Transform. Defense Technical Information Center, 1986. http://dx.doi.org/10.21236/ada168605.

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