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Journal articles on the topic 'Very Large Scale Integrated (VLSI) Circuits'

Author: Grafiati

Published: 3 June 2025

Last updated: 1 August 2025

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1

M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M, and Rahul S.G. "Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits." ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.

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High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal

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Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.

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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits bec

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Madhura, S. "A Review on Low Power VLSI Design Models in Various Circuits." Journal of Electronics and Informatics 4, no. 2 (2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.

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Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the pe

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Yang, Boyu. "Very Large-Scale Integration Circuit and Its Current Status Analysis." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 421–27. http://dx.doi.org/10.54097/hset.v71i.14627.

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The development of Very Large Scale Integration (VLSI) has become very relevant to our lives, and although many of the technologies have matured, scientists are still actively exploring and innovating them. This article is a basic introduction to the composition and advanced technology of large-scale integrated circuits, focusing on transistors and the basic components it consists of, as well as the design of integrated circuits, manufacturing and measurement technology. Very Large Scale Integration Circuit, the transistor is the most basic component of the original, to the low-power CMOS tube

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Wölcken, Klaus. "Skill Needs in VLSI Circuits." Industry and Higher Education 6, no. 1 (1992): 50. http://dx.doi.org/10.1177/095042229200600113.

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The forecast need for designers of Very Large Scale Integrated Circuits is described. The article then goes on to outline the support being provided for academic institutions involved with VLSI design training by the European Commission's Directorate General XIII.

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Zolnikov, Vladimir, Konstantin Zolnikov, Nadezhda Ilina, and Kirill Grabovy. "Verification methods for complex-functional blocks in CAD for chips deep submicron design standards." E3S Web of Conferences 376 (2023): 01090. http://dx.doi.org/10.1051/e3sconf/202337601090.

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The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used.

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7

Rahman, Tasnim Ikra. "Fault Diagnosis Methods in Analog and Mixed Signal Circuits." DIU Journal of Science & Technology 14, no. 1 (2024): 23–27. https://doi.org/10.5281/zenodo.13770923.

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Fault identification of analog and mixed signal circuits is very difficult topics for previous few decades. Localization of hard and soft faults in analog circuit is often a troublesome task without a transparent cut methodology. For manufacturing process of Very Large Scale Integration (VLSI) Application Specific Integrated Circuits (ASICs) both fault diagnosis and localization are mandatory. The importance of such analog test has become important due to enhancement of networking and communication sector. This paper gives a brief review on the faults present in analog circuits and different d

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Boychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky, and Pavel Nekrasov. "Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices." Facta universitatis - series: Electronics and Energetics 28, no. 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.

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Total ionizing dose (TID) effects and radiation tests of complex multifunctional Very-large-scale integration (VLSI) integrated circuits (ICs) rise up some particularities as compared to conventional ?simple? ICs. The main difficulty is to organize informative and quick functional tests directly under irradiation. Functional tests approach specified for complex multifunctional VLSI devices is presented and the basic radiation test procedure is discussed in application to some typical examples.

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9

Shur, Michael. "(Invited) Industrial Face of Nanotechnology." ECS Meeting Abstracts MA2023-01, no. 16 (2023): 1452. http://dx.doi.org/10.1149/ma2023-01161452mtgabs.

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Ever since the proposal and demonstration of quantum dots in 1980 by Drs. A. Efros, Al. Efros and A. Ekimov, the relentless progress of nanotechnology has been unstoppable. And nowhere this progress is more evident than in the Si Very Large Scale Integrated Circuits (VLSI) and Thin Film Transistor (TFT) technologies. The minimum feature size of the Si VLSI with up to 2.6 trillion transistors on a chip was reduced to 3 nm in 2022 with plans for the 2 nm technology. TFTs fabricated on glass or even on cloth or paper enable integrated circuits with 50 nm tolerances over square meter sizes. These

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Gonsai, Sima K., Kinjal Ravi Sheth, Dhavalkumar N. Patel, et al. "Exploring the synergy: AI and ML in very large scale integration design and manufacturing." Bulletin of Electrical Engineering and Informatics 13, no. 6 (2024): 3993–4001. http://dx.doi.org/10.11591/eei.v13i6.8594.

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With the rapid advancements in very large scale integration (VLSI) and integrated circuit (IC) technology, the complexity of devices has escalated significantly. Designing a VLSI chip is essential for scaling up the capabilities of chips to meet the growing demands of modern applications, like artificial intelligence (AI), IoT, and high-performance computing. Chip testing and verification also emerges as crucial tasks to ensure optimal device functionality. Testing verifies the integrity of a circuit’s gates and connections, ensuring accurate operation. Throughout the chip’s design and develop

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Shan, Tianchang. "Advancements in VLSI low-power design: Strategies and optimization techniques." Applied and Computational Engineering 41, no. 1 (2024): 22–28. http://dx.doi.org/10.54254/2755-2721/41/20230706.

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As production technology advances, integrated circuits are increasing in size, leading to a corresponding rise in power consumption if not properly optimized. Consequently, the optimization of integrated circuit power consumption has gained paramount significance. This paper provides an overview of the theoretical and research developments in Very Large Scale Integration (VLSI) low-power design. Initially, the paper delves into the components of VLSI power consumption, elucidating the origins of various power consumption types and the factors influencing their magnitude. Subsequently, existing

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Maskowitz, J. V., W. E. Rhoden, D. R. Kitchen, R. E. Omlor, and P. F. Lloyd. "In situ STEM observations of electromigration on thin aluminum stripes." Proceedings, annual meeting, Electron Microscopy Society of America 44 (August 1986): 740–41. http://dx.doi.org/10.1017/s0424820100145078.

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The existence of electromigration in thin films has been acknowledged since the early sixties. Electromigration is described as the main transport for atoms in a conductor under a current stress. Initial interest had been of a theoretical nature as electromigration had little impact on circuit reliability. With the maturing of Very Large Scale Integrated Circuit (VLSI) technology, current densities are exceeding 106 Amps/cm2 while linestripes are reaching into the submicron range. In this environment, electromigration can cause unwanted open or short circuits in thin films. This has serious im

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13

CHEN, JIANLI, and WENXING ZHU. "A PLACEMENT FLOW FOR VERY LARGE-SCALE MIXED-SIZE CIRCUIT PLACEMENT." Journal of Circuits, Systems and Computers 23, no. 02 (2014): 1450016. http://dx.doi.org/10.1142/s0218126614500169.

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The very large-scale integrated circuit (VLSI) placement problem is to determine the exact location of each movable circuit element within a given region. It is a crucial process in physical design, since it affects performance, power consumption, routability, and heat distribution of a design. In this paper, we propose a VLSI placement flow to handle the large-scale mixed-size placement problem. The main idea of our placement flow is using a floorplanning algorithm to guide the placement of circuit elements. It consists of four steps: (1) With the multilevel framework, circuit elements are cl

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14

B, Harshitha. "An Area and Power Optimization for Level Shifters using 45nm CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 4951–55. http://dx.doi.org/10.22214/ijraset.2024.62674.

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Abstract: Modern integrated circuits require level shifters as essential parts to enable communication between circuits running at various voltage levels. Design-wise, the Level Shifter has a minimal silicon footprint due to its limited component count and operates with minimal power usage, making it well-suited for energy-efficient applications. This work implements CMOS voltage level shifter, also known as conventional CMOS level shifter. The level shifter's overall power and area usage are compared. CMOS level shifters simulations are carried out using CADENCE tool. The simulation's outcome

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15

Dove, Lewis. "Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS." Journal of Microelectronics and Electronic Packaging 6, no. 1 (2009): 38–41. http://dx.doi.org/10.4071/1551-4897-6.1.38.

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Mixed-signal Application Specific Integrated Circuits (ASICs) have traditionally been used in test and measurement applications for a variety of functions such as data converters, pin electronics circuitry, drivers, and receivers. Over the past several years, the complexity, power density, and bandwidth of these chips has increased dramatically. This has necessitated dramatic changes in the way these chips have been packaged. As the chips have become true VLSI (Very Large Scale Integration) ICs, the number of I/Os have become too large to interconnect with wire bonds. Thus, it has become neces

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Shakir, Muhammad, Shuoben Hou, Raheleh Hedayati, Bengt Gunnar Malm, Mikael Östling, and Carl-Mikael Zetterling. "Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications." Electronics 8, no. 5 (2019): 496. http://dx.doi.org/10.3390/electronics8050496.

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A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on l

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Liu, Fengyuan. "Stochastic Nature of Large-Scale Contact Printed ZnO Nanowires Based Transistors." Stochastic Nature of Large-Scale Contact Printed ZnO Nanowires Based Transistors 35, no. 2 (2024): 2412299. https://doi.org/10.1002/adfm.202412299.

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Printing technology holds great potential for resource-efficient development of electronic devices and circuits. However, even after decades of research, achieving uniformly responding nanowires (NWs) based printed devices is still a challenge. To date, there is no design rule that clearly guides the fabrication of NW ensemble-based field-effect transistors (FETs) and the variables that influence device-level uniformity remain unclear. The lack of fundamental understanding severely limits the large-scale and very large-scale integration (LSI and VLSI). Herein this longstanding issue is address

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Rajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics." Journal of Circuits, Systems and Computers 27, no. 13 (2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.

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Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write

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19

Zhang, Jin, Zhenghui Liu, Xiao Hu, Peixin Liu, Zhiling Hu, and Lidan Kuang. "FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs." Electronics 13, no. 9 (2024): 1667. http://dx.doi.org/10.3390/electronics13091667.

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The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As

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20

Wong, C. P. "Electrical performance and reaction kinetics of silicone gels." Journal of Materials Research 5, no. 4 (1990): 795–800. http://dx.doi.org/10.1557/jmr.1990.0795.

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Silicone gels are becoming more accepted as protective coatings for Very Large Scale Integrated circuits (VLSI) against severe environments due to their excellent electrical, thermal, and mechanical properties. Recent studies indicate that high performance silicone gels in low-cost, non-hermetic plastic packaging may replace conventional hermetic ceramic packaging. This paper describes the use of the soft silicone gels as coatings on Integrated Circuit (IC) devices, and the correlation between the material's cure temperature and cure time versus their adhesion and electrical reliability during

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M, Pradeep, Udutha Rajender, Pravin Prakash Adivarekar, and Sumit Kumar Gupta. "BALANCING COST AND PERFORMANCE IN VLSI SYSTEMS USING RMSPROP ALGORITHM-ASSISTED DESIGN SPACE EXPLORATION." ICTACT Journal on Microelectronics 9, no. 2 (2023): 1580–84. https://doi.org/10.21917/ijme.2023.0275.

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As Very Large Scale Integration (VLSI) technology advances, the need to efficiently balance cost and performance in VLSI systems becomes paramount. To address this challenge, we propose a novel approach that leverages the RMSPROP algorithm for assisted design space exploration. The RMSPROP algorithm, which has proven effective in the field of deep learning optimization, is adapted to navigate the complex design space of VLSI systems. By integrating RMSPROP into the design space exploration process, we can intelligently search for optimal trade-offs between cost and performance, leading to high

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Pan, Li Yan, and Yan Pei Liu. "An Application of Rectilinear Embedding in VLSI Placement." Advanced Materials Research 734-737 (August 2013): 2842–45. http://dx.doi.org/10.4028/www.scientific.net/amr.734-737.2842.

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The VLSI (Very Large Scale Integrated Circuits) technology has developed rapidly in recent years, with a lot of advanced electric products emerging. Placement layout is regarded as the initial step in VLSI physical design. Its quality has a direct effect on the chip area and performance. The rectilinear embedding, which originates from graph theory, is widely employed in VLSI placement. In this paper, we set up a mathematical model for VLSI. Firstly, the issue of VLSI placement was converted to quadrangulation by using rectilinear embedding. Then we provided generating functions for two types

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Siddesh, K. B., S. Roopa, Parveen B. A. Farzana, and T. Tanuja. "Design of duty cycle correction circuit using ASIC implementation for high speed communication." i-manager’s Journal on Electronics Engineering 13, no. 3 (2023): 33. http://dx.doi.org/10.26634/jele.13.3.19969.

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This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cy

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Im, James S., and Robert S. Sposili. "Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays." MRS Bulletin 21, no. 3 (1996): 39–48. http://dx.doi.org/10.1557/s0883769400036125.

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The fabrication of thin-film-transistor (TFT) devices on a transparent substrate lies at the heart of active-matrix-liquid-crystal-display (AMLCD) technology. This is both good and bad. On one hand it is a difficult task to manufacture millions of intricate semiconductor devices reliably over such large display substrates. On the positive side, AMLCD technology can aspire to become much more than a “display” technology. The idea is as follows: It is possible for one to readily fabricate additional transistors to execute various electronic functions—those that would otherwise be handled by sepa

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Li, Jian, Robert Blewer, and J. W. Mayer. "Copper-Based Metallization for ULSI Applications." MRS Bulletin 18, no. 6 (1993): 18–21. http://dx.doi.org/10.1557/s088376940004728x.

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Multilevel metallization of very large-scale integrated (VLSI) circuits has become an area of intense research interest as devices are scaled down in order to increase circuit density. As device dimensions approach the submicron regime, reliability becomes more of an issue. Metallization generally requires good conductivity, electromigration resistance, controllable contact performance, corrosion resistance, adherence, thermal stability, bondability, ability to be patterned into a desirable geometry, and economic feasibility.Aluminum and its alloys have been commonly used as the main metalliza

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Nagarajan, Sridevi, and Prasanna Kumar Mahadeviah. "On-chip based power estimation for CMOS VLSI circuits using support vector machine." Indonesian Journal of Electrical Engineering and Computer Science 35, no. 2 (2024): 804. http://dx.doi.org/10.11591/ijeecs.v35.i2.pp804-811.

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Power estimation has a major impact on the reliability of very-large-scale integration (VLSI) circuits. As a results power estimation is highly needed in VLSI circuits at the early stages. One of the evident challenges in integrated circuit (IC) industry is development and investigation of techniques for the reduction of design complexity due to the growing process variations and reduction of chip manufacturing turnaround time. Under these conditions, the higher design levels of average power estimation before the chip manufacturing process is highly essential for the calculation of power budg

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Sridevi, Nagarajan Prasanna Kumar Mahadeviah. "On-chip based power estimation for CMOS VLSI circuits using support vector machine." Indonesian Journal of Electrical Engineering and Computer Science 35, no. 2 (2024): 804–11. https://doi.org/10.11591/ijeecs.v35.i2.pp804-811.

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Power estimation has a major impact on the reliability of very-large-scale integration (VLSI) circuits. As a results power estimation is highly needed in VLSI circuits at the early stages. One of the evident challenges in integrated circuit (IC) industry is development and investigation of techniques for the reduction of design complexity due to the growing process variations and reduction of chip manufacturing turnaround time. Under these conditions, the higher design levels of average power estimation before the chip manufacturing process is highly essential for the calculation of power budg

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Dayanand, Swathi, R. Varshitha K, Rohini T, Yasha Jyothi M. Shirur, and Jyoti R. Munavalli. "Low Power High Speed Vedic Techniques in Recent VLSI Design – A Survey." Perspectives in Communication, Embedded-systems and Signal-processing - PiCES 4, no. 6 (2020): 147–56. https://doi.org/10.5281/zenodo.4247825.

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Advancement in the Artificial Intelligence (AI) and Machine Learning (ML) has influenced complex designs to be integrated in Very Large-Scale Integration (VLSI) Design. Designers are concentrating on high speed and low power techniques to facilitate the needs of the technology requirements. In multiple AI applications, Digital Signal Processor is the building block, optimization of it may solve the issues related to computation of the data signal at faster rate consuming less power using Vedic mathematics. In this paper, a detailed review is made on recent applications of Vedic Mathematics in

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MOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (2021): 505–11. http://dx.doi.org/10.6036/10214.

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Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit

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Oliver Ava, Muhammad Oscar, and Tommy George. "The Impact and Prevention of Latch-up in CMOS in VLSI Design." Fusion of Multidisciplinary Research, An International Journal 1, no. 01 (2020): 1–13. https://doi.org/10.63995/vgrd5263.

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Latch-up in CMOS (Complementary Metal-Oxide-Semiconductor) technology is a significant reliability concern in VLSI (Very Large Scale Integration) design. Latch-up is a parasitic, unintended creation of a low-impedance path between the power supply rails due to the triggering of parasitic thyristor structures inherent in CMOS processes. This phenomenon can lead to device malfunction, excessive current flow, and potential permanent damage to the integrated circuit. The impact of latch-up is profound, as it compromises the stability and functionality of electronic systems, especially in high-perf

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Horiuchi, Timothy K., and Christof Koch. "Analog VLSI-Based Modeling of the Primate Oculomotor System." Neural Computation 11, no. 1 (1999): 243–65. http://dx.doi.org/10.1162/089976699300016908.

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One way to understand a neurobiological system is by building a simulacrum that replicates its behavior in real time using similar constraints. Analog very large-scale integrated (VLSI) electronic circuit technology provides such an enabling technology. We here describe a neuromorphic system that is part of a long-term effort to understand the primate oculomotor system. It requires both fast sensory processing and fast motor control to interact with the world. A one-dimensional hardware model of the primate eye has been built that simulates the physical dynamics of the biological system. It is

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Mishra, Prateek. "Exploring Diverse Approaches in VLSI Design Methodologies." International Journal of Multidisciplinary Research in Science, Engineering and Technology 6, no. 05 (2023): 391–94. http://dx.doi.org/10.15680/ijmrset.2023.0605056.

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The field of Very-Large-Scale Integration (VLSI) design has witnessed significant evolution, driven by advances in technology and the increasing complexity of integrated circuits. This paper provides a comprehensive examination of various methodologies employed in VLSI design, aiming to shed light on their unique advantages, limitations, and applications. We categorize the methodologies into traditional, contemporary, and emerging approaches, including Full Custom Design, Standard Cell Design, and ASIC/FPGA-based design strategies. Through comparative analysis, we explore how each approach add

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Sun, Ben. "Interpretable machine learning in VLSI physical design." Applied and Computational Engineering 4, no. 1 (2023): 13–19. http://dx.doi.org/10.54254/2755-2721/4/20230338.

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Today's popularisation of portable devices largely depends on the progress in integrated circuits. Modern Very Large Scale Integration technology (VLSI) allows billions of transistors to be packed into the same chip. In the past years, digital design in VLSI has been developed compared to analogue design. The traditional method is hard to model the performance change in analogue or mixed-signal components caused by physical design. In the early 2000s, rapid advances in machine learning and computing power made analogue design automation possible. Despite their outstanding performance, the tran

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IKEDA, SHOJI, HIDEO SATO, MICHIHIKO YAMANOUCHI, et al. "RECENT PROGRESS OF PERPENDICULAR ANISOTROPY MAGNETIC TUNNEL JUNCTIONS FOR NONVOLATILE VLSI." SPIN 02, no. 03 (2012): 1240003. http://dx.doi.org/10.1142/s2010324712400036.

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We review recent developments in magnetic tunnel junctions with perpendicular easy axis (p-MTJs) for nonvolatile very large scale integrated circuits (VLSIs). So far, a number of material systems such as rare-earth/transition metal alloys, L10-ordered ( Co, Fe )– Pt alloys, Co /( Pd, Pt ) multilayers, and ferromagnetic-alloy/oxide stacks have been proposed as electrodes in p-MTJs. Among them, p-MTJs with single or double ferromagnetic-alloy/oxide stacks, particularly CoFeB–MgO , were shown to have high potential to satisfy major requirements for integration.

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Diéguez, Ángel, Joan Canals, Sergio Moreno, and Anna Vilà. "Gamification for Teaching Integrated Circuit Processing in an Introductory VLSI Design Course." Education Sciences 14, no. 8 (2024): 921. http://dx.doi.org/10.3390/educsci14080921.

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Gamification is being incorporated into university classrooms due to its educational benefits for students learning, including encouraging student behavior and engagement, and consequently improving learning outcomes. Despite gamification being increasingly used in education, little has been developed related to Very-Large-Scale Integration (VLSI). In this article, we describe two different gamification experiences applied to integrated circuit processing and design in an introductory VLSI design course for Electronic Engineers. While gamification in universities is still not very mature and o

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Cheung, R., and P. Argyrakis. "Microscale sensors based on silicon carbide and silicon." Proceedings of the Institution of Mechanical Engineers, Part C: Journal of Mechanical Engineering Science 222, no. 1 (2008): 19–26. http://dx.doi.org/10.1243/09544062jmes663.

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The current paper consists of two topics related to microelectromechanical systems (MEMS). The first topic reviews recent advances made in the area of silicon carbide (SiC) MEMS for applications in harsh environments. Given the unique properties of SiC, the potential and progress in the development and deployment of the harsh environment material for the fabrication and characterization of resonators and pressure sensors are described. The second topic details the motivation behind the study of biologically inspired systems and how silicon-based microscale sensors with out-of-plane structures

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Wong, C. P. "An Overview of Integrated Circuit Device Encapsulants." Journal of Electronic Packaging 111, no. 2 (1989): 97–107. http://dx.doi.org/10.1115/1.3226528.

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The rapid development of integrated circuit technology from small-scale integration (SSI) to very large scale integration (VLSI) has had great technological and economical impact on the electronics industry. The exponential growth of the number of components per IC chip, the exponential decrease of device dimensions, and the steady increase in IC chip size have imposed stringent requirements, not only on the IC physical design and fabrication, but also on IC encapsulants. This report addresses the purpose of encapsulation, encapsulation techniques, and a general overview of the application of

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Beck, Anthony, Franziska Obst, Mathias Busek, et al. "Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration." Micromachines 11, no. 5 (2020): 479. http://dx.doi.org/10.3390/mi11050479.

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The interest in large-scale integrated (LSI) microfluidic systems that perform high-throughput biological and chemical laboratory investigations on a single chip is steadily growing. Such highly integrated Labs-on-a-Chip (LoC) provide fast analysis, high functionality, outstanding reproducibility at low cost per sample, and small demand of reagents. One LoC platform technology capable of LSI relies on specific intrinsically active polymers, the so-called stimuli-responsive hydrogels. Analogous to microelectronics, the active components of the chips can be realized by photolithographic micro-pa

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Katircioglu, Haluk, JohnA De Beule, Debaditya Mukherjee, and GaryC Whitlock. "4932028 Error log system for self-testing in very large scale integrated circuit (VLSI) units." Microelectronics Reliability 31, no. 2-3 (1991): viii. http://dx.doi.org/10.1016/0026-2714(91)90267-b.

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Sun, Chongjun, and Chao Ding. "Study on Calibration Method for Testing During Burn In equipment of integrated circuits." Journal of Physics: Conference Series 2029, no. 1 (2021): 012035. http://dx.doi.org/10.1088/1742-6596/2029/1/012035.

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Abstract In order to implement Method 1015 of GJB 548B, TDBI(Testing During Burn In) technology of integrated circuit is widely used in the aging process of core VLSI(Very Large Scale Integration) which is included of FPGA, DSP, CPU and dedicated chips. Many models of TDBI equipment at home or abroad have been come into use. It is an important task to calibrate TDBI equipment in system level and ensure the traceability of its measurement value. At present, the calibration device of TDBI equipment has been successfully finalized and put into production, which has the advantages of convenient us

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Solanki, Saurabh. "Low-Power VLSI Design for Next-Gen IoT Devices." International Journal of Research in Modern Engineering & Emerging Technology 10, no. 5 (2022): 9–16. https://doi.org/10.63345/ijrmeet.org.v10.i5.2.

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The advancement of the Internet of Things (IoT) is heavily reliant on the design of efficient, low-power integrated circuits that can support a wide range of IoT applications. Low-power Very-Large-Scale Integration (VLSI) design has emerged as a critical factor in extending battery life and reducing energy consumption for next-generation IoT devices. This manuscript explores recent trends and methodologies in low-power VLSI design specifically tailored for IoT devices. It covers key design techniques, from voltage scaling and power gating to clock gating, and discusses the impact of technology

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Zhang, Ai Rong. "The Integration on Electrical Control Systems Based on Optimized Method." Advanced Materials Research 490-495 (March 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.

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Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity a

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S., Jothilakshmi, Manikanda Kumaran T., and Rekha S. "Controlling factors affecting the stability and rate of electroless copper plating." Journal of Indian Chemical Society Vol. 96, Jan 2019 (2019): 153–57. https://doi.org/10.5281/zenodo.5653450.

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Research and Development, Bharathiar University, Coimbatore-641 046, Tamilnadu, India <em>E-mail</em>: rekhaperichiappan@gmail.com Department of Chemistry, R.M.D. Engineering College, Kavaraipettai-601 206, Tamilnadu, India <em>Manuscript received online 30 August 2018, accepted 10 October 2018</em> The main purpose of this article is to focus on the electroless copper deposition from EDTA bath which is used in printed circuit boards (PCB) and very large scale integrated circuits (VLSI). The effect of the bath operating conditions and bath additives on plating rate, bath stability and morpholo

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Ahmad, Afaq, Sabir Hussain, M. A. Raheem, Ahmed Al Maashri, Sayyid Samir Al Busaidi, and Medhat Awadalla. "ASIC vs FPGA based Implementations of Built-In Self-Test." International Journal of Advanced Natural Sciences and Engineering Researches 7, no. 6 (2023): 14–20. http://dx.doi.org/10.59287/ijanser.942.

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Linear Feedback Shift Registers (LFSRs) are play key role in testing of for Very Large Scale Integration (VLSI) Integrated Circuits (ICs) testing. Due to tremendous IC complex growth, testing of recent VLSI ICs technology have become more complicated. This led to develop a popular alternate viable solution in the form of Built-In Self-Test (BIST) technology as compared to Automatic Test Equipment (ATE). However, the challenges of BIST technology remain the subject of research. Furthermore, implementation of BIST’s LFSR on Application Specific Integrated Circuit (ASIC) versus Field Programmable

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Luo, Guozheng, Xiang Chen, and Shanshan Nong. "Net Clusting Based Low Complexity Coarsening Algorithm In k-way Hypergraph Partitioning." Journal of Physics: Conference Series 2245, no. 1 (2022): 012019. http://dx.doi.org/10.1088/1742-6596/2245/1/012019.

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Abstract With the increasing scale of integrated circuits, hypergraph partitioning is usually applied to Very Large Scale Integration (VLSI) circuit layout and other applications to reduce the computational complexity. However, if without properly coarsening, the hypergraph partitioning problem will become intractable along with the increase of the number of vertices. In this paper, we propose a coarsening algorithm in k-way hypergraph partitioning based on net clustering, where net clustering is used to obtain the initial set of vertices with higher internal similarity. Due to the property of

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Li, Peng, Shite Zhu, Wei Xi, Changbao Xu, Dandan Zheng, and Kai Huang. "Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS Technology." Applied Sciences 13, no. 6 (2023): 3471. http://dx.doi.org/10.3390/app13063471.

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The threshold voltage distribution technique is an effective way to reduce the static power consumption of integrated circuits. Several gate-level-based distribution algorithms have been proposed, but the optimization effect and run time still need further optimization when applied to very large-scale integration (VLSI) designs. This paper presents a triple-threshold path-based static power optimization methodology (TPSPOM) for low-power system-on-chip. This method obtains the path weights and cell weights from paths’ timing constraints and cells’ delay-to-power ratios, then uses them as index

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Nagabushanam, M., Skandan Srikanth, Rushita Mupalla, Sushmitha S. Kumar, and Swathi K. "Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module." International Journal of Electrical and Electronics Research 10, no. 4 (2022): 1099–106. http://dx.doi.org/10.37391/ijeer.100455.

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The development of Digital Signal Processors (DSPs), graphical systems, Field Programmable Gate Arrays (FPGAs)/ Application-Specific Integrated Circuits (ASICs), and multimedia systems all rely heavily on digital circuits. The need for high-precision fixed-point or floating-point multipliers suitable for Very Large-Scale Integration (VLSI) implementation in high-speed DSP applications is developing rapidly. An integral part of any digital system is the multiplier. In digital systems as well as signal processing, the adder and multiplier seem to be the fundamental arithmetic units. Problems ari

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Wang, Lin, Zhongqiang Luo, and Li Gao. "Stochastic Computing Architectures: Modeling, Optimization, and Applications." Symmetry 16, no. 12 (2024): 1701. https://doi.org/10.3390/sym16121701.

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With the rapid development of artificial intelligence (AI), the design and implementation of very large-scale integrated circuits (VLSI) based on traditional binary computation are facing challenges of high complexity, computational power, and high power consumption. The development of Moore’s law has reached the limit of physical technology, and there is an urgent need to explore new computing architectures to make up for the shortcomings of traditional binary computing. To address the existing problems, Stochastic Computing (SC) is an unconventional stochastic sequence that converts binary n

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Radfar, Mohsen, Kriyang Shah, and Jugdutt Singh. "Recent Subthreshold Design Techniques." Active and Passive Electronic Components 2012 (2012): 1–11. http://dx.doi.org/10.1155/2012/926753.

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Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementat

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Meher, Sukanya S., M. Eren Çelik, Jushya Ravi, Amol Inamdar, and Deepnarayan Gupta. "An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite." Journal of Physics: Conference Series 2776, no. 1 (2024): 012007. http://dx.doi.org/10.1088/1742-6596/2776/1/012007.

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Abstract The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Pa

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