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1
M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M, and Rahul S.G. "Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits." ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.
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High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal error rate. VLSI circuits are designed using the behavioral input and results are measured at running condition. When VLSI circuit’s results get reduced, the language description of the circuit is considered as an input. Then, compilation process convert high level specification into Intermediate Representation (IR) in control/data flow graph (CDFG). CDFG computes data and control dependencies among operations. eXtreme Gradient Boosting (XGBoost) Classifier is exploited in C4.5-XGBCHLS method to classify the error causing functional unit (FU) with minimal error rate. XGBoost Classifier exploited C4.5 decision tree as base classifier to enhance classification of error causing FU in VLSI circuits. After that, FU gets allocated in place of error causing FU from functional library based on the design objectives and PPVTD variations. Finally, operation scheduling and binding process is executed for register transfer level (RTL) generation to form VLSI circuits with improved RA. The simulation results shows that the C4.5-XGBCHLS method enhances the performance of functional unit selection accuracy (FUSA) with minimal error rate (ER) and circuit adaptability time (CAT).
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Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.
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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.
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Madhura, S. "A Review on Low Power VLSI Design Models in Various Circuits." Journal of Electronics and Informatics 4, no. 2 (2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.
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Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the performance improvement of VLSI design and it shows the future directions of the areas that are to be concentrated on VLSI circuit design.
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Yang, Boyu. "Very Large-Scale Integration Circuit and Its Current Status Analysis." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 421–27. http://dx.doi.org/10.54097/hset.v71i.14627.
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The development of Very Large Scale Integration (VLSI) has become very relevant to our lives, and although many of the technologies have matured, scientists are still actively exploring and innovating them. This article is a basic introduction to the composition and advanced technology of large-scale integrated circuits, focusing on transistors and the basic components it consists of, as well as the design of integrated circuits, manufacturing and measurement technology. Very Large Scale Integration Circuit, the transistor is the most basic component of the original, to the low-power CMOS tube is the most widely used, they form a logic gate and storage elements, to achieve a variety of basic functions of the circuit, while the circuit also exists to provide signal distribution and interconnection of the clock network, the optimization of the design of the contemporary research is also a hot spot. In recent years, the progress of the chip can not be separated from the development of new technologies, SOC technology, low-power technology and detection technology plays an important role in the promotion.
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Wölcken, Klaus. "Skill Needs in VLSI Circuits." Industry and Higher Education 6, no. 1 (1992): 50. http://dx.doi.org/10.1177/095042229200600113.
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The forecast need for designers of Very Large Scale Integrated Circuits is described. The article then goes on to outline the support being provided for academic institutions involved with VLSI design training by the European Commission's Directorate General XIII.
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Zolnikov, Vladimir, Konstantin Zolnikov, Nadezhda Ilina, and Kirill Grabovy. "Verification methods for complex-functional blocks in CAD for chips deep submicron design standards." E3S Web of Conferences 376 (2023): 01090. http://dx.doi.org/10.1051/e3sconf/202337601090.
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The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used.
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Rahman, Tasnim Ikra. "Fault Diagnosis Methods in Analog and Mixed Signal Circuits." DIU Journal of Science & Technology 14, no. 1 (2024): 23–27. https://doi.org/10.5281/zenodo.13770923.
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Fault identification of analog and mixed signal circuits is very difficult topics for previous few decades. Localization of hard and soft faults in analog circuit is often a troublesome task without a transparent cut methodology. For manufacturing process of Very Large Scale Integration (VLSI) Application Specific Integrated Circuits (ASICs) both fault diagnosis and localization are mandatory. The importance of such analog test has become important due to enhancement of networking and communication sector. This paper gives a brief review on the faults present in analog circuits and different diagnosis methodologies of these faults. Comparison of detection is also demonstrated among some techniques for some of the ITC97 Benchmark circuits.
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Shur, Michael. "(Invited) Industrial Face of Nanotechnology." ECS Meeting Abstracts MA2023-01, no. 16 (2023): 1452. http://dx.doi.org/10.1149/ma2023-01161452mtgabs.
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Ever since the proposal and demonstration of quantum dots in 1980 by Drs. A. Efros, Al. Efros and A. Ekimov, the relentless progress of nanotechnology has been unstoppable. And nowhere this progress is more evident than in the Si Very Large Scale Integrated Circuits (VLSI) and Thin Film Transistor (TFT) technologies. The minimum feature size of the Si VLSI with up to 2.6 trillion transistors on a chip was reduced to 3 nm in 2022 with plans for the 2 nm technology. TFTs fabricated on glass or even on cloth or paper enable integrated circuits with 50 nm tolerances over square meter sizes. These technologies have become disruptive with applications ranging from 5G and Beyond 5G communications to robotics, driverless cars, and electronic warfare. This talk will focus on the new counter-intuitive physics of ballistic transport required to support the design, characterization, and parameter extraction for nanoscale Si VLSI and TFT integrated circuits. Figure 1
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Boychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky, and Pavel Nekrasov. "Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices." Facta universitatis - series: Electronics and Energetics 28, no. 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.
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Total ionizing dose (TID) effects and radiation tests of complex multifunctional Very-large-scale integration (VLSI) integrated circuits (ICs) rise up some particularities as compared to conventional ?simple? ICs. The main difficulty is to organize informative and quick functional tests directly under irradiation. Functional tests approach specified for complex multifunctional VLSI devices is presented and the basic radiation test procedure is discussed in application to some typical examples.
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Gonsai, Sima K., Kinjal Ravi Sheth, Dhavalkumar N. Patel, et al. "Exploring the synergy: AI and ML in very large scale integration design and manufacturing." Bulletin of Electrical Engineering and Informatics 13, no. 6 (2024): 3993–4001. http://dx.doi.org/10.11591/eei.v13i6.8594.
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With the rapid advancements in very large scale integration (VLSI) and integrated circuit (IC) technology, the complexity of devices has escalated significantly. Designing a VLSI chip is essential for scaling up the capabilities of chips to meet the growing demands of modern applications, like artificial intelligence (AI), IoT, and high-performance computing. Chip testing and verification also emerges as crucial tasks to ensure optimal device functionality. Testing verifies the integrity of a circuit’s gates and connections, ensuring accurate operation. Throughout the chip’s design and development life cycle, design, testing and verification composes a substantial portion of the effort. AI and machine learning (ML) are used in many different research domains to improve predicted accuracy, automate difficult jobs, provide data-driven insights, and optimise workflows. This study aims to showcase the vital role of AI/ML in reducing complexity in VLSI chip design life cycle by automating test pattern generation and fault detection, enhancing efficiency and accuracy, and significantly reducing the time and resources needed for design verification and optimization.
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Shan, Tianchang. "Advancements in VLSI low-power design: Strategies and optimization techniques." Applied and Computational Engineering 41, no. 1 (2024): 22–28. http://dx.doi.org/10.54254/2755-2721/41/20230706.
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As production technology advances, integrated circuits are increasing in size, leading to a corresponding rise in power consumption if not properly optimized. Consequently, the optimization of integrated circuit power consumption has gained paramount significance. This paper provides an overview of the theoretical and research developments in Very Large Scale Integration (VLSI) low-power design. Initially, the paper delves into the components of VLSI power consumption, elucidating the origins of various power consumption types and the factors influencing their magnitude. Subsequently, existing power reduction technologies are examined, including transistor-level optimization, gate-level optimization, and system-level power optimization. The principles, applicable power consumption types, as well as their respective advantages and drawbacks are analysed. The paper also introduces methods for evaluating VLSI power consumption and summarizes the characteristics, advantages, and disadvantages of high-level power estimation and low-level power estimation. Ultimately, it underscores the importance of considering multiple power optimization strategies during VLSI design and discusses research approaches for achieving low power consumption. This comprehensive exploration contributes to the enhancement and optimization of VLSI design efforts.
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Maskowitz, J. V., W. E. Rhoden, D. R. Kitchen, R. E. Omlor, and P. F. Lloyd. "In situ STEM observations of electromigration on thin aluminum stripes." Proceedings, annual meeting, Electron Microscopy Society of America 44 (August 1986): 740–41. http://dx.doi.org/10.1017/s0424820100145078.
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The existence of electromigration in thin films has been acknowledged since the early sixties. Electromigration is described as the main transport for atoms in a conductor under a current stress. Initial interest had been of a theoretical nature as electromigration had little impact on circuit reliability. With the maturing of Very Large Scale Integrated Circuit (VLSI) technology, current densities are exceeding 106 Amps/cm2 while linestripes are reaching into the submicron range. In this environment, electromigration can cause unwanted open or short circuits in thin films. This has serious implications on the reliability of any integrated circuit. By 1990, millions of transistors may be fabricated on a chip with feature sizes smaller than the wavelength of visible light.
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CHEN, JIANLI, and WENXING ZHU. "A PLACEMENT FLOW FOR VERY LARGE-SCALE MIXED-SIZE CIRCUIT PLACEMENT." Journal of Circuits, Systems and Computers 23, no. 02 (2014): 1450016. http://dx.doi.org/10.1142/s0218126614500169.
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The very large-scale integrated circuit (VLSI) placement problem is to determine the exact location of each movable circuit element within a given region. It is a crucial process in physical design, since it affects performance, power consumption, routability, and heat distribution of a design. In this paper, we propose a VLSI placement flow to handle the large-scale mixed-size placement problem. The main idea of our placement flow is using a floorplanning algorithm to guide the placement of circuit elements. It consists of four steps: (1) With the multilevel framework, circuit elements are clustered into blocks by recursively partitioning; (2) a floorplanning algorithm is performed on every level of the blocks; (3) the macro cells are shifted by a macro shifting technique to determine their exact locations; (4) with each macro cell location fixed, a standard cell placement algorithm is applied to place the remaining objects. The proposed approach is tested on the IBM mixed-size benchmarks and the modern mixed-size (MMS) placement benchmarks. Experimental results show that our approach outperforms the state-of-the-art placers on the solution quality for most of the benchmarks.
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B, Harshitha. "An Area and Power Optimization for Level Shifters using 45nm CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 4951–55. http://dx.doi.org/10.22214/ijraset.2024.62674.
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Abstract: Modern integrated circuits require level shifters as essential parts to enable communication between circuits running at various voltage levels. Design-wise, the Level Shifter has a minimal silicon footprint due to its limited component count and operates with minimal power usage, making it well-suited for energy-efficient applications. This work implements CMOS voltage level shifter, also known as conventional CMOS level shifter. The level shifter's overall power and area usage are compared. CMOS level shifters simulations are carried out using CADENCE tool. The simulation's outcomes are implemented in conventional 45-µm CMOS technology. Index Terms: Level shifters, - Very Large-Scale Integrated Circuits (VLSI), level shifter, low power
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Dove, Lewis. "Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS." Journal of Microelectronics and Electronic Packaging 6, no. 1 (2009): 38–41. http://dx.doi.org/10.4071/1551-4897-6.1.38.
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Mixed-signal Application Specific Integrated Circuits (ASICs) have traditionally been used in test and measurement applications for a variety of functions such as data converters, pin electronics circuitry, drivers, and receivers. Over the past several years, the complexity, power density, and bandwidth of these chips has increased dramatically. This has necessitated dramatic changes in the way these chips have been packaged. As the chips have become true VLSI (Very Large Scale Integration) ICs, the number of I/Os have become too large to interconnect with wire bonds. Thus, it has become necessary to utilize flip chip interconnects. Also, the bandwidth of the high-speed signal paths and clocks has increased into the multi Gbit or GHz ranges. This requires the use of packages with good high-frequency performance which are designed using microwave circuit techniques to optimize signal integrity and to minimize signal crosstalk and noise.
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Shakir, Muhammad, Shuoben Hou, Raheleh Hedayati, Bengt Gunnar Malm, Mikael Östling, and Carl-Mikael Zetterling. "Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications." Electronics 8, no. 5 (2019): 496. http://dx.doi.org/10.3390/electronics8050496.
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A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.
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Liu, Fengyuan. "Stochastic Nature of Large-Scale Contact Printed ZnO Nanowires Based Transistors." Stochastic Nature of Large-Scale Contact Printed ZnO Nanowires Based Transistors 35, no. 2 (2024): 2412299. https://doi.org/10.1002/adfm.202412299.
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Printing technology holds great potential for resource-efficient development of electronic devices and circuits. However, even after decades of research, achieving uniformly responding nanowires (NWs) based printed devices is still a challenge. To date, there is no design rule that clearly guides the fabrication of NW ensemble-based field-effect transistors (FETs) and the variables that influence device-level uniformity remain unclear. The lack of fundamental understanding severely limits the large-scale and very large-scale integration (LSI and VLSI). Herein this longstanding issue is addressed with a holistic approach that starts with optimization of the synthesis of ZnO NWs, their printing, and further processing to fabricate transistors with uniform responses (e.g., on-state current, threshold voltage). Monte Carlo simulation based on statistical analysis of printed ZnO NWs is carried out to develop a probabilistic framework that can predict the large-scale performance of FETs. As a proof of concept, inverter circuits have been developed using printed ZnO NWs based FETs. This work provides a valuable toolkit to handle the stochastic nature of FETs based on printed ZnO NW ensemble, which can be used for neuromorphic integrated circuit in the future.
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Rajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics." Journal of Circuits, Systems and Computers 27, no. 13 (2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.
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Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write operation over the previous MFFs. This magnetic-based logic circuit is based on the previous two-in-one (TIO) MTJ cell that presents the aforementioned attributes. Radiation-induced single event upset, as another reliability challenge, is also taken into consideration for the MFFs and another MFF robust against radiation effects is suggested and evaluated.
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Zhang, Jin, Zhenghui Liu, Xiao Hu, Peixin Liu, Zhiling Hu, and Lidan Kuang. "FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs." Electronics 13, no. 9 (2024): 1667. http://dx.doi.org/10.3390/electronics13091667.
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The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.
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Wong, C. P. "Electrical performance and reaction kinetics of silicone gels." Journal of Materials Research 5, no. 4 (1990): 795–800. http://dx.doi.org/10.1557/jmr.1990.0795.
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Silicone gels are becoming more accepted as protective coatings for Very Large Scale Integrated circuits (VLSI) against severe environments due to their excellent electrical, thermal, and mechanical properties. Recent studies indicate that high performance silicone gels in low-cost, non-hermetic plastic packaging may replace conventional hermetic ceramic packaging. This paper describes the use of the soft silicone gels as coatings on Integrated Circuit (IC) devices, and the correlation between the material's cure temperature and cure time versus their adhesion and electrical reliability during 85°C, 85% RH and bias accelerating testing. In addition, the reaction kinetics of the silicone gel based on the Differential Scanning Calorimetry (DSC) study of the uncured sample will be reported.
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M, Pradeep, Udutha Rajender, Pravin Prakash Adivarekar, and Sumit Kumar Gupta. "BALANCING COST AND PERFORMANCE IN VLSI SYSTEMS USING RMSPROP ALGORITHM-ASSISTED DESIGN SPACE EXPLORATION." ICTACT Journal on Microelectronics 9, no. 2 (2023): 1580–84. https://doi.org/10.21917/ijme.2023.0275.
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As Very Large Scale Integration (VLSI) technology advances, the need to efficiently balance cost and performance in VLSI systems becomes paramount. To address this challenge, we propose a novel approach that leverages the RMSPROP algorithm for assisted design space exploration. The RMSPROP algorithm, which has proven effective in the field of deep learning optimization, is adapted to navigate the complex design space of VLSI systems. By integrating RMSPROP into the design space exploration process, we can intelligently search for optimal trade-offs between cost and performance, leading to highly efficient VLSI designs. Our experimental results demonstrate the effectiveness of the RMSPROP algorithm-assisted design space exploration, showcasing significant improvements in cost-performance trade-offs compared to traditional design methodologies. This research opens new avenues for designing VLSI systems with improved efficiency, enabling the realization of high-performance yet cost-effective integrated circuits.
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Pan, Li Yan, and Yan Pei Liu. "An Application of Rectilinear Embedding in VLSI Placement." Advanced Materials Research 734-737 (August 2013): 2842–45. http://dx.doi.org/10.4028/www.scientific.net/amr.734-737.2842.
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The VLSI (Very Large Scale Integrated Circuits) technology has developed rapidly in recent years, with a lot of advanced electric products emerging. Placement layout is regarded as the initial step in VLSI physical design. Its quality has a direct effect on the chip area and performance. The rectilinear embedding, which originates from graph theory, is widely employed in VLSI placement. In this paper, we set up a mathematical model for VLSI. Firstly, the issue of VLSI placement was converted to quadrangulation by using rectilinear embedding. Then we provided generating functions for two types of quadrangulations with graph multiple parameters. And the explicit formulae by employing Lagrangian inversion were obtained. Furthermore, we found the relation between outerplanar graph and Hamilton graph, so the counting result of Hamilton quadrangulation was derived. The quadrangulation calculation can be applied to the establishment of a computerized algorithm, which can be widely used for VLSI placement optimization.
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Siddesh, K. B., S. Roopa, Parveen B. A. Farzana, and T. Tanuja. "Design of duty cycle correction circuit using ASIC implementation for high speed communication." i-manager’s Journal on Electronics Engineering 13, no. 3 (2023): 33. http://dx.doi.org/10.26634/jele.13.3.19969.
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This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cycle. DCC have improved stability, correction range, and operating frequency compared with mixed-signal and all-digital DCCs. In this analysis, the duty cycle correction circuits and their significance in Application Specific Integrated Circuit (ASIC) design, along with typical implementation methods, are discussed.
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Im, James S., and Robert S. Sposili. "Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays." MRS Bulletin 21, no. 3 (1996): 39–48. http://dx.doi.org/10.1557/s0883769400036125.
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The fabrication of thin-film-transistor (TFT) devices on a transparent substrate lies at the heart of active-matrix-liquid-crystal-display (AMLCD) technology. This is both good and bad. On one hand it is a difficult task to manufacture millions of intricate semiconductor devices reliably over such large display substrates. On the positive side, AMLCD technology can aspire to become much more than a “display” technology. The idea is as follows: It is possible for one to readily fabricate additional transistors to execute various electronic functions—those that would otherwise be handled by separate large-scale-integration (LSI) and very large-scale-integration (VLSI) circuits—on the periphery of the display. Since this can be done, in principle, with no—or a minimal number of—additional processing steps, substantial cost reduction is possible and significant value can be added to the final product.Doing so and doing it well can ultimately lead to “system-on-glass” products in which the entire electronic circuitry needed for a product is incorporated directly onto a glass substrate. This means that integrated active-matrix liquid-crystal displays (IAMLCDs) have the potential to bypass conventional Si-wafer-based products and may lead TFT technology to compete directly against Si-wafer-based monolithic integrated circuits.
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Li, Jian, Robert Blewer, and J. W. Mayer. "Copper-Based Metallization for ULSI Applications." MRS Bulletin 18, no. 6 (1993): 18–21. http://dx.doi.org/10.1557/s088376940004728x.
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Multilevel metallization of very large-scale integrated (VLSI) circuits has become an area of intense research interest as devices are scaled down in order to increase circuit density. As device dimensions approach the submicron regime, reliability becomes more of an issue. Metallization generally requires good conductivity, electromigration resistance, controllable contact performance, corrosion resistance, adherence, thermal stability, bondability, ability to be patterned into a desirable geometry, and economic feasibility.Aluminum and its alloys have been commonly used as the main metallization materials because they meet most of the metallization requirements for microelectronic devices. Aluminum, however, suffers from major limitations, such as elec-tromigration and stress-voiding induced open-circuit failure. For the development of ultralarge-scale integration (ULSI) for fast-switching-speed devices, the electrical resistivities of aluminum and its alloys are not low enough. As the minimum geometry is scaled down to one-quarter micron, aluminum and its alloys potentially will be replaced by other materials such as Cu, Au, or superconductors for on-chip interconnection.
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Nagarajan, Sridevi, and Prasanna Kumar Mahadeviah. "On-chip based power estimation for CMOS VLSI circuits using support vector machine." Indonesian Journal of Electrical Engineering and Computer Science 35, no. 2 (2024): 804. http://dx.doi.org/10.11591/ijeecs.v35.i2.pp804-811.
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Power estimation has a major impact on the reliability of very-large-scale integration (VLSI) circuits. As a results power estimation is highly needed in VLSI circuits at the early stages. One of the evident challenges in integrated circuit (IC) industry is development and investigation of techniques for the reduction of design complexity due to the growing process variations and reduction of chip manufacturing turnaround time. Under these conditions, the higher design levels of average power estimation before the chip manufacturing process is highly essential for the calculation of power budget and to take the necessary steps for the reduction of power consumption. Over the years, most of the approaches were designed to estimate the power usage, however, most of the conventional techniques are time consuming, resource-intensive and largely manual. Machine learning techniques have received much attention in many of the engineering applications and are capable for modelling the complex systems through historical data. Hence, in this work on chip-based power estimation for complementary metal-oxide-semiconductor (CMOS) VLSI using support-vector machine (SVM) is presented to estimate the power. The SVM is employed to estimate the usage of power at runtime. The performance of this model is evaluated in terms of Power usage, delay, data accuracy and error rate.
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Sridevi, Nagarajan Prasanna Kumar Mahadeviah. "On-chip based power estimation for CMOS VLSI circuits using support vector machine." Indonesian Journal of Electrical Engineering and Computer Science 35, no. 2 (2024): 804–11. https://doi.org/10.11591/ijeecs.v35.i2.pp804-811.
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Power estimation has a major impact on the reliability of very-large-scale integration (VLSI) circuits. As a results power estimation is highly needed in VLSI circuits at the early stages. One of the evident challenges in integrated circuit (IC) industry is development and investigation of techniques for the reduction of design complexity due to the growing process variations and reduction of chip manufacturing turnaround time. Under these conditions, the higher design levels of average power estimation before the chip manufacturing process is highly essential for the calculation of power budget and to take the necessary steps for the reduction of power consumption. Over the years, most of the approaches were designed to estimate the power usage, however, most of the conventional techniques are time consuming, resource-intensive and largely manual. Machine learning techniques have received much attention in many of the engineering applications and are capable for modelling the complex systems through historical data. Hence, in this work on chip-based power estimation for complementary metal-oxide-semiconductor (CMOS) VLSI using support-vector machine (SVM) is presented to estimate the power. The SVM is employed to estimate the usage of power at runtime. The performance of this model is evaluated in terms of Power usage, delay, data accuracy and error rate.
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Dayanand, Swathi, R. Varshitha K, Rohini T, Yasha Jyothi M. Shirur, and Jyoti R. Munavalli. "Low Power High Speed Vedic Techniques in Recent VLSI Design – A Survey." Perspectives in Communication, Embedded-systems and Signal-processing - PiCES 4, no. 6 (2020): 147–56. https://doi.org/10.5281/zenodo.4247825.
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Advancement in the Artificial Intelligence (AI) and Machine Learning (ML) has influenced complex designs to be integrated in Very Large-Scale Integration (VLSI) Design. Designers are concentrating on high speed and low power techniques to facilitate the needs of the technology requirements. In multiple AI applications, Digital Signal Processor is the building block, optimization of it may solve the issues related to computation of the data signal at faster rate consuming less power using Vedic mathematics. In this paper, a detailed review is made on recent applications of Vedic Mathematics in the domain of VLSI to yield novel design, efficient architecture for Squarer, Multiplier, Arithmetic unit, Cubic and divider circuits along with their crucial performance criteria. It is deduced that the use of Vedic Sutras in formulating algorithms for digital logic circuit design has led to simplified architecture and yielded higher speed, low power consumption and enhanced efficiency of operation.
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MOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (2021): 505–11. http://dx.doi.org/10.6036/10214.
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Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;
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Oliver Ava, Muhammad Oscar, and Tommy George. "The Impact and Prevention of Latch-up in CMOS in VLSI Design." Fusion of Multidisciplinary Research, An International Journal 1, no. 01 (2020): 1–13. https://doi.org/10.63995/vgrd5263.
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Latch-up in CMOS (Complementary Metal-Oxide-Semiconductor) technology is a significant reliability concern in VLSI (Very Large Scale Integration) design. Latch-up is a parasitic, unintended creation of a low-impedance path between the power supply rails due to the triggering of parasitic thyristor structures inherent in CMOS processes. This phenomenon can lead to device malfunction, excessive current flow, and potential permanent damage to the integrated circuit. The impact of latch-up is profound, as it compromises the stability and functionality of electronic systems, especially in high-performance and high-reliability applications such as aerospace, medical devices, and critical infrastructure. The primary factors contributing to latch-up include high current spikes, radiation exposure, and improper circuit layout. Preventive measures are essential to mitigate these risks and ensure the robustness of CMOS circuits. Effective prevention strategies include the use of guard rings, which isolate the sensitive regions of the chip and prevent the formation of parasitic paths. Proper substrate doping and well design can also minimize latch-up susceptibility. Additionally, optimizing the layout design to minimize the proximity of p-n junctions and employing advanced CMOS processes with latch-up resistant technologies are crucial. This abstract highlights the importance of understanding and preventing latch-up in CMOS VLSI design to enhance the reliability and performance of modern integrated circuits.
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Horiuchi, Timothy K., and Christof Koch. "Analog VLSI-Based Modeling of the Primate Oculomotor System." Neural Computation 11, no. 1 (1999): 243–65. http://dx.doi.org/10.1162/089976699300016908.
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One way to understand a neurobiological system is by building a simulacrum that replicates its behavior in real time using similar constraints. Analog very large-scale integrated (VLSI) electronic circuit technology provides such an enabling technology. We here describe a neuromorphic system that is part of a long-term effort to understand the primate oculomotor system. It requires both fast sensory processing and fast motor control to interact with the world. A one-dimensional hardware model of the primate eye has been built that simulates the physical dynamics of the biological system. It is driven by two different analog VLSI chips, one mimicking cortical visual processing for target selection and tracking and another modeling brain stem circuits that drive the eye muscles. Our oculomotor plant demonstrates both smooth pursuit movements, driven by a retinal velocity error signal, and saccadic eye movements, controlled by retinal position error, and can reproduce several behavioral, stimulation, lesion, and adaptation experiments performed on primates.
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Mishra, Prateek. "Exploring Diverse Approaches in VLSI Design Methodologies." International Journal of Multidisciplinary Research in Science, Engineering and Technology 6, no. 05 (2023): 391–94. http://dx.doi.org/10.15680/ijmrset.2023.0605056.
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The field of Very-Large-Scale Integration (VLSI) design has witnessed significant evolution, driven by advances in technology and the increasing complexity of integrated circuits. This paper provides a comprehensive examination of various methodologies employed in VLSI design, aiming to shed light on their unique advantages, limitations, and applications. We categorize the methodologies into traditional, contemporary, and emerging approaches, including Full Custom Design, Standard Cell Design, and ASIC/FPGA-based design strategies. Through comparative analysis, we explore how each approach addresses key design challenges such as scalability, power efficiency, and design flexibility. The paper also discusses the impact of automated tools and software innovations on the efficiency of VLSI design processes. By highlighting case studies and practical examples, we illustrate the effectiveness of these methodologies in real-world scenarios. This study serves as a valuable resource for both practitioners and researchers, offering insights into selecting the most suitable VLSI methodology based on specific project requirements and constraints.
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Sun, Ben. "Interpretable machine learning in VLSI physical design." Applied and Computational Engineering 4, no. 1 (2023): 13–19. http://dx.doi.org/10.54254/2755-2721/4/20230338.
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Today's popularisation of portable devices largely depends on the progress in integrated circuits. Modern Very Large Scale Integration technology (VLSI) allows billions of transistors to be packed into the same chip. In the past years, digital design in VLSI has been developed compared to analogue design. The traditional method is hard to model the performance change in analogue or mixed-signal components caused by physical design. In the early 2000s, rapid advances in machine learning and computing power made analogue design automation possible. Despite their outstanding performance, the transparency issue has become significant. This paper introduces the history of VLSI physical design, which includes placement and routing in the early stages. The change that machine learning (ML) has made is mentioned in the third section. Analysis of the potential problem has been proposed, followed by a brief category of some well-known work in interpretable Machine Learning, which could be the primary direction for VLSI automation to be further popularised in the future.
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IKEDA, SHOJI, HIDEO SATO, MICHIHIKO YAMANOUCHI, et al. "RECENT PROGRESS OF PERPENDICULAR ANISOTROPY MAGNETIC TUNNEL JUNCTIONS FOR NONVOLATILE VLSI." SPIN 02, no. 03 (2012): 1240003. http://dx.doi.org/10.1142/s2010324712400036.
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We review recent developments in magnetic tunnel junctions with perpendicular easy axis (p-MTJs) for nonvolatile very large scale integrated circuits (VLSIs). So far, a number of material systems such as rare-earth/transition metal alloys, L10-ordered ( Co, Fe )– Pt alloys, Co /( Pd, Pt ) multilayers, and ferromagnetic-alloy/oxide stacks have been proposed as electrodes in p-MTJs. Among them, p-MTJs with single or double ferromagnetic-alloy/oxide stacks, particularly CoFeB–MgO , were shown to have high potential to satisfy major requirements for integration.
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Diéguez, Ángel, Joan Canals, Sergio Moreno, and Anna Vilà. "Gamification for Teaching Integrated Circuit Processing in an Introductory VLSI Design Course." Education Sciences 14, no. 8 (2024): 921. http://dx.doi.org/10.3390/educsci14080921.
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Gamification is being incorporated into university classrooms due to its educational benefits for students learning, including encouraging student behavior and engagement, and consequently improving learning outcomes. Despite gamification being increasingly used in education, little has been developed related to Very-Large-Scale Integration (VLSI). In this article, we describe two different gamification experiences applied to integrated circuit processing and design in an introductory VLSI design course for Electronic Engineers. While gamification in universities is still not very mature and our experience spans only two academic years, we observed that, with the practice of gamifying part of our course, the topics treated in games were profoundly learned and the experience was very positive in every aspect of the teaching–learning process.
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Cheung, R., and P. Argyrakis. "Microscale sensors based on silicon carbide and silicon." Proceedings of the Institution of Mechanical Engineers, Part C: Journal of Mechanical Engineering Science 222, no. 1 (2008): 19–26. http://dx.doi.org/10.1243/09544062jmes663.
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The current paper consists of two topics related to microelectromechanical systems (MEMS). The first topic reviews recent advances made in the area of silicon carbide (SiC) MEMS for applications in harsh environments. Given the unique properties of SiC, the potential and progress in the development and deployment of the harsh environment material for the fabrication and characterization of resonators and pressure sensors are described. The second topic details the motivation behind the study of biologically inspired systems and how silicon-based microscale sensors with out-of-plane structures could be integrated with analogue very-large-scale integrated circuits (VLSI) for insect-inspired robotic studies.
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Wong, C. P. "An Overview of Integrated Circuit Device Encapsulants." Journal of Electronic Packaging 111, no. 2 (1989): 97–107. http://dx.doi.org/10.1115/1.3226528.
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The rapid development of integrated circuit technology from small-scale integration (SSI) to very large scale integration (VLSI) has had great technological and economical impact on the electronics industry. The exponential growth of the number of components per IC chip, the exponential decrease of device dimensions, and the steady increase in IC chip size have imposed stringent requirements, not only on the IC physical design and fabrication, but also on IC encapsulants. This report addresses the purpose of encapsulation, encapsulation techniques, and a general overview of the application of inorganic and organic polymer materials as electronic device encapsulants.
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Beck, Anthony, Franziska Obst, Mathias Busek, et al. "Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration." Micromachines 11, no. 5 (2020): 479. http://dx.doi.org/10.3390/mi11050479.
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The interest in large-scale integrated (LSI) microfluidic systems that perform high-throughput biological and chemical laboratory investigations on a single chip is steadily growing. Such highly integrated Labs-on-a-Chip (LoC) provide fast analysis, high functionality, outstanding reproducibility at low cost per sample, and small demand of reagents. One LoC platform technology capable of LSI relies on specific intrinsically active polymers, the so-called stimuli-responsive hydrogels. Analogous to microelectronics, the active components of the chips can be realized by photolithographic micro-patterning of functional layers. The miniaturization potential and the integration degree of the microfluidic circuits depend on the capability of the photolithographic process to pattern hydrogel layers with high resolution, and they typically require expensive cleanroom equipment. Here, we propose, compare, and discuss a cost-efficient do-it-yourself (DIY) photolithographic set-up suitable to micro-pattern hydrogel-layers with a resolution as needed for very large-scale integrated (VLSI) microfluidics. The achievable structure dimensions are in the lower micrometer scale, down to a feature size of 20 µm with aspect ratios of 1:5 and maximum integration densities of 20,000 hydrogel patterns per cm². Furthermore, we demonstrate the effects of miniaturization on the efficiency of a hydrogel-based microreactor system by increasing the surface area to volume (SA:V) ratio of integrated bioactive hydrogels. We then determine and discuss a correlation between ultraviolet (UV) exposure time, cross-linking density of polymers, and the degree of immobilization of bioactive components.
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Katircioglu, Haluk, JohnA De Beule, Debaditya Mukherjee, and GaryC Whitlock. "4932028 Error log system for self-testing in very large scale integrated circuit (VLSI) units." Microelectronics Reliability 31, no. 2-3 (1991): viii. http://dx.doi.org/10.1016/0026-2714(91)90267-b.
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Sun, Chongjun, and Chao Ding. "Study on Calibration Method for Testing During Burn In equipment of integrated circuits." Journal of Physics: Conference Series 2029, no. 1 (2021): 012035. http://dx.doi.org/10.1088/1742-6596/2029/1/012035.
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Abstract In order to implement Method 1015 of GJB 548B, TDBI(Testing During Burn In) technology of integrated circuit is widely used in the aging process of core VLSI(Very Large Scale Integration) which is included of FPGA, DSP, CPU and dedicated chips. Many models of TDBI equipment at home or abroad have been come into use. It is an important task to calibrate TDBI equipment in system level and ensure the traceability of its measurement value. At present, the calibration device of TDBI equipment has been successfully finalized and put into production, which has the advantages of convenient use and high cost performance. This paper mainly introduces the calibration method for TDBI equipment of integrated circuit from the aspects of the overall architecture design, signal adaptation design and calibration software design.
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Solanki, Saurabh. "Low-Power VLSI Design for Next-Gen IoT Devices." International Journal of Research in Modern Engineering & Emerging Technology 10, no. 5 (2022): 9–16. https://doi.org/10.63345/ijrmeet.org.v10.i5.2.
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The advancement of the Internet of Things (IoT) is heavily reliant on the design of efficient, low-power integrated circuits that can support a wide range of IoT applications. Low-power Very-Large-Scale Integration (VLSI) design has emerged as a critical factor in extending battery life and reducing energy consumption for next-generation IoT devices. This manuscript explores recent trends and methodologies in low-power VLSI design specifically tailored for IoT devices. It covers key design techniques, from voltage scaling and power gating to clock gating, and discusses the impact of technology scaling on power consumption. The rapid expansion of the Internet of Things (IoT) has placed significant pressure on the design of energy-efficient electronic components, especially in the context of embedded systems that require long-lasting battery life. Low-power Very-Large-Scale Integration (VLSI) design has become indispensable for these systems, providing the foundational technology to enhance both performance and energy efficiency in next-generation IoT devices. This manuscript explores the application of low-power VLSI design techniques specifically aimed at reducing power consumption in IoT devices without compromising computational efficiency. Key techniques such as dynamic voltage and frequency scaling (DVFS), clock gating, power gating, and subthreshold operation are discussed in detail. Furthermore, the impact of advanced semiconductor technologies, such as the 7nm and 5nm process nodes, on reducing power consumption while maintaining performance standards is examined. Moreover, a comprehensive approach to simulation methodologies and the results of recent advancements are presented. The manuscript also includes a statistical analysis of power consumption across various VLSI techniques. The findings provide insights into how these designs can influence future IoT devices’ performance and sustainability.
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Zhang, Ai Rong. "The Integration on Electrical Control Systems Based on Optimized Method." Advanced Materials Research 490-495 (March 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.
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Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity and reuse difficulty. This is true even with programmable logic device (PLD) solutions. Conception aid developer (CAD) combined with hardware description languages (HDL) and VLSI design methodology have accelerated conception and reuse. Nevertheless, the main problem of integrated circuit design is to define the hardware architecture; this is particularly true for heterogeneous algorithm structures such as electrical controls.
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S., Jothilakshmi, Manikanda Kumaran T., and Rekha S. "Controlling factors affecting the stability and rate of electroless copper plating." Journal of Indian Chemical Society Vol. 96, Jan 2019 (2019): 153–57. https://doi.org/10.5281/zenodo.5653450.
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Research and Development, Bharathiar University, Coimbatore-641 046, Tamilnadu, India <em>E-mail</em>: rekhaperichiappan@gmail.com Department of Chemistry, R.M.D. Engineering College, Kavaraipettai-601 206, Tamilnadu, India <em>Manuscript received online 30 August 2018, accepted 10 October 2018</em> The main purpose of this article is to focus on the electroless copper deposition from EDTA bath which is used in printed circuit boards (PCB) and very large scale integrated circuits (VLSI). The effect of the bath operating conditions and bath additives on plating rate, bath stability and morphology of the coating has been studied. It has been found that the organic additive does not stabilize the bath but enhances the plating rate. The additives were found to modify the structure of the deposits with the production of small grain size, dense and tightly adherent copper deposit
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Ahmad, Afaq, Sabir Hussain, M. A. Raheem, Ahmed Al Maashri, Sayyid Samir Al Busaidi, and Medhat Awadalla. "ASIC vs FPGA based Implementations of Built-In Self-Test." International Journal of Advanced Natural Sciences and Engineering Researches 7, no. 6 (2023): 14–20. http://dx.doi.org/10.59287/ijanser.942.
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Linear Feedback Shift Registers (LFSRs) are play key role in testing of for Very Large Scale Integration (VLSI) Integrated Circuits (ICs) testing. Due to tremendous IC complex growth, testing of recent VLSI ICs technology have become more complicated. This led to develop a popular alternate viable solution in the form of Built-In Self-Test (BIST) technology as compared to Automatic Test Equipment (ATE). However, the challenges of BIST technology remain the subject of research. Furthermore, implementation of BIST’s LFSR on Application Specific Integrated Circuit (ASIC) versus Field Programmable Gate Array on (FPGA) platform is current area of research especially in context to power consumption. Hence, to make an informed choice between ASIC and FPGA for implementing BIST’s LFSR we focus on study of design of reconfigurable LFSR on ASIC versus FPGA platform. The Electronic Design Automation (EDA) tool, Cadence is used for implementing BIST’s LFSR on ASIC platform. Whereas, Hardware Description Language (HDL), Verilog is used to implement BIST’s LFSR on FPGA platform. During experimental methodology, maximum frequency, the critical path delay is investigated to assess the power dissipation. The functional and timing simulation models are used to verify the implemented reconfigurable BIST’s LFSR designs. The obtained results show that the performance, in terms of speed and power, of ASIC implementation is far better than traditional FPGA implementation.
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Luo, Guozheng, Xiang Chen, and Shanshan Nong. "Net Clusting Based Low Complexity Coarsening Algorithm In k-way Hypergraph Partitioning." Journal of Physics: Conference Series 2245, no. 1 (2022): 012019. http://dx.doi.org/10.1088/1742-6596/2245/1/012019.
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Abstract With the increasing scale of integrated circuits, hypergraph partitioning is usually applied to Very Large Scale Integration (VLSI) circuit layout and other applications to reduce the computational complexity. However, if without properly coarsening, the hypergraph partitioning problem will become intractable along with the increase of the number of vertices. In this paper, we propose a coarsening algorithm in k-way hypergraph partitioning based on net clustering, where net clustering is used to obtain the initial set of vertices with higher internal similarity. Due to the property of nets connecting through vertices, the proposal can cluster the net by local search and discard unimportant vertices from net clusters to achieve high-quality solutions. The experimental results show that our proposal achieves a high quality of coarsening with lower complexity. Even as the number of partitions rises, the computation time reduction will obviously increase. In the case of setting the number of partitions as 8, our algorithm can achieve almost the same partitioning quality as traditional hMetis, but with a time consumption reduction of 50%.
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Li, Peng, Shite Zhu, Wei Xi, Changbao Xu, Dandan Zheng, and Kai Huang. "Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS Technology." Applied Sciences 13, no. 6 (2023): 3471. http://dx.doi.org/10.3390/app13063471.
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The threshold voltage distribution technique is an effective way to reduce the static power consumption of integrated circuits. Several gate-level-based distribution algorithms have been proposed, but the optimization effect and run time still need further optimization when applied to very large-scale integration (VLSI) designs. This paper presents a triple-threshold path-based static power optimization methodology (TPSPOM) for low-power system-on-chip. This method obtains the path weights and cell weights from paths’ timing constraints and cells’ delay-to-power ratios, then uses them as indexes to distribute each cell to low-threshold voltage (LVT), standard-threshold voltage (SVT), or high-threshold voltage (HVT). The experimental results based on a 28 nm circuit containing 385,781 cells show that the TPSPOM method reduces static power consumption by 15.16% more than the critical-path aware power consumption optimization methodology (CAPCOM). At the same time, run time is reduced by 96.85%.
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Nagabushanam, M., Skandan Srikanth, Rushita Mupalla, Sushmitha S. Kumar, and Swathi K. "Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module." International Journal of Electrical and Electronics Research 10, no. 4 (2022): 1099–106. http://dx.doi.org/10.37391/ijeer.100455.
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The development of Digital Signal Processors (DSPs), graphical systems, Field Programmable Gate Arrays (FPGAs)/ Application-Specific Integrated Circuits (ASICs), and multimedia systems all rely heavily on digital circuits. The need for high-precision fixed-point or floating-point multipliers suitable for Very Large-Scale Integration (VLSI) implementation in high-speed DSP applications is developing rapidly. An integral part of any digital system is the multiplier. In digital systems as well as signal processing, the adder and multiplier seem to be the fundamental arithmetic units. Problems arise when using a multiplier in the realms of area, power, complexity, and speed. This paper details a more efficient MAC (Multiply- Accumulate) multiplier that has been tuned for space usage. The proposed design is more efficient, takes up less room, and has lower latency than conventional designs. The performance of the Additive Multiply Module (AMM) multiplier is measured against that of existing multipliers, where it serves as a module in the MAC reducing area and delay.
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Wang, Lin, Zhongqiang Luo, and Li Gao. "Stochastic Computing Architectures: Modeling, Optimization, and Applications." Symmetry 16, no. 12 (2024): 1701. https://doi.org/10.3390/sym16121701.
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With the rapid development of artificial intelligence (AI), the design and implementation of very large-scale integrated circuits (VLSI) based on traditional binary computation are facing challenges of high complexity, computational power, and high power consumption. The development of Moore’s law has reached the limit of physical technology, and there is an urgent need to explore new computing architectures to make up for the shortcomings of traditional binary computing. To address the existing problems, Stochastic Computing (SC) is an unconventional stochastic sequence that converts binary numbers into a coded stream of digital pulses. It has a remarkable symmetry with binary computation. It uses logic gate circuits in the probabilistic domain to implement complex arithmetic operations at the expense of computational accuracy and time. It has low power and logic resource consumption and a small circuit area. This paper analyzes the basic concepts and development history of SC and neural networks (NNs), summarizes the development progress of SC with NN at home and abroad, and discusses the development trend of SC and the future challenges and prospects of NN. Through systematic summarization, this paper provides new learning ideas and research directions for developing AI chips.
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Radfar, Mohsen, Kriyang Shah, and Jugdutt Singh. "Recent Subthreshold Design Techniques." Active and Passive Electronic Components 2012 (2012): 1–11. http://dx.doi.org/10.1155/2012/926753.
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Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.
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Meher, Sukanya S., M. Eren Çelik, Jushya Ravi, Amol Inamdar, and Deepnarayan Gupta. "An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite." Journal of Physics: Conference Series 2776, no. 1 (2024): 012007. http://dx.doi.org/10.1088/1742-6596/2776/1/012007.
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Abstract The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Parametron (AQFP) logic families. This paper presents a passive transmission line (PTL) based standard cell library for SFQ logic, designed with Synopsys Electronic Design Automation (EDA) software tools for MIT-LL 100μA/μm2 SFQ5ee fab node. The dual RSFQ/ERSFQ standard cell library facilitates seamless integration of SFQ RTL-to-GDS design flow with Synopsys Fusion Compiler, an automated design tool. The SFQ RTL-to-GDS flow entails logic synthesis, checking, placement, clock synthesis, and routing. Row-based placement for library cells and H-tree clock tree structures are employed. Fusion Compiler’s effectiveness is validated with Hypres designs such as finite impulse response (FIR) filters, scalable multiply-accumulate (MAC) units, and memory arrays, comparing single and dual clocking schemes. The synergy between Hypres and Synopsys achieves a milestone by demonstrating the design of a digital superconducting circuit with over 10 million JJs, facilitated by a fully automated design tool for the first time. Challenges in very large-scale SFQ scaling are also discussed.