Relevant bibliographies by topics / Very Large-Scale Integrated (VLSI) design

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Very Large-Scale Integrated (VLSI) design'

Author: Grafiati
Published: 4 June 2021
Last updated: 3 February 2022

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Journal articles on the topic "Very Large-Scale Integrated (VLSI) design"

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MOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (2021): 505–11. http://dx.doi.org/10.6036/10214.

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Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;
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CHEN, JIANLI, and WENXING ZHU. "A PLACEMENT FLOW FOR VERY LARGE-SCALE MIXED-SIZE CIRCUIT PLACEMENT." Journal of Circuits, Systems and Computers 23, no. 02 (2014): 1450016. http://dx.doi.org/10.1142/s0218126614500169.

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The very large-scale integrated circuit (VLSI) placement problem is to determine the exact location of each movable circuit element within a given region. It is a crucial process in physical design, since it affects performance, power consumption, routability, and heat distribution of a design. In this paper, we propose a VLSI placement flow to handle the large-scale mixed-size placement problem. The main idea of our placement flow is using a floorplanning algorithm to guide the placement of circuit elements. It consists of four steps: (1) With the multilevel framework, circuit elements are clustered into blocks by recursively partitioning; (2) a floorplanning algorithm is performed on every level of the blocks; (3) the macro cells are shifted by a macro shifting technique to determine their exact locations; (4) with each macro cell location fixed, a standard cell placement algorithm is applied to place the remaining objects. The proposed approach is tested on the IBM mixed-size benchmarks and the modern mixed-size (MMS) placement benchmarks. Experimental results show that our approach outperforms the state-of-the-art placers on the solution quality for most of the benchmarks.
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Wölcken, Klaus. "Skill Needs in VLSI Circuits." Industry and Higher Education 6, no. 1 (1992): 50. http://dx.doi.org/10.1177/095042229200600113.

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The forecast need for designers of Very Large Scale Integrated Circuits is described. The article then goes on to outline the support being provided for academic institutions involved with VLSI design training by the European Commission's Directorate General XIII.
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Zabidi, Nurulnajah Mohd, and Ab Al-Hadi Ab Rahman. "VLSI Design of a Fast Pipelined 8x8 Discrete Cosine Transform." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 3 (2017): 1430. http://dx.doi.org/10.11591/ijece.v7i3.pp1430-1435.

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This paper presents a Very Large Scale Integrated (VLSI) design and implementation of a fixed-point 8x8 multiplierless Discrete Cosine Transform (DCT) using the ISO/IEC 23002-2 algorithm. The standard DCT algorithm, which is mainly used in image and video compression technology, consists of only adders, subtractors, and shifters, therefore making it efficient for hardware implementation. The VLSI implementation of the algorithm given in this paper further enhances the performance of the transform unit. Furthermore, circuit pipelining has been applied to the base design of the DCT, which significantly improves the performance by reducing the longest path in the non-pipeline design. The DCT has been implemented using semi-custom VLSI design methodology using the TSMC 0.13um process technology. Results show that our DCT designs can run up to around 1.7 Giga pixels/s, which is well above the timing required for real-time ultra-high definition 8K video.
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Wong, C. P. "An Overview of Integrated Circuit Device Encapsulants." Journal of Electronic Packaging 111, no. 2 (1989): 97–107. http://dx.doi.org/10.1115/1.3226528.

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The rapid development of integrated circuit technology from small-scale integration (SSI) to very large scale integration (VLSI) has had great technological and economical impact on the electronics industry. The exponential growth of the number of components per IC chip, the exponential decrease of device dimensions, and the steady increase in IC chip size have imposed stringent requirements, not only on the IC physical design and fabrication, but also on IC encapsulants. This report addresses the purpose of encapsulation, encapsulation techniques, and a general overview of the application of inorganic and organic polymer materials as electronic device encapsulants.
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Zhang, Ai Rong. "The Integration on Electrical Control Systems Based on Optimized Method." Advanced Materials Research 490-495 (March 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.

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Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity and reuse difficulty. This is true even with programmable logic device (PLD) solutions. Conception aid developer (CAD) combined with hardware description languages (HDL) and VLSI design methodology have accelerated conception and reuse. Nevertheless, the main problem of integrated circuit design is to define the hardware architecture; this is particularly true for heterogeneous algorithm structures such as electrical controls.
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Suresh, N., K. Subba Rao, and R. Vassoudevan. "Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques." Journal of Computational and Theoretical Nanoscience 17, no. 4 (2020): 1595–99. http://dx.doi.org/10.1166/jctn.2020.8407.

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Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.
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Pan, Li Yan, and Yan Pei Liu. "An Application of Rectilinear Embedding in VLSI Placement." Advanced Materials Research 734-737 (August 2013): 2842–45. http://dx.doi.org/10.4028/www.scientific.net/amr.734-737.2842.

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The VLSI (Very Large Scale Integrated Circuits) technology has developed rapidly in recent years, with a lot of advanced electric products emerging. Placement layout is regarded as the initial step in VLSI physical design. Its quality has a direct effect on the chip area and performance. The rectilinear embedding, which originates from graph theory, is widely employed in VLSI placement. In this paper, we set up a mathematical model for VLSI. Firstly, the issue of VLSI placement was converted to quadrangulation by using rectilinear embedding. Then we provided generating functions for two types of quadrangulations with graph multiple parameters. And the explicit formulae by employing Lagrangian inversion were obtained. Furthermore, we found the relation between outerplanar graph and Hamilton graph, so the counting result of Hamilton quadrangulation was derived. The quadrangulation calculation can be applied to the establishment of a computerized algorithm, which can be widely used for VLSI placement optimization.
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Radfar, Mohsen, Kriyang Shah, and Jugdutt Singh. "Recent Subthreshold Design Techniques." Active and Passive Electronic Components 2012 (2012): 1–11. http://dx.doi.org/10.1155/2012/926753.

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Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.
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Dhiraj, Dhiraj, Seema Verma, Rajesh Kumar, and Himanshu Choudhary. "A enhanced algorithm for floorplan design using evolutionary technique." Artificial Intelligence Research 1, no. 2 (2012): 38. http://dx.doi.org/10.5430/air.v1n2p38.

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Floor planning is an important problem in very large scale integrated-circuit (VLSI) design automation domain as it evaluates the performance, size, yield and reliability of ICs. Due to rapid increase in number of components on a chip, floor planning has gained its importance further in determining the quality of the design achieved. In this paper we have devised an approach for placement of modules in a given area with bounding constraints in terms of minimum placement area imposed. We have used Modified Genetic Algorithm (MGA) technique for determining and obtaining an optimal placement using an iterative approach.
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Dissertations / Theses on the topic "Very Large-Scale Integrated (VLSI) design"

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Al-Mahmood, Saiyid Jami Islah Ahmad. "A distributed design rule checker for VLSI layouts." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-11012008-063423/.

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高雲龍 and Wan-lung Ko. "A new optimization model for VLSI placement." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B29812938.

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Chu, Chung-kwan, and 朱頌君. "Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B38719551.

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Chen, Ing-yi 1962. "Efficient reconfiguration by degradation in defect-tolerant VLSI arrays." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277195.

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This thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI array consists of identical cells such as memory cells or processors. In contrast to the redundancy approach in which some cells are dedicated as spares, all the cells in the degradation approach are treated in a uniform way. Each cell can be either fault-free or defective and a subarray which contains no faulty cell is derived under constraints of switching and routing mechanisms. Although extensive literatures exist concerning spare allocation and reconfiguration in arrays with redundancy, little research has been published on optimal reconfiguration in a degradable array. A systematic method based on graph theoretic models is developed to deal with the problem. The complexities of reconfiguration are analyzed for schemes using different switching mechanisms. Efficient heuristic algorithms are presented to determine a target subarray from the defective host array.
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Dickinson, Alex. "Complexity management and modelling of VLSI systems." Title page, contents and abstract only, 1988. http://web4.library.adelaide.edu.au/theses/09PH/09phd553.pdf.

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Koelmans, Albertus Maria. "STRICT : a language and tool set for the design of very large scale integrated circuits." Thesis, University of Newcastle Upon Tyne, 1996. http://hdl.handle.net/10443/2076.

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An essential requirement for the design of large VLSI circuits is a design methodology which would allow the designer to overcome the complexity and correctness issues associated with the building of such circuits. We propose that many of the problems of the design of large circuits can be solved by using a formal design notation based upon the functional programming paradigm, that embodies design concepts that have been used extensively as the framework for software construction. The design notation should permit parallel, sequential, and recursive decompositions of a design into smaller components, and it should allow large circuits to be constructed from simpler circuits that can be embedded in a design in a modular fashion. Consistency checking should be provided as early as possible in a design. Such a methodology would structure the design of a circuit in much the same way that procedures, classes, and control structures may be used to structure large software systems. However, such a design notation must be supported by tools which automatically check the consistency of the design, if the methodology is to be practical. In principle, the methodology should impose constraints upon circuit design to reduce errors and provide' correctness by construction' . It should be possible to generate efficient and correct circuits, by providing a route to a large variety of design tools commonly found in design systems: simulators, automatic placement and routing tools, module generators, schematic capture tools, and formal verification and synthesis tools.
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袁志勤 and Chi-kan Yuen. "A double-track greedy algorithm for VLSI channel routing." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1997. http://hub.hku.hk/bib/B31220241.

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Boudreault, Yves 1959. "Design of a VLSI convolver for a robot vision system." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65342.

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Whipple, Thomas Driggs 1961. "Design and implementation of an integrated VLSI packaging support software environment." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277105.

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An interactive software shell has been developed which integrates several packaging simulation tools developed at the University of Arizona which are used to analyze electro-magnetic coupling between interconnects in an integrated circuit. This software shell uses experimental frames to manage this simulation process. Through the experimental frames, the model descriptions and the model inputs are separated, and input data is verified for correctness. This model/input separation allows several model variations to be tested based on several input variations. The results of these simulations are then analyzed and displayed graphically. Further work for the software shell is discussed. This tool provides a user-friendly, efficient method for performing coupled-line analyses in interconnect systems.
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Chabbi, Charef. "VLSI NMOS hardware design of a linear phase FIR low pass digital filter." Ohio University / OhioLINK, 1985. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183749814.

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Books on the topic "Very Large-Scale Integrated (VLSI) design"

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VLSI design. CRC Press, 2001.

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IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration (1987 Vancouver, Canada). VLSI 87: VLSI design of digital systems. North-Holland, 1988.

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1959-, Dündar Günhan, and Öğrenci A. Selçuk, eds. Analog VLSI design automation. CRC Press, 2003.

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Tsui, Frank F. LSI/VLSI testability design. McGraw-Hill, 1987.

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VLSI digital signal processing systems: Design and implementation. Wiley, 1999.

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Churiwala, Sanjay. Principles of VLSI RTL design: A practical guide. Springer, 2011.

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Rino, Micheloni, and Novosel David, eds. VLSI-design of non-volatile memories. Springer, 2005.

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Modern VLSI design: A systems approach. Prentice-Hall International, 1994.

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R, Coelho David, ed. Multi-level simulation for VLSI design. Kluwer Academic Publishers, 1987.

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V, Kachan I., ed. Self-testing VLSI design. Elsevier, 1993.

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Book chapters on the topic "Very Large-Scale Integrated (VLSI) design"

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Pop, Paul, Wajid Hassan Minhass, and Jan Madsen. "Allocation and Schematic Design." In Microfluidic Very Large Scale Integration (VLSI). Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29599-2_8.

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Pop, Paul, Wajid Hassan Minhass, and Jan Madsen. "Testing and Fault-Tolerant Design." In Microfluidic Very Large Scale Integration (VLSI). Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29599-2_11.

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Pop, Paul, Wajid Hassan Minhass, and Jan Madsen. "Design Methodology for Flow-Based Microfluidic Biochips." In Microfluidic Very Large Scale Integration (VLSI). Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29599-2_2.

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MOHSEN, AMR, SAI WAI FU, and CARL SIMONSEN. "Fundamental Principles of Very Large Scale Integrated Circuit Design." In Vlsi Handbook. Elsevier, 1985. http://dx.doi.org/10.1016/b978-0-12-234100-7.50008-3.

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Zaidi, Muhaned, Ian Grout, and Abu Khari A’ain. "Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices." In Very-Large-Scale Integration. InTech, 2018. http://dx.doi.org/10.5772/intechopen.68815.

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Rodríguez-Tastets, M. Andrea. "Consistency in Spatial Databases." In Encyclopedia of Database Technologies and Applications. IGI Global, 2005. http://dx.doi.org/10.4018/978-1-59140-560-3.ch016.

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During the past several years, traditional databases have been enhanced to include spatially referenced data. Spatial database management (SDBM) systems aim at providing models for the efficient manipulation of data related to space. Such type of manipulation is useful for any type of applications based on large spatial data sets, such as computer-aided design (CAD), very large scale integration (VLSI), robotics, navigation systems, and image processing.
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Capmany, José, and Daniel Pérez. "Practical Implementation of Programmable Photonic Circuits." In Programmable Integrated Photonics. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198844402.003.0006.

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In covering the fundamentals and ideal implementation of integrated multi-port interferometers and waveguide meshes, we saw that solutions with larger integration density of programmable unit cells enables the synthesis of more complex circuits. However, photonic integrated circuits (PICs) generally suffer from design and fabrication errors and other non-ideal working conditions, which compromises performance and scalability. In addition, PICs require the development of two additional tiers (electronic hardware and software) to allow their programmability, optimisation and (re)configuration. This chapter introduces basic practical considerations of programmable PIC design and reviews experimental demonstrations of both multi-port interferometers and waveguide mesh arrangements. It analyses the main error sources and their impact on circuit performance and investigates the most challenging evolution obstacles for very large-scale programmable PICs. It introduces an analytical method for arbitrary waveguide mesh analysis. Finally, it presents a general architecture for the control subsystem and introduces the software framework and main algorithms.
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Kitsos, Paris. "System-on-Chip Design of the Whirlpool Hash Function." In Handbook of Research on Wireless Security. IGI Global, 2008. http://dx.doi.org/10.4018/978-1-59904-899-4.ch017.

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In this chapter, a system-on-chip design of the newest powerful standard in the hash families, named Whirlpool, is presented. With more details an architecture and two very large-scale integration (VLSI) implementations are presented. The first implementation is suitable for high speed applications while the second one is suitable for applications with constrained silicon area resources. The architecture permits a wide variety of implementation tradeoffs. Different implementations have been introduced and each specific application can choose the appropriate speed-area, trade-off implementation. The implementations are examined and compared in the security level and in the performance by using hardware terms. Whirlpool with RIPEMD, SHA-1, and SHA-2 hash functions are adopted by the International Organization for Standardization (ISO/IEC, 2003) 10118-3 standard. The Whirlpool implementations allow fast execution and effective substitution of any previous hash families’ implementations in any cryptography application.
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Kumar, Sunil, and Balwinder Raj. "Simulations and Modeling of TFET for Low Power Design." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-8823-0.ch021.

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In Complementary Metal-Oxide-Semiconductor (CMOS) technology, scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past four decades. However, as the technology advancement on nanometer scale regime for the purpose of building ultra-high density integrated electronic computers and extending performance, CMOS devices are facing fundamental problems such as increased leakage currents, large process parameter variations, short channel effects, increase in manufacturing cost, etc. The new technology must be energy efficient, dense, and enable more device function per unit area and time. There are many novel nanoscale semiconductor devices, this book chapter introduces and summarizes progress in the development of the Tunnel Field-Effect Transistors (TFETs) for low power design. Tunnel FETs are interesting devices for ultra-low power applications due to their steep sub-threshold swing (SS) and very low OFF-current. Tunnel FETs avoid the limit 60mv/decade by using quantum-mechanical Band-to-Band Tunneling (BTBT).
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Corral, Antonio, and Michael Vassilakopoulos. "Query Processing in Spatial Databases." In Handbook of Research on Innovations in Database Technologies and Applications. IGI Global, 2009. http://dx.doi.org/10.4018/978-1-60566-242-8.ch030.

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Spatial data management has been an active area of intensive research for more than two decades. In order to support spatial objects in a database system several important issues must be taken into account such as: spatial data models, indexing mechanisms and efficient query processing. A spatial database system (SDBS) is a database system that offers spatial data types in its data model and query language and supports spatial data types in its implementation, providing at least spatial indexing and efficient spatial query processing (Güting, 1994). The main reason that has caused the active study of spatial database management systems (SDBMS) comes from the needs of the existing applications such as geographical information systems (GIS), computer-aided design (CAD), very large scale integration design (VLSI), multimedia information systems (MIS), data warehousing, multi-criteria decision making, location-based services, etc.
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Conference papers on the topic "Very Large-Scale Integrated (VLSI) design"

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Dahanayaka, Daminda, Phil Kaszuba, Leon Moszkowicz, Randall Wells, James Slinkman, and Lloyd A. Bumm. "Scanning Surface Photovoltage Microscopy for Stress Analysis in Nanoscale CMOS Devices." In ISTFA 2017. ASM International, 2017. http://dx.doi.org/10.31399/asm.cp.istfa2017p0088.

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Abstract Mechanical stress is a critical parameter in the design and manufacture of devices in very large scale integrated (VLSI) circuits. Whether intentionally introduced or parasitic, mechanical stress in nanoscale silicon technologies can alter carrier mobility as by as much as 25%, which can significantly affect device performance. Currently stress metrology for in-line production is conducted only at a wafer monitor level. For design purposes, the stress state in active device regions is usually inferred from electrical data. In this paper an instrument which we have developed is described for measuring mechanical stress in nanoscale silicon devices with high spatial resolution using scanning surface photovoltage microscopy (SSPVM). Other existing techniques are generally not suitable for making such measurements on production silicon nano-device structures in situ.
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Khosrowjerdi, Mohammad, and Gary A. Sniezak. "Design and Analysis of Mechanical Systems Using Electronic Spreadsheet Packages." In ASME 1993 International Computers in Engineering Conference and Exposition. American Society of Mechanical Engineers, 1993. http://dx.doi.org/10.1115/cie1993-0073.

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Abstract In the past decade, sophisticated mathematical, statistical and graphical routines have been added to spreadsheet packages, thus converting them to serious analytical tools. The engineering community has adopted these packages to perform various sensitivity analyses on design problems which lend themselves to these types of applications. Design engineers can now rapidly and conveniently utilize these tools to perform a wide variety of analyses on design problems having simple geometries and loading conditions, without having to develop any FORTRAN, Basic or C code. This paper is concerned with the applications of spreadsheet packages in the area of steady and transient thermal analysis, design optimization and solution of initial-value differential equations. Lotus 1-2-3 in conjunction with the explicit finite difference method (Gauss-Seidel method) has been used to predict transient temperature distribution in an axi-symmetric model of the barrel of a handgun. Borland International Quattro Pro spreadsheet program along with Runge-Kutta and Newmark numerical integration techniques have been employed to optimally design the recoil system of a handgun. Also, the use of Quattro Pro for constructing the contour plots of temperature in a Very Large Scale Integrated (VLSI) chip and the IBM 3081 TCM cold plate are demonstrated. Finally, the built-in Error and Bessel functions in Microsoft Excel have been used to find temperature distribution in a semi-infinite and cylindrical objects.
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Park, Je-Hyoung, Ali Shakouri, and Sung-Mo Kang. "Fast Thermal Analysis of Vertically Integrated Circuits (3-D ICs) Using Power Blurring Method." In ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability. ASMEDC, 2009. http://dx.doi.org/10.1115/interpack2009-89072.

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CMOS VLSI technology has been facing various technical challenges as the feature sizes scale down. To overcome the challenges imposed by the shrink of the conventional on-chip interconnect system in IC chips, alternative interconnect technologies are being developed: one of them is three dimensional chips (3D ICs). Even though 3D IC technology is a promising solution for interconnect bottlenecks, thermal issues can be exacerbated. Thermal-aware design and optimization will be more critical in 3D IC technology than conventional planar IC technology, and hence accurate temperature profiles of each active layer will become very important. In 3D ICs, temperature profile of one layer depends not only on its own power dissipation but also on the heat transferred from other layers. Thus, thermal considerations for 3D ICs need to be done in a holistic manner even if each layer can be designed and fabricated individually. Conventional grid-based temperature computation methods are accurate but are computationally expensive, especially for 3D ICs. To increase computational efficiency, we developed a matrix convolution technique, called Power Blurring (PB) for 3D ICs. The temperature resulting from any arbitrary power dissipation in each layer of the 3D chip can be computed quickly. The PB method has been validated against commercial FEA software, ANSYS. Our method yields good results with maximum error less than 2% for various case studies and reduces the computation time by a factor of ∼ 60. The additional advantage is the possibility to evaluate different power dissipation profiles without the need to re-mesh the whole 3D chip structure.
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Chen, Xiaolin, Hui Zhang, and Will Miller. "Automatic Feature Recognition for Data Interoperability Issues in High-Speed Electronics System Design." In ASME 2008 International Mechanical Engineering Congress and Exposition. ASMEDC, 2008. http://dx.doi.org/10.1115/imece2008-68389.

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Technology trends toward higher speed and density devices have pushed high performance electronic system design to its limits. With fine miniaturization of very-large-scale integrated (VLSI) circuits and rapid increase in the working frequency of system-on-a-chip (SoC), the signal integrity has become a major concern. As the operating frequencies enter the gigahertz range, signal integrity issues such as cross talk, power-ground-plane voltage bounce, and substrate losses can no longer be neglected. In order to design high-performance electronic systems with fast time-to-market, it is often needed to analyze whole or part of the system at one fundamentally deeper level of physics. It has begun to be recognized that electromagnetic (EM) field analysis needs to be rigorously included as an addition to traditional circuit simulation. A common problem in this practice is the lack of efficient tools that enable engineers to easily transfer circuit board design data into EM solvers. To partially solve this problem, ACIS SAT has been introduced as a standard data exchange format and been adopted by many software vendors for data import and export. However, efficient data transfer remains a problem as the geometry created in the design package becomes static and no longer feature-based once imported into the simulation package. In this paper, automatic feature recognition algorithms are implemented to help extract features and parameters from the imported static model in SAT format. Case studies will be provided for some representative high speed electronics designs. This work is supported by Research & Technology Development Grant Program of Washington Technology Center with a goal to achieve improved design process for high-speed electronic systems. The developed tool has a potential to speed up the current design process by eliminating laborious manual preparation of design data for EM simulation and allow what-if analysis to be automated to highlight likely signal integrity issues.
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Kim, Se, and Vincent Mooney. "Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design." In 2006 IFIP International Conference on Very Large Scale Integration. IEEE, 2006. http://dx.doi.org/10.1109/vlsisoc.2006.313263.

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Koser, Erol, Sebastian Krosche, and Walter Stechele. "Integrated Soft Error Resilience and Self-Test." In 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2016. http://dx.doi.org/10.1109/vlsi-soc.2016.7753569.

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Chusseau, Laurent, Rachid Omarouayache, Jeremy Raoult, et al. "Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI)." In 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-soc.2014.7004189.

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Gunti, Nagendra Babu, Aman Khatri, and Karthikeyan Lingasubramanian. "Realizing a security aware triple modular redundancy scheme for robust integrated circuits." In 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-soc.2014.7004183.

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Sui, Y., C. J. Teo, P. S. Lee, Y. T. Chew, and C. Shu. "An Efficient Wavy Microchannel Heat Sink for Electronic Devices." In ASME 2009 Heat Transfer Summer Conference collocated with the InterPACK09 and 3rd Energy Sustainability Conferences. ASMEDC, 2009. http://dx.doi.org/10.1115/ht2009-88585.

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In this paper, we have designed a compact and efficient liquid-cooled heat sink for mini-sized electronic devices, particularly for very-large-scale integrated (VLSI) circuits. The heat sink can either be an integral part of the silicon (or metal) substrate, or a separate part attached onto the substrate. The heat sink consists of several wavy microchannels, with hydraulic diameter on the order of 100 μm, microfabricated on a silicon or metal substrate. The fluid flow and heat transfer performance of the heat sink are studied using numerical simulations in the steady laminar flow region and the dynamical system technique using Poincare´ sections is employed to analyze the fluid mixing. It is found that when the liquid coolant flows through the wavy microchannel, Dean vortices can develop. The quantity and location of the Dean vortices may change along the flow direction, which can lead to laminar chaos. The chaotic advection greatly enhances the fluid mixing, and thus the heat transfer performance of the present heat sink is much more superior than previous designs which employed straight microchannels. It is also found that the pressure drop penalty is much smaller that the heat transfer enhancement for the present heat sink. Furthermore, the relative wavy amplitude (wavy amplitude/wavelength) of the channels can be varied along the flow direction for various purposes, without compromising the compactness and efficiency of the heat sink. The relative waviness can be increased along the flow direction, which results in higher heat transfer coefficients and renders the temperature for the devices much more uniform. The relative waviness can also be designed to be higher in regions of high heat flux for hot spot mitigation purposes.
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OrConnor, Ian, Mayeul Cantan, Cedric Marchand, et al. "Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices." In 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2018. http://dx.doi.org/10.1109/vlsi-soc.2018.8644809.

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Reports on the topic "Very Large-Scale Integrated (VLSI) design"

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Clark, Kay E. VLSI/VHSIC (Very Large Scale Integrated/Very High Speed Integrated Circuits) Package Test Development. Defense Technical Information Center, 1986. http://dx.doi.org/10.21236/ada182360.

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Nash, J. G. VLSI (Very Large Scale Integration) Floating Point Chip Design Study. Defense Technical Information Center, 1985. http://dx.doi.org/10.21236/ada164198.

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Leighton, F. T. Theoretical Aspects of VLSI (Very Large Scale Integration) Circuit Design. Defense Technical Information Center, 1986. http://dx.doi.org/10.21236/ada175051.

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Cohen, Seymour. Quality Procedures for VLSI/VHSIC (Very Large Scale Integrated and Very High Speed Integrated Circuits) Type Devices. Defense Technical Information Center, 1985. http://dx.doi.org/10.21236/ada164885.

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Collier, Wiehrs L. VLSI (Very Large Scale Integrated Circuits) Implementation of a Quantized Sinusoid Filter Algorithm and Its Use to Compute the Discrete Fourier Transform. Defense Technical Information Center, 1986. http://dx.doi.org/10.21236/ada168605.

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