Dissertations / Theses: 'Very Large-Scale Integrated (VLSI) design'

1

Al-Mahmood, Saiyid Jami Islah Ahmad. "A distributed design rule checker for VLSI layouts." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-11012008-063423/.

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2

高雲龍 and Wan-lung Ko. "A new optimization model for VLSI placement." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B29812938.

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Chu, Chung-kwan, and 朱頌君. "Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B38719551.

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4

Chen, Ing-yi 1962. "Efficient reconfiguration by degradation in defect-tolerant VLSI arrays." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277195.

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This thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI array consists of identical cells such as memory cells or processors. In contrast to the redundancy approach in which some cells are dedicated as spares, all the cells in the degradation approach are treated in a uniform way. Each cell can be either fault-free or defective and a subarray which contains no faulty cell is derived under constraints of switching and routing mechanisms. Although extensive literatures exist concerning spare allocation and reconfiguration in arrays with redundancy, little research has been published on optimal reconfiguration in a degradable array. A systematic method based on graph theoretic models is developed to deal with the problem. The complexities of reconfiguration are analyzed for schemes using different switching mechanisms. Efficient heuristic algorithms are presented to determine a target subarray from the defective host array.

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Dickinson, Alex. "Complexity management and modelling of VLSI systems." Title page, contents and abstract only, 1988. http://web4.library.adelaide.edu.au/theses/09PH/09phd553.pdf.

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Koelmans, Albertus Maria. "STRICT : a language and tool set for the design of very large scale integrated circuits." Thesis, University of Newcastle Upon Tyne, 1996. http://hdl.handle.net/10443/2076.

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An essential requirement for the design of large VLSI circuits is a design methodology which would allow the designer to overcome the complexity and correctness issues associated with the building of such circuits. We propose that many of the problems of the design of large circuits can be solved by using a formal design notation based upon the functional programming paradigm, that embodies design concepts that have been used extensively as the framework for software construction. The design notation should permit parallel, sequential, and recursive decompositions of a design into smaller components, and it should allow large circuits to be constructed from simpler circuits that can be embedded in a design in a modular fashion. Consistency checking should be provided as early as possible in a design. Such a methodology would structure the design of a circuit in much the same way that procedures, classes, and control structures may be used to structure large software systems. However, such a design notation must be supported by tools which automatically check the consistency of the design, if the methodology is to be practical. In principle, the methodology should impose constraints upon circuit design to reduce errors and provide' correctness by construction' . It should be possible to generate efficient and correct circuits, by providing a route to a large variety of design tools commonly found in design systems: simulators, automatic placement and routing tools, module generators, schematic capture tools, and formal verification and synthesis tools.

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袁志勤 and Chi-kan Yuen. "A double-track greedy algorithm for VLSI channel routing." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1997. http://hub.hku.hk/bib/B31220241.

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Boudreault, Yves 1959. "Design of a VLSI convolver for a robot vision system." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65342.

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Whipple, Thomas Driggs 1961. "Design and implementation of an integrated VLSI packaging support software environment." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277105.

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An interactive software shell has been developed which integrates several packaging simulation tools developed at the University of Arizona which are used to analyze electro-magnetic coupling between interconnects in an integrated circuit. This software shell uses experimental frames to manage this simulation process. Through the experimental frames, the model descriptions and the model inputs are separated, and input data is verified for correctness. This model/input separation allows several model variations to be tested based on several input variations. The results of these simulations are then analyzed and displayed graphically. Further work for the software shell is discussed. This tool provides a user-friendly, efficient method for performing coupled-line analyses in interconnect systems.

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10

Chabbi, Charef. "VLSI NMOS hardware design of a linear phase FIR low pass digital filter." Ohio University / OhioLINK, 1985. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183749814.

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11

Mao, Hsein-Jung Joey. "VLSI design and implementation of a parallel sorter." Ohio : Ohio University, 1988. http://www.ohiolink.edu/etd/view.cgi?ohiou1182865325.

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12

Cooke, Bradly James. "S-parameter VLSI transmission line analysis." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184876.

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This dissertation investigates the implementation of S-parameter based network techniques for the analysis of multiconductor, high speed VLSI integrated circuit and packaging interconnects. The S-parameters can be derived from three categories of input parameters: (1) lossy quasi-static R,L,C and G, (2) lossy frequency dependent (dispersive) R,L,C,G and (3) the propagation constants, Γ, the characteristic impedance, Z(c) and the conductor eigencurrents, I, derived from full wave analysis. The S-parameter network techniques developed allow for: the analysis of periodic waveform excitation, the incorporation of externally measured or calculated scattering parameter data and large system analysis through macro decomposition. The inclusion of non-linear terminations has also been developed.

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13

Liu, Zhenyu. "Generic low power reconfigurable distributed arithmetic processor." Thesis, University of Edinburgh, 2009. http://hdl.handle.net/1842/3930.

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Higher performance, lower cost, increasingly minimizing integrated circuit components, and higher packaging density of chips are ongoing goals of the microelectronic and computer industry. As these goals are being achieved, however, power consumption and flexibility are increasingly becoming bottlenecks that need to be addressed with the new technology in Very Large-Scale Integrated (VLSI) design. For modern systems, more energy is required to support the powerful computational capability which accords with the increasing requirements, and these requirements cause the change of standards not only in audio and video broadcasting but also in communication such as wireless connection and network protocols. Powerful flexibility and low consumption are repellent, but their combination in one system is the ultimate goal of designers. A generic domain-specific low-power reconfigurable processor for the distributed arithmetic algorithm is presented in this dissertation. This domain reconfigurable processor features high efficiency in terms of area, power and delay, which approaches the performance of an ASIC design, while retaining the flexibility of programmable platforms. The architecture not only supports typical distributed arithmetic algorithms which can be found in most still picture compression standards and video conferencing standards, but also offers implementation ability for other distributed arithmetic algorithms found in digital signal processing, telecommunication protocols and automatic control. In this processor, a simple reconfigurable low power control unit is implemented with good performance in area, power and timing. The generic characteristic of the architecture makes it applicable for any small and medium size finite state machines which can be used as control units to implement complex system behaviour and can be found in almost all engineering disciplines. Furthermore, to map target applications efficiently onto the proposed architecture, a new algorithm is introduced for searching for the best common sharing terms set and it keeps the area and power consumption of the implementation at low level. The software implementation of this algorithm is presented, which can be used not only for the proposed architecture in this dissertation but also for all the implementations with adder-based distributed arithmetic algorithms. In addition, some low power design techniques are applied in the architecture, such as unsymmetrical design style including unsymmetrical interconnection arranging, unsymmetrical PTBs selection and unsymmetrical mapping basic computing units. All these design techniques achieve extraordinary power consumption saving. It is believed that they can be extended to more low power designs and architectures. The processor presented in this dissertation can be used to implement complex, high performance distributed arithmetic algorithms for communication and image processing applications with low cost in area and power compared with the traditional methods.

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Dandu, Venkata Satyanarayana Raju. "Parallel processing and VLSI design a high speed efficient multiplier." Ohio : Ohio University, 1985. http://www.ohiolink.edu/etd/view.cgi?ohiou1183753328.

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15

Bagchi, Tanuj. "An Efficient Hybrid Heuristic and Probabilistic Model for the Gate Matrix Layout Problem in VLSI Design." Thesis, University of North Texas, 1993. https://digital.library.unt.edu/ark:/67531/metadc500878/.

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In this thesis, the gate matrix layout problem in VLSI design is considered where the goal is to minimize the number of tracks required to layout a given circuit and a taxonomy of approaches to its solution is presented. An efficient hybrid heuristic is also proposed for this combinatorial optimization problem, which is based on the combination of probabilistic hill-climbing technique and greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test cases, five benchmark problems from the literature as well as randomly generated problem instances are considered. The experimental results show that the proposed hybrid algorithm, on the average, performs better than other heuristics in terms of the required computation time and/or the quality of solution. Due to the computation-intensive nature of the problem, an exact solution within reasonable time limits is impossible. So, it is difficult to judge the effectiveness of any heuristic in terms of the quality of solution (number of tracks required). A probabilistic model of the gate matrix layout problem that computes the expected number of tracks from the given input parameters, is useful to this respect. Such a probabilistic model is proposed in this thesis, and its performance is experimentally evaluated.

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16

Johnson, Timothy E. "MOSSTAT An interactive static rule checker for MOS VLSI designs." Full text open access at:, 1986. http://content.ohsu.edu/u?/etd,109.

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17

Lacy, William Stephen. "Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/14690.

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18

Appleton, Samuel Scott. "Performance-directed design of asynchronous VLSI systems /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09pha651.pdf.

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19

Anbalagan, Pranav. "Limitations and opportunities for wire length prediction in gigascale integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22670.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007. Committee Chair: Dr. Jeff Davis; Committee Member: Dr. James D. Meindl; Committee Member: Dr. Paul Kohl; Committee Member: Dr. Scott Wills; Committee Member: Dr. Sung Kyu Lim.

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20

Battina, Brahmasree. "An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc799495/.

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Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and is a process of making ICs by placing millions of transistors on a single chip. Because of advancements in VLSI design technologies, ICs are getting smaller, faster in speed and more efficient, making personal devices handy, and with more features. In this thesis work an interactive framework is designed in which the fundamental concepts of digital logic design and VLSI design such as logic gates, MOS transistors, combinational and sequential logic circuits, and memory are presented in a simple, interactive and user friendly way to create interest in students towards engineering fields, especially Electrical Engineering and Computer Engineering. Most of the concepts are explained in this framework by taking the examples which we see in our daily lives. Some of the critical design concerns such as power and performance are presented in an interactive way to make sure that students can understand these significant concepts in an easy and user friendly way.

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Zhang, Wei Zhang. "Wireless receiver designs from information theory to VLSI implementation /." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31817.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. Committee Chair: Ma, Xiaoli; Committee Member: Anderson, David; Committee Member: Barry, John; Committee Member: Chen, Xu-Yan; Committee Member: Kornegay, Kevin. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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22

Mukherjee, Valmiki. "A Dual Dielectric Approach for Performance Aware Reduction of Gate Leakage in Combinational Circuits." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5255/.

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Design of systems in the low-end nanometer domain has introduced new dimensions in power consumption and dissipation in CMOS devices. With continued and aggressive scaling, using low thickness SiO2 for the transistor gates, gate leakage due to gate oxide direct tunneling current has emerged as the major component of leakage in the CMOS circuits. Therefore, providing a solution to the issue of gate oxide leakage has become one of the key concerns in achieving low power and high performance CMOS VLSI circuits. In this thesis, a new approach is proposed involving dual dielectric of dual thicknesses (DKDT) for the reducing both ON and OFF state gate leakage. It is claimed that the simultaneous utilization of SiON and SiO2 each with multiple thicknesses is a better approach for gate leakage reduction than the conventional usage of a single gate dielectric (SiO2), possibly with multiple thicknesses. An algorithm is developed for DKDT assignment that minimizes the overall leakage for a circuit without compromising with the performance. Extensive experiments were carried out on ISCAS'85 benchmarks using 45nm technology which showed that the proposed approach can reduce the leakage, as much as 98% (in an average 89.5%), without degrading the performance.

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Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

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The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.

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24

Inampudi, Sivateja. "Teaching Fundamentals of Digital Logic Design and VLSI Design Using Computational Textiles." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc699874/.

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This thesis presents teaching fundamentals of digital logic design and VLSI design for freshmen and even for high school students using e-textiles. This easily grabs attention of students as it is creative and interesting. Using e-textiles to project these concepts would be easily understood by students at young age. This involves stitching electronic circuits on a fabric using basic components like LEDs, push buttons and so on. The functioning of these circuits is programmed in Lilypad Arduino. By using this method, students get exposed to basic electronic concepts at early stage which eventually develops interest towards engineering field.

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Voranantakul, Suwan 1962. "CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/277037.

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Voo, Thart Fah. "Tunable techniques for robust high frequency analogue VLSI." Thesis, Imperial College London, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.369050.

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Matsumori, Barry Alan. "QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275313.

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Jafar, Mutaz 1960. "THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276959.

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Liu, Yansong. "Passivity checking and enforcement in VLSI model reduction exercise." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290690.

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Morris, Tonia Gay. "Analog VLSI visual attention systems." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/15010.

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Măndoiu, Ion I. "Approximation algorithms for VLSI routing." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/9128.

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Kelley, Brian T. "VLSI computing architectures for high speed seismc migration." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13919.

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Wilson, Denise M. "Analog VLSI architecture for chemical sensing microsystems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13322.

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34

KRISHT, MUHAMMED HUSSEIN, and MUHAMMED HUSSEIN KRISHT. "LPCVD TUNGSTEN MULTILAYER METALLIZATION FOR VLSI SYSTEMS." Diss., The University of Arizona, 1985. http://hdl.handle.net/10150/187983.

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Advances in microlithography, dry etching, scaling of devices, ion-implantation, process control, and computer aid design brought the integrated circuit technology into the era of VLSI circuits. Those circuits are characterized by high packing density, improved performance, complex circuits, and large chip sizes. Interconnects and their spacing dominate the chip area of VLSI circuits and they degrade the circuit performance through the unacceptable high time delays. Multilayer metallization enables shorter interconnects, ease of design and yet higher packing density for VLSI circuits. It was shown in this dissertation that, tungsten films deposited in a cold-wall LPCVD reactor offer viable solution to the problems of VLSI multilayer interconnects. Experiments showed that LPCVD tungsten films have good uniformity, high purity, low resistivity, low stress-good adherence and are readily patterned into high resolution lines. Moreover, a multilayer interconnect system consisting of three layers of tungsten metallization followed by a fourth layer of aluminum metallization has been designed, fabricated and tested. The interlevel dielectric used to separate the metal layers was CVD phosphorus doped silicon dioxide. Low ohmic contacts were achieved for heavily doped silicon. Also, low resistance tungsten-tungsten intermetallic contacts were obtained. In addition to excellent step coverage, high electromigration resistance of interconnects was realized. Finally, CMOS devices and logic gates were successfully fabricated and tested using tungsten multilayer metallization schemes.

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Bragg, Julian Alexander. "A biomorphic analog VLSI implementation of a mammalian motor unit." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/20693.

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36

Tan, Wei-Siong. "A VLSI parallel processor structure for scientific computing." Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/13455.

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37

Moini, Alireza. "Synthesis of biological vision models using analog VLSI /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09phm712.pdf.

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38

Shope, David Allen 1958. "Thermal characterization of VLSI packaging." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276686.

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With electronic packaging becoming more complex, simple hand methods to model the thermal performance of the package are insufficient. As computer aided modeling methods came into use, a test system was developed to verify the predictions produced by such modeling methods. The test system is evaluated for operation and performance. Further, the premise of this type of test (the accurate calibration of packaged temperature-sensitive-parameter devices can be done) is investigated using a series of comparative tests. From this information, causes of possible/probable errors in calibration are identified and related to the different methodologies and devices used. Finally, conclusions are presented regarding the further improvement of the test system and methodologies used in this type of testing.

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Narayanan, Prakash. "Analytical modeling and simulation of bicmos for VLSI circuits." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/42199.

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Interest in BiCMOS technology has been generated recently due to the potential advantages this technology offers over conventional CMOS which enjoys widespread use in today’s semiconductor industry. However, before BiCMOS can be readily adopted by the VLSI community, an understanding of the design issues and tradeoffs involved when utilizing it, must be achieved. The principal focus of this research is to move towards such an understanding through the means of analytical modeling and circuit simulation using PSPICE [1]. The device chosen for the modeling approach is the basic BiCMOS Inverting Buffer Driver. The model yields equations that characterize output rise and fall transients and quantify the delays incurred therein. At the end of the analysis, we have a composite set of delay equations that are a measure of the total gate delay and reflect the importance of individual device and circuit parameters in determining this delay. Further investigations conducted to determine the influence of device, circuit and process parameters on BiCMOS, indicate that this technology is far more resilient to variations in such parameters than CMOS. At the end of this research, we are able to make a definitive judgement about BiCMOS performance and its superiority over CMOS in the switching speed domain. Master of Science

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40

Geller, Ronnie Dee. "A VLSI architecture for a neurocomputer using higher-order predicates." Full text open access at:, 1987. http://content.ohsu.edu/u?/etd,137.

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41

Sayers, I. L. "An investigation of 'design for testability' techniques in very large scale integrated circuits." Thesis, University of Newcastle Upon Tyne, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.370643.

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42

Liu, Yansong, and 劉岩松. "Passivity checking and enforcement in VLSI model reduction exercise." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B41290690.

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Blum, Richard Alan. "An analog VLSI centroid imager." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14826.

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雷應春 and Ying-chun Lui. "Lattice algorithms for multidimensional fields suitable for VLSI implementation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1989. http://hub.hku.hk/bib/B31208757.

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45

Holland, Kenneth Chris. "Probability of latching single event upset errors in VLSI circuits." Thesis, Virginia Tech, 1991. http://hdl.handle.net/10919/41980.

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The ability of radiation to cause transient faults in space borne as well as ground based computers is well known. with the density of VLSI circuits increasing every year, the probability of an upset by radiation is becoming more likely. However, research in this area has matured over the last decade, and the mechanisms which cause such faults are better understood. This understanding enables us to propose ideas to eliminate or lessen the effects of radiation on VLSI circuits. Most of the research to date has concentrated on the effect of transient faults on flip-flops rather than combinational logic. This is due to several reasons. First, transient faults, also known as Single Event Upsets (SEU), were first observed in memory circuits located on board satellites. Second, an SEU can leave a lasting effect on a circuit if it occurs in a flip-flop, and third, SEUs can cause the output of a flip-flop to change state more easily if it occurs directly in the flip-flop rather than in the combinational logic. In combinational logic, the node struck by the radiation is completely disjoint from the flip-flops output node. This in effect causes the SEU to satisfy more criteria in order to change the flip-flops output state. The criteria that the SEU must satisfy tend to be complex, and this complexity has caused many researchers to believe that SEUs that occur in combinational logic cause negligible errors in the state of flip-flops. Thus, in this thesis, the criteria for latching a SEU are discussed, and original methods are presented that can be used to determine the probability of an SEU occurring at any node in a circuit will cause a change in the output state of a flip-flop. The methods are then incorporated into a program, named SUPER II, that is able to evaluate the circuit to determine the nodes with the highest probability of having a SEU error latched. The results from the program show that SEUs that occur in combinational logic can have a significant probability of becoming latched. Master of Science

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46

Ali, Faridah M. "Parallel pipelined VLSI arrays for real-time image processing." Diss., Virginia Polytechnic Institute and State University, 1988. http://hdl.handle.net/10919/49914.

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Real-time image processing involves processing a wide spectrum of algorithms on huge data sets. Processing at the pixel data rate demands more powerful parallel machines than those developed for conventional image processing. This research takes advantage of current VLSI technology to examine a new approach for processing arbitrary algorithms at real-time data rate. It is based on embedding the algorithms, expressed by their dependency graphs, into two dimensional regularly connected processing arrays. Each node in a graph represents an operation which can be processed by an individual processor in the array. The embedding is performed such that data can be processed in a pipeline fashion as they are received. The result is a machine which exploits functional parallelism and data pipelining simultaneously. The presentation is divided into three parts: the first discusses graphical representation for general image processing algorithms, taking into account the nature of the data flow in real-time systems. The conditions for pipelining the processing of the graph are derived. Next the logical design of a class of VLSI arrays is considered. These arrays can be configured to embed arbitrary problem graphs. The discussion involves the architecture of the array, the architecture of its processing elements and an efficient programming scheme. Finally, static embedding of the dependency graphs into the proposed array is considered. Lower and upper bounds on the area needed to embed any graph are found. Three heuristic procedures to embed the graph at minimum cost are developed, implemented and tested. Ph. D. incomplete_metadata

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47

Zhang, Zheng, and 张政. "Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2010. http://hub.hku.hk/bib/B44909056.

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The Best MPhil Thesis in the Faculties of Dentistry, Engineering, Medicine and Science (University of Hong Kong), Li Ka Shing Prize,2009-2010 published_or_final_version Electrical and Electronic Engineering Master Master of Philosophy

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Buchanan, Brent E. "A mixed-signal CMOS VLSI image convolution circuit using error spectrum shaping." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15420.

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Lei, Chi-un, and 李志遠. "VLSI macromodeling and signal integrity analysis via digital signal processing techniques." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45700588.

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Chen, Quan, and 陈全. "Efficient high-frequency electromagnetic simulation in VLSI: rough surface effects and electromagnetic-semiconductor coupled simulation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2010. http://hub.hku.hk/bib/B44904940.

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Dissertations / Theses on the topic 'Very Large-Scale Integrated (VLSI) design'

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