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Journal articles on the topic 'Very Large-Scale Integrated (VLSI) design'
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MOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (2021): 505–11. http://dx.doi.org/10.6036/10214.
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Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;
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CHEN, JIANLI, and WENXING ZHU. "A PLACEMENT FLOW FOR VERY LARGE-SCALE MIXED-SIZE CIRCUIT PLACEMENT." Journal of Circuits, Systems and Computers 23, no. 02 (2014): 1450016. http://dx.doi.org/10.1142/s0218126614500169.
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The very large-scale integrated circuit (VLSI) placement problem is to determine the exact location of each movable circuit element within a given region. It is a crucial process in physical design, since it affects performance, power consumption, routability, and heat distribution of a design. In this paper, we propose a VLSI placement flow to handle the large-scale mixed-size placement problem. The main idea of our placement flow is using a floorplanning algorithm to guide the placement of circuit elements. It consists of four steps: (1) With the multilevel framework, circuit elements are clustered into blocks by recursively partitioning; (2) a floorplanning algorithm is performed on every level of the blocks; (3) the macro cells are shifted by a macro shifting technique to determine their exact locations; (4) with each macro cell location fixed, a standard cell placement algorithm is applied to place the remaining objects. The proposed approach is tested on the IBM mixed-size benchmarks and the modern mixed-size (MMS) placement benchmarks. Experimental results show that our approach outperforms the state-of-the-art placers on the solution quality for most of the benchmarks.
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Wölcken, Klaus. "Skill Needs in VLSI Circuits." Industry and Higher Education 6, no. 1 (1992): 50. http://dx.doi.org/10.1177/095042229200600113.
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The forecast need for designers of Very Large Scale Integrated Circuits is described. The article then goes on to outline the support being provided for academic institutions involved with VLSI design training by the European Commission's Directorate General XIII.
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Zabidi, Nurulnajah Mohd, and Ab Al-Hadi Ab Rahman. "VLSI Design of a Fast Pipelined 8x8 Discrete Cosine Transform." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 3 (2017): 1430. http://dx.doi.org/10.11591/ijece.v7i3.pp1430-1435.
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This paper presents a Very Large Scale Integrated (VLSI) design and implementation of a fixed-point 8x8 multiplierless Discrete Cosine Transform (DCT) using the ISO/IEC 23002-2 algorithm. The standard DCT algorithm, which is mainly used in image and video compression technology, consists of only adders, subtractors, and shifters, therefore making it efficient for hardware implementation. The VLSI implementation of the algorithm given in this paper further enhances the performance of the transform unit. Furthermore, circuit pipelining has been applied to the base design of the DCT, which significantly improves the performance by reducing the longest path in the non-pipeline design. The DCT has been implemented using semi-custom VLSI design methodology using the TSMC 0.13um process technology. Results show that our DCT designs can run up to around 1.7 Giga pixels/s, which is well above the timing required for real-time ultra-high definition 8K video.
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Wong, C. P. "An Overview of Integrated Circuit Device Encapsulants." Journal of Electronic Packaging 111, no. 2 (1989): 97–107. http://dx.doi.org/10.1115/1.3226528.
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The rapid development of integrated circuit technology from small-scale integration (SSI) to very large scale integration (VLSI) has had great technological and economical impact on the electronics industry. The exponential growth of the number of components per IC chip, the exponential decrease of device dimensions, and the steady increase in IC chip size have imposed stringent requirements, not only on the IC physical design and fabrication, but also on IC encapsulants. This report addresses the purpose of encapsulation, encapsulation techniques, and a general overview of the application of inorganic and organic polymer materials as electronic device encapsulants.
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Zhang, Ai Rong. "The Integration on Electrical Control Systems Based on Optimized Method." Advanced Materials Research 490-495 (March 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.
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Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity and reuse difficulty. This is true even with programmable logic device (PLD) solutions. Conception aid developer (CAD) combined with hardware description languages (HDL) and VLSI design methodology have accelerated conception and reuse. Nevertheless, the main problem of integrated circuit design is to define the hardware architecture; this is particularly true for heterogeneous algorithm structures such as electrical controls.
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Suresh, N., K. Subba Rao, and R. Vassoudevan. "Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques." Journal of Computational and Theoretical Nanoscience 17, no. 4 (2020): 1595–99. http://dx.doi.org/10.1166/jctn.2020.8407.
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Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.
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Pan, Li Yan, and Yan Pei Liu. "An Application of Rectilinear Embedding in VLSI Placement." Advanced Materials Research 734-737 (August 2013): 2842–45. http://dx.doi.org/10.4028/www.scientific.net/amr.734-737.2842.
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The VLSI (Very Large Scale Integrated Circuits) technology has developed rapidly in recent years, with a lot of advanced electric products emerging. Placement layout is regarded as the initial step in VLSI physical design. Its quality has a direct effect on the chip area and performance. The rectilinear embedding, which originates from graph theory, is widely employed in VLSI placement. In this paper, we set up a mathematical model for VLSI. Firstly, the issue of VLSI placement was converted to quadrangulation by using rectilinear embedding. Then we provided generating functions for two types of quadrangulations with graph multiple parameters. And the explicit formulae by employing Lagrangian inversion were obtained. Furthermore, we found the relation between outerplanar graph and Hamilton graph, so the counting result of Hamilton quadrangulation was derived. The quadrangulation calculation can be applied to the establishment of a computerized algorithm, which can be widely used for VLSI placement optimization.
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Radfar, Mohsen, Kriyang Shah, and Jugdutt Singh. "Recent Subthreshold Design Techniques." Active and Passive Electronic Components 2012 (2012): 1–11. http://dx.doi.org/10.1155/2012/926753.
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Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.
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Dhiraj, Dhiraj, Seema Verma, Rajesh Kumar, and Himanshu Choudhary. "A enhanced algorithm for floorplan design using evolutionary technique." Artificial Intelligence Research 1, no. 2 (2012): 38. http://dx.doi.org/10.5430/air.v1n2p38.
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Floor planning is an important problem in very large scale integrated-circuit (VLSI) design automation domain as it evaluates the performance, size, yield and reliability of ICs. Due to rapid increase in number of components on a chip, floor planning has gained its importance further in determining the quality of the design achieved. In this paper we have devised an approach for placement of modules in a given area with bounding constraints in terms of minimum placement area imposed. We have used Modified Genetic Algorithm (MGA) technique for determining and obtaining an optimal placement using an iterative approach.
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Shakir, Muhammad, Shuoben Hou, Raheleh Hedayati, Bengt Gunnar Malm, Mikael Östling, and Carl-Mikael Zetterling. "Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications." Electronics 8, no. 5 (2019): 496. http://dx.doi.org/10.3390/electronics8050496.
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A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.
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Laudis, Lalin L., and N. Ramadass. "A Lion’s Pride Inspired Algorithm for VLSI Floorplanning." Journal of Circuits, Systems and Computers 29, no. 01 (2019): 2050003. http://dx.doi.org/10.1142/s0218126620500036.
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The complexity of any integrated circuit pushes the researchers to optimize the various parameters in the design process. Usually, the Nondeterministic Polynomial problems in the design process of Very Large Scale Integration (VLSI) are considered as a Single Objective Optimization Problem (SOOP). However, due to the increasing demand for the multi-criterion optimization, researchers delve up on Multi-Objective Optimization methodologies to solve a problem with multiple objectives. Moreover, it is evident from the literature that biologically inspired algorithm works very well in optimizing a Multi-Objective Optimization Problem (MOOP). This paper proposes a new Lion’s pride inspired algorithm to solve any MOOP. The methodologies mimic the traits of a Lion which always strives to become the Pride Lion. The Algorithm was tested with VLSI floorplanning problem wherein the area and dead space are the objectives. The algorithm was also tested with several standard test problems. The tabulated results justify the ruggedness of the proposed algorithm in solving any MOOP.
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Yoshikawa, Masaya, and Hidekazu Terai. "Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation." Journal of Advanced Computational Intelligence and Intelligent Informatics 10, no. 1 (2006): 112–20. http://dx.doi.org/10.20965/jaciii.2006.p0112.
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The floorplanning problem, a basic design step in layout design of very large-scale integrated circuit (VLSI), deals with placing rectangular modules at maximum density. Many studies have dealt with conducted this problem using sequence pairs based on genetic algorithms (GAs), but this generally requires much calculation time. We propose an architecture for high-speed floorplanning using a sequence pair based on GA. The proposed architecture, implemented on the field-programmable gate array (FPGA), achieves high-speed processing. Measurement evaluating the proposed architecture demonstrated speeds 37.1 times greater than software processing.
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Rajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics." Journal of Circuits, Systems and Computers 27, no. 13 (2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.
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Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write operation over the previous MFFs. This magnetic-based logic circuit is based on the previous two-in-one (TIO) MTJ cell that presents the aforementioned attributes. Radiation-induced single event upset, as another reliability challenge, is also taken into consideration for the MFFs and another MFF robust against radiation effects is suggested and evaluated.
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Sidorenko, V. P., V. D. Zhora, O. I. Radkevich, et al. "Assembly technology and design features of microelectronic coordinate-sensitive detectors." Технология и конструирование в электронной аппаратуре, no. 1 (2018): 21–27. http://dx.doi.org/10.15222/tkea2018.1.21.
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The design features and assembly technology of microelectronic coordinate-sensitive detectors of charged particles for spectroscopy are considered. The device is based on the specialized very-large-scale integration (VLSI) crystal manufactured using CMOS technology and containing a charge-sensitive matrix designed to detect isotope ions in a wide mass spectrum of the test substance. The range of concentrations measured by devices is also wide and ranges from 10–7 to 100%. The VLSI crystal is placed on a multilayer ceramic basis. The devices also contain a Hamamatsu micro-channel plate (MCP), electrodes that supply high voltage to integrated circuits (2.0 kV), a non-magnetic metal shield for protecting the device components, a connector and other structural elements. VLSI crystals are installed using the method of laying the microcircuits on a flexible aluminum — polyimide media. Such mounting method has a number of advantages over others. The VLSI crystals with project standards of 1 µm are designed for the possibility to create new generation of detectors, which can include either one or several crystals. The prototype version has been developed and it allows placing a bar of five ceramic-based crystals with a minimum gap of 100 µm between them. This design provides high reliability of products due to the usage of multilayer ceramic boards and due to progressive assembly methods used in the manufacturing of special-purpose microelectronic equipment, including the equipment resistant to special external factors.
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Shanavas, I. Hameem, and R. K. Gnanamurthy. "Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm." Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/809642.
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In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.
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Kumar, Umesh. "Vlsi Interconnection Modelling Using a Finite Element Approach." Active and Passive Electronic Components 18, no. 3 (1995): 179–202. http://dx.doi.org/10.1155/1995/97362.
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In the last decade, an important shift has taken place in the design of hardware with the advent of smaller and denser integrated circuit packages. Analysis techniques are required to ensure the proper electrical functioning of this hardware. An efficient method is presented to model the parasitic capacitance of VLSI (very large scale integration) interconnections. It is valid for conductors in a stratified medium, which is considered to be a good approximation for theSi−SiO2system of which present day ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a “spider” of edges. Here the method used [1] has very low complexity, as compared to other models used previously [2], and achieves a high degree of precision within the range of validity of the stratified medium.
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S. Khanande, Sachin, and S. J. Honade. "Design and Implementation of Recursive Least Square Adaptive Filter Using Block DCD approach." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (2015): 209. http://dx.doi.org/10.11591/ijres.v4.i3.pp209-212.
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<p>Due to the explosive growth of multimedia application and tremendous demands in Very Large Scale Integrated (VLSI), there is a need of high speed and low power digital filters for digital signal processing applications. In Digital Signal Processing (DSP) systems, Finite Impulse Response (FIR) filters are one of the most common components which is used, by convolving the input data samples with the desired unit sample response of the filter. The proposed work deals with the design and implementation of RLS adaptive filter using block DCD approach. The evaluation of speed, area and power for proposed work will be done. Also, the comparison of the proposed design with the existing will be carried out for various input combinations.</p>
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Shekarian, Seyed Mohammad Hossein, and Morteza Saheb Zamani. "A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust." Journal of Circuits, Systems and Computers 24, no. 08 (2015): 1550115. http://dx.doi.org/10.1142/s0218126615501157.
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During the last few years, hardware Trojan horses (HTHs) have become one of the most important threats to the security of very large scale integrated (VLSI) chips. Many efforts have been made to facilitate the process of HTH detection, mostly based on the power analysis of chips. The techniques would be more beneficial if trust-driven techniques are used during the system design. Whereas design for hardware trust (DFHT) is one of the fields of interest, most current approaches include ad-hoc and gate-level design techniques. This paper discusses the advantage of physical-level design approaches with integrated strategies for improving the HTH-detection probability. As a proof of concept, a placement technique is presented with the goal of enhancing the ability of HTH detection techniques based on local power signal analysis. Our results show that the background effects on power pads can be leveraged by a simple partitioning-based placement algorithm. Minimizing the background effects leads to a better Trojan-to-background-effect ratio and more (by about 1.7 times) Trojan detectability.
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Balodi, Deepak, and Rahul Misra. "Low Power Differential and Ring Voltage Controlled Oscillator Architectures for High Frequency (L-Band) Phase Lock Loop Applications in 0.35 Complementary Metal Oxide Semi Conductor Process." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 11, no. 01 (2019): 63–70. http://dx.doi.org/10.18090/samriddhi.v11i01.9.
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The design of a high frequency (L Band), low power (2.75mW) Phase Lock Loops with a 350nm Complementary Metal Oxide Semi Conductor (CMOS) technology has been represented. The comparison of Current Starved Voltage Controlled Oscillator (CSVCO) and Differential pair VCO is performed and analyzed for low power and high frequency analysis respectively. Each component of Phase Lock Loop (PLL) is designed with 350nm CMOS technology in Design Architect Integrated Circuit Station by Mentor Graphics (Eldo-Net) as simulator. In this paper both the standard configurations have been simulated under the same environment and results are analyzed for two most important Very Large Scale Integration (VLSI)constraints, Speed (High frequency range) and Power consumption. The high speed and locking performance of the Differential pair VCO has been evaluated against the lower power consumption benefit of CSVCO.
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N., Alivelu Manga. "Design of High-Speed Low Power Computational Blocks for DSP Processors." Revista Gestão Inovação e Tecnologias 11, no. 2 (2021): 1419–29. http://dx.doi.org/10.47059/revistageintec.v11i2.1768.
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In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.
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G, Shyamala, and G. R. Prasad. "Obstacle aware delay optimized rectilinear steiner minimum tree routing." Indonesian Journal of Electrical Engineering and Computer Science 16, no. 2 (2019): 640. http://dx.doi.org/10.11591/ijeecs.v16.i2.pp640-652.
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<p><span>This work presents a method to solve the problem of constructing Rectilinear Steiner Minimum Tree (RSMT) for a group of pins in the presence of obstacles. In modern </span><span>very large-scale integrated circuit</span><span> (VLSI) designs, the obstacles, generally blocks the metal and the device layer. Therefore routing on top of blockage is a possible solution but buffers cannot be placed over the obstacle. Modern VLSI design OARSMT construction has long wire length, which results in signal violation. To address this issue a slew constraint interconnect need to be considered in routing over obstacle. This is called the Obstacle-Avoiding Rectilinear Steiner minimum trees (OARSMT) problem with slew constraints over obstacles. The drawback of traditional OARSMT is that they only consider slew constraint, and delay constraints are neglected. It induces high routing resources overhead due to buffer insertion and does not solve global routing solution. This work presents an Obstacle Aware Delay Optimized Rectilinear Steiner Minimum Tree (OADORSMT) Routing to address the delay, slew constraint and reduce the routing resources. Experiments are conduced to evaluate the performance of proposed approach over existing approach in term of wire length and worst negative slack. The experiments are conducted for small and large nets considering fixed and varied obstacles and outcome shows the proposed efficiency over existing approaches. The OADORSMT is designed in such a way where it can be parallelized to obtain better efficiency.</span></p>
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NIRANJAN, VANDANA, ASHWANI KUMAR, and SHAIL BALA JAIN. "COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 08 (2014): 1450108. http://dx.doi.org/10.1142/s0218126614501084.
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In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.
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Qiao, Zhitong, Yan Han, Xiaoxia Han, et al. "ASIC Implementation of a Nonlinear Dynamical Model for Hippocampal Prosthesis." Neural Computation 30, no. 9 (2018): 2472–99. http://dx.doi.org/10.1162/neco_a_01107.
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A hippocampal prosthesis is a very large scale integration (VLSI) biochip that needs to be implanted in the biological brain to solve a cognitive dysfunction. In this letter, we propose a novel low-complexity, small-area, and low-power programmable hippocampal neural network application-specific integrated circuit (ASIC) for a hippocampal prosthesis. It is based on the nonlinear dynamical model of the hippocampus: namely multi-input, multi-output (MIMO)–generalized Laguerre-Volterra model (GLVM). It can realize the real-time prediction of hippocampal neural activity. New hardware architecture, a storage space configuration scheme, low-power convolution, and gaussian random number generator modules are proposed. The ASIC is fabricated in 40 nm technology with a core area of 0.122 mm[Formula: see text] and test power of 84.4 [Formula: see text]W. Compared with the design based on the traditional architecture, experimental results show that the core area of the chip is reduced by 84.94% and the core power is reduced by 24.30%.
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Saab, Youssef. "A Fast Clustering-Based Min-Cut Placement Algorithm With Simulated-Annealing Performance." VLSI Design 5, no. 1 (1996): 37–48. http://dx.doi.org/10.1155/1996/58084.
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Placement is an important constrained optimization problem in the design of very large scale (VLSI) integrated circuits [1–4]. Simulated annealing [5] and min-cut placement [6] are two of the most successful approaches to the placement problem. Min-cut methods yield less congested and more routable placements at the expense of more wire-length, while simulated annealing methods tend to optimize more the total wire-length with little emphasis on the minimization of congestion. It is also well known that min-cut algorithms are substantially faster than simulated-annealing-based methods. In this paper, a fast min-cut algorithm (ROW-PLACE) for row-based placement is presented and is empirically shown to achieve simulated-annealing-quality wire-length on a number of benchmark circuits. In comparison with Timberwolf 6 [7], ROW-PLACE is at least 12 times faster in its normal mode and is at least 25 times faster in its faster mode. The good results of ROW-PLACE are achieved using a very effective clustering-based partitioning algorithm in combination with constructive methods that reduce the wire-length of nets involved in terminal propagation.
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Cheang, Sin Man, Kwong Sak Leung, and Kin Hong Lee. "Genetic Parallel Programming: Design and Implementation." Evolutionary Computation 14, no. 2 (2006): 129–56. http://dx.doi.org/10.1162/evco.2006.14.2.129.
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This paper presents a novel Genetic Parallel Programming (GPP) paradigm for evolving parallel programs running on a Multi-Arithmetic-Logic-Unit (Multi-ALU) Processor (MAP). The MAP is a Multiple Instruction-streams, Multiple Data-streams (MIMD), general-purpose register machine that can be implemented on modern Very Large-Scale Integrated Circuits (VLSIs) in order to evaluate genetic programs at high speed. For human programmers, writing parallel programs is more difficult than writing sequential programs. However, experimental results show that GPP evolves parallel programs with less computational effort than that of their sequential counterparts. It creates a new approach to evolving a feasible problem solution in parallel program form and then serializes it into a sequential programif required. The effectiveness and efficiency of GPP are investigated using a suite of 14 well-studied benchmark problems. Experimental results show that GPP speeds up evolution substantially.
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Naidu, D. J. Samatha, and T. Mahammad Rafi. "HANDWRITTEN CHARACTER RECOGNITION USING CONVOLUTIONAL NEURAL NETWORKS." International Journal of Computer Science and Mobile Computing 10, no. 8 (2021): 41–45. http://dx.doi.org/10.47760/ijcsmc.2021.v10i08.007.
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Handwritten character Recognition is one of the active area of research where deep neural networks are been utilized. Handwritten character Recognition is a challenging task because of many reasons. The Primary reason is different people have different styles of handwriting. The secondary reason is there are lot of characters like capital letters, small letters & special symbols. In existing were immense research going on the field of handwritten character recognition system has been design using fuzzy logic and created on VLSI(very large scale integrated)structure. To Recognize the tamil characters they have use neural networks with the Kohonen self-organizing map(SOM) which is an unsupervised neural networks. In proposed system this project design a image segmentation based hand written character recognition system. The convolutional neural network is the current state of neural network which has wide application in fields like image, video recognition. The system easily identify or easily recognize text in English languages and letters, digits. By using Open cv for performing image processing and having tensor flow for training the neural network. To develop this concept proposing the innovative method for offline handwritten characters. detection using deep neural networks using python programming language.
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Mekala, Priyanka, Jeffrey Fan, Wen-Cheng Lai, and Ching-Wen Hsue. "Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform." Advances in Software Engineering 2013 (February 24, 2013): 1–13. http://dx.doi.org/10.1155/2013/707248.
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Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design. To accelerate the computation of the gesture recognition technique, an HW/SW implementation using field programmable gate array (FPGA) technology is presented in this paper. The major contributions of this work are: (1) a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL) to reduce memory consumption and load on the processor. (2) The testing part of the neural network algorithm is being hardwired to improve the speed and performance. The American Sign Language gesture recognition is chosen to verify the performance of the approach. Several experiments were carried out on four databases of the gestures (alphabet signs A to Z). (3) The major benefit of this design is that it takes only few milliseconds to recognize the hand gesture which makes it computationally more efficient.
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Nasution, Anggara, Raemon Syaljumairi, and Rusfandi Rusfandi. "Perancangan Sistem Informasi Untuk Perawatan Dan Perbaikan Modul Pratikum Berbasis Web." Elektron : Jurnal Ilmiah 10, no. 2 (2018): 22–27. http://dx.doi.org/10.30630/eji.10.2.74.
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Microprocessor and microcontroller laboratories are type III laboratories that are in the electronics engineering study program majoring in electrical engineering, this laboratory serves the activities of student practices for microprocessor system courses, microcontroller systems and interfaces I and II and very large scale intergration (VLSI) programmable logic devices and programmable electronics. Laboran as manager and person in charge of the laboratory, every month submits reports on equipment support facilities and practice modules made manually to the head of the laboratory. Every day the laboratory staff must examine all equipment activities one by one such as computers and practice modules to find out the latest conditions. Seeing the problems above, we need a system solution that can provide fast, accurate, complete and integrated information as a whole. The purpose of this study is to produce an information system design for maintenance and repairs to microprocessor and microcontroller laboratories. The method used in this study analyzes the current system to create a conceptual model so as to produce a database diagram. Next, the design of the display includes the design of the application interface such as the reporter display, laboratory performance reports etc. To further maximize laboratory use and quality teaching and learning is expected that students, lecturers and staff will also participate by reporting damage to supporting facilities at the microprocessor and microcontroller laboratory.
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Bibilo, P. N., and V. I. Romanov. "Minimization of Binary Decision Diagrams for Systems of Completely Defined Boolean Functions using Algebraic Representations of Cofactors." INFORMACIONNYE TEHNOLOGII 27, no. 8 (2021): 395–408. http://dx.doi.org/10.17587/it.27.395-408.
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In design systems for digital VLSI (very large integrated circuits), the BDD is used for VLSI verification, as well as for technologically independent optimization, performed as the first stage in the synthesis of logic circuits in various technological bases. BDD is an acyclic graph defining a Boolean function or a system of Boolean functions. Each vertex of this graph corresponds to the complete or reduced Shannon expansion formula. Having constructed BDD representation for systems of Boolean functions, it is possible to perform additional logical optimization based on the proposed method of searching for algebraic representations of cofactors (subfunctions) of the same BDD level in the form of a disjunction or conjunction of other cofactors of this BDD level. The method allows to reduce the number of literals by replacing the Shannon expansion formulas with simpler formulas that are disjunctions or conjunctions of cofactors, and to reduce the number of literals in specifying a system of Boolean functions. The number of literals in algebraic multilevel representations of systems of fully defined Boolean functions is the main optimization criterion in the synthesis of combinational circuits from library logic gates.
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Murarka, S. P., J. Steigerwald, and R. J. Gutmann. "Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing." MRS Bulletin 18, no. 6 (1993): 46–51. http://dx.doi.org/10.1557/s0883769400047321.
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Continuing advances in the fields of very-large-scale integration (VLSI), ultralarge-scale integration (ULSI), and gigascale integration (GSI), leading to the continuing development of smaller and smaller devices, have continually challenged the fields of materials, processes, and circuit designs. The existing metallization schemes for ohmic contacts, gate metal, and interconnections are inadequate for the ULSI and GSI era. An added concern is the reliability of aluminum and its alloys as the current carrier. Also, the higher resistivity of Al and its use in two-dimensional networks have been considered inadequate, since they lead to unacceptably high values of the so-called interconnection delay or RC delay, especially in microprocessors and application-specific integrated circuits (ICs). Here, R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the RC delay must be reduced to such a level that the contribution of RC to switching delays (access time) becomes a small fraction of the total, which is a sum of the inherent device delay associated with the semiconductor, the device geometry and type, and the RC delay.
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Wang, Guoqing, He Chen, and Yizhuang Xie. "An Efficient Dual-Channel Data Storage and Access Method for Spaceborne Synthetic Aperture Radar Real-Time Processing." Electronics 10, no. 6 (2021): 662. http://dx.doi.org/10.3390/electronics10060662.
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With the development of remote sensing technology and very large-scale integrated circuit (VLSI) technology, the real-time processing of spaceborne Synthetic Aperture Radar (SAR) has greatly improved the ability of Earth observation. However, the characteristics of external memory have led to matrix transposition becoming a technical bottleneck that limits the real-time performance of the SAR imaging system. In order to solve this problem, this paper combines the optimized data mapping method and reasonable hardware architecture to implement a data controller based on the Field-Programmable Gate Array (FPGA). First of all, this paper proposes an optimized dual-channel data storage and access method, so that the two-dimensional data access efficiency can be improved. Then, a hardware architecture is designed with register manager, simplified address generator and dual-channel Double-Data-Rate Three Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) access mode. Finally, the proposed data controller is implemented on the Xilinx XC7VX690T FPGA chip. The experimental results show that the reading efficiency of the data controller proposed is 80% both in the range direction and azimuth direction, and the writing efficiency is 66% both in the range direction and azimuth direction. The results of a comparison with the recent implementations show that the proposed data controller has a higher data bandwidth, is more flexible in its design, and is suitable for use in spaceborne scenarios.
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Bibilo, P. N., and V. I. Romanov. "Minimization of binary decision diagrams for systems of completely defined Boolean functions using Shannon expansions and algebraic representations of cofactors." Informatics 18, no. 2 (2021): 7–32. http://dx.doi.org/10.37661/1816-0301-2021-18-2-7-32.
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In the systems of digital VLSI design (Very Large Integrated Circuits), the BDD (Binary Decision Diagram) is used for VLSI verification, as well as for technologically independent optimization as the first stage in the synthesis of logic circuits in various technological bases. The BDD is an acyclic graph defining a Boolean function or a system of Boolean functions. Each vertex of this graph corresponds to the complete or reduced Shannon expansion formula. When BDD representation for systems of Boolean functions is constructed, it is possible to perform additional logical optimization based on the proposed method of searching for algebraic representations of cofactors (subfunctions) of the same BDD level in the form of a disjunction, conjunction either exclusive-or of cofactors of the same level or lower levels of BDD. A directed BDD graph for a system of functions is constructed on the basis of Shannon expansion of all component functions of the system by the same permutation of variables. The method allows to reduce the number of literals by replacing the Shannon expansion formulas with simpler formulas that are disjunctions or conjunctions of cofactors, and to reduce the number of literals in specifying a system of Boolean functions. The number of literals in algebraic multilevel representations of systems of fully defined Boolean functions is the main optimization criterion in the synthesis of combinational circuits from librarian logic elements.
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Kumar Sharma, Devendra, Brajesh Kumar Kaushik, and R. K. Sharma. "Impact of driver size and interwire parasitics on crosstalk noise and delay." Journal of Engineering, Design and Technology 12, no. 4 (2014): 475–90. http://dx.doi.org/10.1108/jedt-08-2012-0036.
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Purpose – The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay. Design/methodology/approach – The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13 μm, 1.5 V technology node. Findings – This paper observes the contradictory effects of coupling parasitics on wire propagation delay; however, the effect on peak noise is of a different kind. Further, this paper shows that the driver size exhibits opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance; thus, the optimization of delay is carried out. Originality/value – The effects of driver sizing and interwire parasitics are analyzed through simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing very large scale integration (VLSI) interconnects.
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Khursheed, Afreen, and Kavita Khare. "Designing dual-chirality and multi-Vt repeaters for performance optimization of 32 nm interconnects." Circuit World 46, no. 2 (2020): 71–83. http://dx.doi.org/10.1108/cw-06-2019-0060.
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Purpose This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm. Design/methodology/approach Usually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-Vt transistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control. Findings An unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (Vt) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes. Originality/value Result analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.
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Kumar, K. R. Lakshmi, R. A. Hadaway, M. A. Copeland, and M. I. H. King. "A precision design technique for analog very large scale integration." Canadian Journal of Physics 63, no. 6 (1985): 702–6. http://dx.doi.org/10.1139/p85-109.
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A study of the matching characteristics of components available in a CMOS VLSI technology is reported. This examination has been extended to produce a design methodology for precision analog functions in VLSI by choosing a digital-to-analog converter as an example. The major emphasis of the paper will be on the device and technological aspects of the design approach.
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Venkatapathi Naidu, Rayapati, and S. Mahapatra. "Very large scale integrated CMOS buffer design." Microelectronics Reliability 29, no. 6 (1989): 1021–33. http://dx.doi.org/10.1016/0026-2714(89)90027-9.
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Signorini, Jacqueline. "Integrated design tools for very large scale cellular architectures." Microprocessing and Microprogramming 31, no. 1-5 (1991): 37–42. http://dx.doi.org/10.1016/s0165-6074(08)80040-3.
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Katircioglu, Haluk, JohnA De Beule, Debaditya Mukherjee, and GaryC Whitlock. "4932028 Error log system for self-testing in very large scale integrated circuit (VLSI) units." Microelectronics Reliability 31, no. 2-3 (1991): viii. http://dx.doi.org/10.1016/0026-2714(91)90267-b.
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Mukhopadhyay, Abhijit Kumar. "A Low Power Digital Binary Magnitude Comparator Design for Very Large Scale Integration Applications." Advanced Science, Engineering and Medicine 12, no. 6 (2020): 825–30. http://dx.doi.org/10.1166/asem.2020.2655.
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This paper reports two designs of low power digital binary magnitude comparator based on static complementary CMOS logic style. The designs make use of recently reported latest XNOR gate designs. The comparator designs proposed here are easily scalable for higher order bits and thus highly suitable for VLSI applications. Mathematical equations establishing the relation between input bit width and transistor count of the magnitude comparators have also been derived in this paper. For a 64 bit magnitude comparator, the designs proposed in this paper outperform an existing design by 12.17% and 10.42% in terms of transistor requirement and 14.81% and 11.78% in terms of average power consumption.
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Boychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky, and Pavel Nekrasov. "Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices." Facta universitatis - series: Electronics and Energetics 28, no. 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.
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Total ionizing dose (TID) effects and radiation tests of complex multifunctional Very-large-scale integration (VLSI) integrated circuits (ICs) rise up some particularities as compared to conventional ?simple? ICs. The main difficulty is to organize informative and quick functional tests directly under irradiation. Functional tests approach specified for complex multifunctional VLSI devices is presented and the basic radiation test procedure is discussed in application to some typical examples.
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Rajeswari, R. "Design and Analysis of Various Standard Multipliers Using Low Power Very Large Scale Integration (VLSI)." International Journal of MC Square Scientific Research 4, no. 1 (2012): 48–57. http://dx.doi.org/10.20894/ijmsr.117.004.001.007.
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van Schaik, André, and Ray Meddis. "Analog very large-scale integrated (VLSI) implementation of a model of amplitude-modulation sensitivity in the auditory brainstem." Journal of the Acoustical Society of America 105, no. 2 (1999): 811–21. http://dx.doi.org/10.1121/1.426270.
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Sedaghat, Reza, and Anirban Sengupta. "Rapid exploration of cost-performance tradeoffs using dominance effect during design of hardware accelerators." Facta universitatis - series: Electronics and Energetics 27, no. 3 (2014): 317–28. http://dx.doi.org/10.2298/fuee1403317s.
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Modern Very Large Scale Integration (VLSI) designs require a tradeoff between cost efficiency and performance (circuit speed). Furthermore, the Design Space Exploration (DSE) of the cost-performance tradeoffs for the multi objective VLSI designs should also be fast and efficient in nature. This paper presents a novel accelerated DSE approach for the exploration of cost-performance tradeoffs of modular multi (trio parametric. viz. cost, execution time and power consumption) objective VLSI hardware accelerators using hierarchical criterion analysis. The selection of the final design point is made after the tradeoffs are explored using the proposed approach. Results of the proposed approach when applied to various benchmarks yielded significant acceleration in the exploration process compared to current existing approaches with multi parametric objective.
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Beck, Anthony, Franziska Obst, Mathias Busek, et al. "Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration." Micromachines 11, no. 5 (2020): 479. http://dx.doi.org/10.3390/mi11050479.
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The interest in large-scale integrated (LSI) microfluidic systems that perform high-throughput biological and chemical laboratory investigations on a single chip is steadily growing. Such highly integrated Labs-on-a-Chip (LoC) provide fast analysis, high functionality, outstanding reproducibility at low cost per sample, and small demand of reagents. One LoC platform technology capable of LSI relies on specific intrinsically active polymers, the so-called stimuli-responsive hydrogels. Analogous to microelectronics, the active components of the chips can be realized by photolithographic micro-patterning of functional layers. The miniaturization potential and the integration degree of the microfluidic circuits depend on the capability of the photolithographic process to pattern hydrogel layers with high resolution, and they typically require expensive cleanroom equipment. Here, we propose, compare, and discuss a cost-efficient do-it-yourself (DIY) photolithographic set-up suitable to micro-pattern hydrogel-layers with a resolution as needed for very large-scale integrated (VLSI) microfluidics. The achievable structure dimensions are in the lower micrometer scale, down to a feature size of 20 µm with aspect ratios of 1:5 and maximum integration densities of 20,000 hydrogel patterns per cm². Furthermore, we demonstrate the effects of miniaturization on the efficiency of a hydrogel-based microreactor system by increasing the surface area to volume (SA:V) ratio of integrated bioactive hydrogels. We then determine and discuss a correlation between ultraviolet (UV) exposure time, cross-linking density of polymers, and the degree of immobilization of bioactive components.
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IKEDA, SHOJI, HIDEO SATO, MICHIHIKO YAMANOUCHI, et al. "RECENT PROGRESS OF PERPENDICULAR ANISOTROPY MAGNETIC TUNNEL JUNCTIONS FOR NONVOLATILE VLSI." SPIN 02, no. 03 (2012): 1240003. http://dx.doi.org/10.1142/s2010324712400036.
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We review recent developments in magnetic tunnel junctions with perpendicular easy axis (p-MTJs) for nonvolatile very large scale integrated circuits (VLSIs). So far, a number of material systems such as rare-earth/transition metal alloys, L10-ordered ( Co, Fe )– Pt alloys, Co /( Pd, Pt ) multilayers, and ferromagnetic-alloy/oxide stacks have been proposed as electrodes in p-MTJs. Among them, p-MTJs with single or double ferromagnetic-alloy/oxide stacks, particularly CoFeB–MgO , were shown to have high potential to satisfy major requirements for integration.
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ETON, TOHRU, MASAYUKI YAMADA, and MICHIO MATSUBARA. "ELECTROTHERMAL VAPORIZATION ICP-MS(ETV-ICP-MS) DETERMINATION OF IMPURITIES IN PHOTORESIST FOR VERY LARGE SCALE INTEGRATED CIRCUIT(VLSI)." Analytical Sciences 7, Supple (1991): 1263–64. http://dx.doi.org/10.2116/analsci.7.supple_1263.
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Dash, Satyabrata, Sukanta Dey, Deepak Joshi, and Gaurav Trivedi. "Minimizing area of VLSI power distribution networks using river formation dynamics." Journal of Systems and Information Technology 20, no. 4 (2018): 417–29. http://dx.doi.org/10.1108/jsit-10-2017-0097.
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Purpose The purpose of this paper is to demonstrate the application of river formation dynamics to size the widths of power distribution network for very large-scale integration designs so that the wire area required by power rails is minimized. The area minimization problem is transformed into a single objective optimization problem subject to various design constraints, such as IR drop and electromigration constraints. Design/methodology/approach The minimization process is carried out using river formation dynamics heuristic. The random probabilistic search strategy of river formation dynamics heuristic is used to advance through stringent design requirements to minimize the wire area of an over-designed power distribution network. Findings A number of experiments are performed on several power distribution benchmarks to demonstrate the effectiveness of river formation dynamics heuristic. It is observed that the river formation dynamics heuristic outperforms other standard optimization techniques in most cases, and a power distribution network having 16 million nodes is successfully designed for optimal wire area using river formation dynamics. Originality/value Although many research works are presented in the literature to minimize wire area of power distribution network, these research works convey little idea on optimizing very large-scale power distribution networks (i.e. networks having more than four million nodes) using an automated environment. The originality in this research is the illustration of an automated environment equipped with an efficient optimization technique based on random probabilistic movement of water drops in solving very large-scale power distribution networks without sacrificing accuracy and additional computational cost. Based on the computation of river formation dynamics, the knowledge of minimum area bounded by optimum IR drop value can be of significant advantage in reduction of routable space and in system performance improvement.
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BINNS, M. D., F. J. CLOUGH, and S. C. J. GARTH. "AN ARCHITECTURE FOR FULLY INTEGRATED LARGE SCALE NEURAL NETWORKS." International Journal of Neural Systems 04, no. 04 (1993): 327–32. http://dx.doi.org/10.1142/s0129065793000262.
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To apply neural networks to many engineering applications, large networks will be required. Such networks are difficult to build using standard crystalline silicon technology due to limitations in both the fabrication and packaging processes. An architecture is proposed where amorphous silicon photoresistors are used to store the synaptic weights. A single plate of amorphous silicon is able to contain up to 100 million photoresistors, exploiting readily available fabrication technology. Using an external light source, each photoresistor can be individually adjusted allowing them to be configured as programmable fixed-value resistors. The processing compatibility of polysilicon and amorphous silicon allows the same glass substrate to be used for large-area integration of the photosensors, the analogue neural network and the neurons. The integration of the photosensors and the rest of the network may be used to alleviate the interface problem at the inputs resulting in a design with a very simple architecture that is both elegant and simple to fabricate. This paper describes such a design in which amorphous silicon technology is applied to neural network hardware.
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Ravikumar, D., Arun Raaza, V. Devi, and E. Gopinathan. "A genetic algorithm approach for global routing of VLSI circuits." International Journal of Engineering & Technology 7, no. 2.21 (2018): 394. http://dx.doi.org/10.14419/ijet.v7i2.21.12450.
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Very Large Scale Integrating (VLSI) design has the objectives of producing the layout for integrating circuits. The currently prevalent submicron regions require innovative, new physical design algorithms. Performance requirements have not seen before, become the significant features of such regions. The last ten years have been witnessing the feature of swelling success of Genetic Algorithms in their application to VLSI physical design. These algorithms are in spot light and the subject matter of study and examination. Routing problem is posed to a cost function which takes care of the total net length, the channel capacity exceedance and crosstalk. The Genetic algorithm is used for optimizing the cost function.