Academic literature on the topic 'VHDL language. eng'

The present cloud benefit measurements truly are stunning. By one year from now 80% of all new programming will be accessible as a cloud benefit, 58% of all Internet activity is guage to be video in only two years and before the decade’s over, 20 billion brilliant gadgets will be associated with the system. There is no uncertainty this will make difficulties wherever in the system. However, with this test, there regularly comes chance to go into the new optical system; never again is it only an asset for transporting bits. What’s more, it’s more than expanding limit. What’s new is the requirement for specialist organizations’ optical systems to end up increasingly “coordinated” and “consumable” enabling them to understand the undiscovered capability of their system. It ought to be a basic element of the developing cloud framework associating clients to their substance and applications. Security is a basic necessity for the system in light of the fact that the touchy data can be gotten to remotely and this makes the whole framework helpless against pernicious assaults. This paper exhibits the AES-256 calculation with respect to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL) for a secured information transmission in the Agile Optical Networks (AON).

Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE)to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly(at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has in spired us to design a low-cost memory tester. A low-cost memory fault detection tester with all the major fault detection algorithms that used in industry is modelled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) in this paper to support the need of the low-cost ATE memory tester. The fault detection algorithms modelled are MATS+ (Modified Algorithm Test Sequence), MATS++, March C, March C-, March X ,March Y, zero-one and checkerboard scan tests. PERL program is used to analyse the simulation results and a log file will be generated at the end of the memory test. Extensive simulation and experimental test results show that the memory tester modelled covers all the memory test algorithms used in the industry. The low-cost memory fault detection tester designed provides the 100% fault detection coverage for all memory defects.

This paper presents an open-source digital circuit of the coprocessor for an integer multiple-precision arithmetic (MPA). The purpose of this coprocessor is to support a central processing unit (CPU) by offloading computations requiring integer precision higher than 32/64 bits. The coprocessor is developed using the very high speed integrated circuit hardware description language (VHDL) as an intellectual property (IP) core. Therefore, it can be implemented within field programmable gate arrays (FPGAs) at various scales, e.g., within a system on chip (SoC), combining CPU cores and FPGA within a single chip as well as FPGA acceleration cards. The coprocessor handles integer numbers with precisions in the range 64 bits–32 kbits, with the limb size set to 64 bits. In our solution, the sign-magnitude representation is used to increase the efficiency of the multiplication operation as well as to provide compatibility with existing software libraries for MPA. The coprocessor is benchmarked in factorial ( n ! ), exponentiation ( n n ) and discrete Green’s function (DGF) computations on Xilinx Zynq-7000 SoC on TySOM-1 board from Aldec. In all benchmarks, the coprocessor demonstrates better runtimes than a CPU core (ARM Cortex A9) executing the same computations using a software MPA library. For sufficiently large input parameters, our coprocessor is up to three times faster when implemented in FPGA on SoC, rising to a factor of ten in DGF computations. The open-source coprocessor code is licensed under the Mozilla Public License.

Due to the rising number of cardiovascular diseases death, the monitoring of cardiac patients has become a primary objective in the world. In this context, a fully FPGA-based system, for ECG signal monitoring and cardiac arrhythmia detection, has been proposed. The proposed QRS detection method is inspired by the Pan and Tompkins algorithm. It is optimized to be implemented in FPGA board Spartan 3 E (Nexys 2) using the VHDL language on the Xilinx ISE 14.2. In order to evaluate the effectiveness and reliability of our system, three comparative studies have been performed. The first comparison targeted the different results obtained with a floating-point representation under Matlab on one hand, and a fixed point representation under Xilinx ISE on the other hand, both using the MIT-BIH arrhythmia database records. The second comparison concerns the results obtained from the records of eight preselected subjects, with a commercialized electronic armband device ROMED BP-WR20 in a real-time test. The third is a comparison between the performance of our proposed method with the recent works in terms of reducing the FPGA resources list. The full embedded system has been realized completely from the signal acquisition to the display using the analog discovery device. The designed architecture has been validated using records obtained from the Massachusetts Institute of Technology — Beth Israel Hospital (MIT-BIH) arrhythmia database. It has also been validated in real-time via the analog discovery device. The overall accuracy and sensitivity are obtained as 97.6% and 97.3%, respectively.

We describe the design of an undergraduate compilers course for computer engineering students in which the projectis to write a simulator and synthesizer for (a subset of) VHDL. The traditional project for such a course is to write a compiler for (a subset of) some procedural programming language. The choice of source language is superficially intended to drive student engagement for computer engineers. The main pedagogical advantage of this project is that item bodies a learning progression: repetition with increasing complexity.This project involves two additional languages: a regular language for boolean waveforms (used for circuit simulator inputand output), and a context-free language for boolean formulas. Parsing and transformations are performed on these simpler languages before attempting them on the subset of VHDL. At the end of the project the students can simulate and synthesize simple circuits such as a ripple-carry adder or a multiplexer.

Under water systems use processor based rooted systems to provide control and guidance to the under water vehicles. They obtain target and vehicle dynamics data from sensors and gyros, and process this data as per control and guidance algorithms to generate control and guidance parameters to the actuation system. Traditionally x86 families are being used in these systems in amassing to memory, I/Os and other peripherals being on the card. The recent developments in FPGA (Field Programmable Gate Array) technology has made pavement to use superior FPGAs with IP cores to develop under water systems. The modern FPGA devices include 32-bit Power PC processor, memory blocks and programmable area to comprise peripheral blocks. Under water systems developed out of the FPGA cores are definitely have several advantages like, saving the card size (FPGA accommodates several of the components in addition to the processor), flexibility to adopt changes in design (as FPGA can be programmed by the end user), preventing obsolescence of components. Building an under water systems based on FPGA IP cores is an innovative and hottest technological demonstration with several advantages to prophesy. The present work describes the dwindling in power consumption and size of the Under Water System. This work will also be productive to CSS Division of NSTL in designing and miniaturizing embedded systems such as MCS, MDAC etc. used in marine systems. The present work describes the mellowness of under water system relevance in Power PC Based FPGA using FPGA IP Cores. This work includes understanding the design flow of EDK and learns about various IP Cores Provided by Xilinx EDK 10.1. The underwater system application has been implemented in ‘C’ language by using Xilinx Device Drivers. A custom logic in VHDL has been developed for truncating extra bits of ADC. In Xilinx ISE10.1 project navigator the developed VHDL Code has been integrated with C. The combined bit file generated has been downloaded into Xilinx Virtex-II Pro FPGA Proto Board.

FIR (Finite Impulse Response) filters play a significant role in the field of Digital Signal Processing (DSP) to eliminate noise suppression in Electro Cardio Graph (ECG), Imaging devices and the signal stored in analog media. So filter evaluation is accomplished to reduce the noise level. The Filter passes only the desired frequency to pass thereby reducing distortion in the processed signal during measurement. The FIR filter comprises of basic units like adders, multipliers and the delay element for its operations.FIR and IIR are the two types of digital filters chosen based on the range of inputs, complexity and size requirement. Multipliers and adders play a vital role in deterring the performance of FIR filter. In this work, we design and analyze different multiplier and adder for high-performance Fir filter implementation. The Vedic Mathematics is the methods containing 16 Sutras to aid fast mental calculations. In this work, we propose modified Anurupye Vedic multiplier methods with Kogge Stone fast adder for implementation in the direct form FIR filter. This approach provides 1.5% decrease in delay and 10.2% reduced in power, hence increasing speed marginally than previous methods. Along with low power consumption in Very High-Speed Hardware Description Language (VHDL), all the adders and the multiplier topologies are Synthesized using (Xilinx Spartan – 6 FPGA) Trainer Kit and the proposed 8 – Tap FIR filter is executed using this Board

Resumo: Este trabalho trata da análise, desenvolvimento e implementação de um estágio Pré- Regulador Retificador Boost de alto fator de potência, para servir como fonte de alimentação para sistemas de iluminação fluorescente multi-lâmpadas, com potência de até 1.200 watts e com índices de qualidade tanto para a fonte de alimentação em corrente alternada quanto para o sistema de iluminação. Este conversor será controlado de forma digital, através da técnica dos valores médios instantâneos da corrente de entrada, desenvolvido através da linguagem de descrição de hardware VHDL (VHSIC HDL - Very High Speed Integrated Circuit Hardware Description Language) e implementado em um dispositivo FPGA (Field Programmable Gate Array) Spartan 3. Neste trabalho são apresentadas análises matemáticas, para a obtenção das funções de transferência pertinentes ao projeto dos compensadores, onde será aplicada uma metodologia de projeto capaz de projetar estes compensadores utilizando os diagramas de Bode, de módulo e de fase, e ainda contemplar as influencias dos dispositivos A/D, D/A e do processador digital de sinais. Isto eliminará os erros presentes nos projetos via aproximação e permitirá a diminuição das taxas de aquisição necessárias. O projeto é simulado e validado através da plataforma MatLab/Simulink, onde são apresentados resultados para o regime permanente e para transitórios de carga e da tensão de alimentação. Além disso, o controle do conversor através da linguagem VHDL, usando o modelo comportamental num estilo de projeto topdown, é apresentado e também validado através de simulação. Ademais, um sucinto estudo dos reatores eletrônicos convencionais é apresentado, com o intuito de sevir como base para o desenvolvimento de um filtro capaz de barrar as componentes em ca da corrente que circula entre o capacitor de saída... (Resumo completo clicar acesso eletrônico abaixo)
Abstract: This work presents the analysis, development and implementation of a single-phase power factor correction (PFC) pre-regulator rectifier, based on boost circuit, to act as a power supply for 1.200 watts multi-lamp fluorescent systems. The converter's digital control will be implemented using the average current mode control, based on VHDL language (VHSIC HDL - Very High Speed Integrated Circuit Hardware Description Language) and using a FPGA (Field Programmable Gate Array) device. In this work, the mathematical analyses of the converter's model are developed in order to obtain the proper transfer functions to design voltage and current digital compensators. The methodology applied at the digital design is capable to deal with the Bode diagrams and incorporate the analog to digital converter, the digital to analog converter and the digital signal processor, eliminating the uncertainties involving approximation methodologies and minimizing the necessity of high level of acquisition rates. This project is evaluated through MatLab/Simulink, showing results for steady-state operation and dynamics in order to analyze the converter's response. Moreover, the converter's digital control is based on VHDL language, using the behavioral modeling in a top-down project style, which is presented and validated through simulation results. In addition, the behavior of the conventional electronic ballasts are presented in order to help in the development of a filter, capable to impede the circulation of the AC components of the ballast current throught the feeding link, guaranteeing the continuous current conduction, among the boost capacitor and the electronic ballasts. Finally, this work presents the laboratorial development of this PFC with digital control, where the prototype was evaluated through experimental results.
Orientador: Carlos Alberto Canesin
Coorientador: Fabio Toshiaki Wakabayashi
Banca: Claudio Kitano
Banca: Arnaldo José Perin
Mestre

Orientador: Suely Cunha Amaro Mantovani
Banca: Nobuo Oki
Banca: Luis Gustavo Wesz da Silva
Resumo: Atualmente as empresas do setor elétrico deparam-se cada vez mais com as exigências do mercado energético sendo obrigadas a assegurarem aos seus clientes bons níveis de continuidade e confiabilidade no serviço de fornecimento da energia elétrica e também atender os índices de continuidade do serviço estabelecidos pela agência reguladora do setor elétrico (ANEEL - Agência Nacional de Energia Elétrica). Para alcançar estes objetivos além de investir na otimização dos seus sistemas de transmissão e distribuição, as empresas responsáveis têm investido na automação de suas operações, buscando alternativas que reduzam os tempos de interrupção por faltas permanentes nos sistemas de potência. Através de informações disponíveis em uma subestação, é possível estabelecer um procedimento para determinar e classificar condições de faltas, localizando o elemento de proteção acionado, e assim fornecer o apoio à tomada de decisão no ambiente de subestações de sistemas de distribuição de energia elétrica. Neste trabalho é proposta uma metodologia que fornece respostas rápidas (controle on line), para detecção e classificação de faltas em sistemas de distribuição de energia elétrica através de informações analógicas disponíveis em uma subestação, tais como amostras de sinais de tensões e correntes na saída dos alimentadores, com uma arquitetura reconfigurável paralela que usa dispositivos lógicos programáveis (Programables Logics Devices - PLDs) -FPGAs e a linguagem de descrição de hardware - VDHL (Very High Speed Integraded Circuit - VHSIC). Para validar o sistema proposto, foram gerados dados de forma aleatória, compatíveis com informações fornecidas em tempo real pelo sistema SCADA (supervisory control and data-acquisition) de uma subestação real. Os resultados obtidos com as simulações realizadas, mostram que a... (Resumo completo, clicar acesso eletrônico abaixo)
Abstract: Currently companies of the energy industry is facing increasingly with the requirements of the energy market are obliged to ensure their customers good levels of continuity in service and reliability of supply of electric energy and also meet the rates of continuity of service established by the agency regulator of the energy industry (ANEEL - National Electric Energy Agency). To achieve these goals than to invest in optimization of its transmission and distribution systems, the companies responsible have invested in automation of its operations, seeking alternatives that reduce the time of interruption by failures in the systems of permanent power. Through information available in a substation, it is possible to establish a procedure for identifying and classifying conditions of absence, finding the element of protection driven, and thus provide support for decision-making within the environment of substations to distribution systems for power. This work is proposed a methodology that provides quick answers (control online), for detection and classification of faults in distribution systems of electric energy through analog information available on a substation, such as samples for signs of tensions and currents in the output of feeders, with an architecture that uses parallel reconfigurable programmable logic devices (Programables Logics Devices - PLDs)-FPGAs and the language of description of hardware - VDHL (Very High Speed Circuit Integraded - VHSIC). To validate the proposed system, data were generated at random, consistent with information provided by the system in real time SCADA (supervisory control and data-acquisition) of a real substation. The results obtained with the simulations conducted, show that the proposed methodology, presents satisfactory results, and times of reasonable answers.
Mestre

Orientador: Eurípedes Guilherme de Oliveira Nóbrega
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecânica
Made available in DSpace on 2018-08-16T07:47:06Z (GMT). No. of bitstreams: 1 Raizer_Klaus_M.pdf: 2682241 bytes, checksum: 765c3dc138a1e4c9258fd0201cd56a8f (MD5) Previous issue date: 2010
Resumo: Este trabalho apresenta a implementação de um sistema de análise de sinais de ECGs (eletrocardiogramas) embarcado em FPGA (field programmable gate array), capaz de classificar cardiopatias. A análise de ECGs é de grande importância devido a sua natureza potencialmente não-invasiva, baixo custo e alta eficiência na identificação de patologias cardíacas. Visto que um sinal de ECG pode ser composto por horas de gravação da atividade cardíaca, uma abordagem computacional para a sua análise torna-se um instrumento valioso para a redução do tempo e dos erros de diagnóstico. No presente trabalho uma série de características são extraídas dos pulsos de ECG, que foram obtidos a partir dos sinais do banco de dados MIT-BIH, através da decomposição por transformada wavelet discreta. Essas características foram então utilizadas para treinar uma Rede Neural do tipo feedforward para discernir pulsos normais de pulsos anômalos. Uma versão da rede neural foi então programada em VHDL e em seguida implementada em um Kit da Xilinx modelo Spartan 3E para a classificação pulso a pulso dos sinais de ECG. As implicações dessa arquitetura são discutidas e os resultados são apresentados
Abstract: this work presents an implementation of an embedded ECG (electrocardiogram) signal analysis system using FPGA (field programmable gate array), capable of classifying cardiopathies. The importance of ECG analysis is mainly due to its potentially non-invasive nature, low cost and high efficiency to identify heart pathologies. Since a single ECG signal can be the record of hours of heart activity, a computational approach to its analysis is invaluable to reduce diagnostic errors and the time taken by the process. In the present work, features are extracted from ECG pulses, obtained from the MIT-BIH database, by decomposing them with the Discrete Wavelet Transform. These features are then used to train a Backpropagation Neural Network in order to discriminate normal ECG pulses from anomalous ones. The neural network is programmed in VHDL and uploaded into a Spartan 3E Xilinx development kit, which performs a pulse-by-pulse classification. The implications of such architecture are discussed and its results are presented
Mestrado
Mecanica dos Sólidos e Projeto Mecanico
Mestre em Engenharia Mecânica