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Relevant bibliographies by topics / VHDL (Very hardware description language)

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Academic literature on the topic 'VHDL (Very hardware description language)'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

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Journal articles on the topic "VHDL (Very hardware description language)"

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Yi, Zhao Xiang, Xiong Mei Zhang, Ning Li, and Xiao Dong Mu. "A Visual Dependency Analysis Method Based on VHDL." Applied Mechanics and Materials 738-739 (March 2015): 582–85. http://dx.doi.org/10.4028/www.scientific.net/amm.738-739.582.

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Modern complex circuits are described in very high speed integrated circuit hardware description language (VHDL) and difficult to verify. This paper proposes a systematic and visual dependency analysis method based on VHDL. The dependency relationships including control dependency, data dependency, signal control dependency and signal data dependency are defined. The entity dependency graph is presented and its generation algorithm, which searches the dependency relationships in hardware processes and between hardware processes, are developed. The experiment of a typical keyboard demonstrates that it is a visual and efficient method to analyze dependency relationships of VHDL for formal verification.

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Shiva, Sajjan G., and Judit U. Jones. "A VHDL Based Expert System for Hardware Synthesis." VLSI Design 1, no. 2 (January 1, 1994): 113–26. http://dx.doi.org/10.1155/1994/93168.

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This paper describes an expert system for Hardware Synthesis. Details of the target digital system are input to the expert system using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The VHDL representation is first translated to a knowledge representation scheme known as a ‘hologram’ which is a combination of rule, frame and semantic network representation schemes. The hologram representation of the target system is then input to the inference engine, which matches the target system to the Knowledge Base components and selects an appropriate set for implementation, and connects them creating a digital circuit. Some design examples are described. The expert system approach results in designs very close to designs from a human designer. In its present form, the system does not perform a design space exploration for alternate designs, but expects the designer to alter the VHDL representation, after observing the results from previous design cycles.

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Shetty, Mamtha. "Design of BPSK Modulator Using VHDL." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, no. 12 (October 23, 2014): 5247–52. http://dx.doi.org/10.24297/ijct.v13i12.5276.

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Binary Phase Shift Keying represents the simulation results of binary digital modulation schemes. Here for BASK and BPSK modulation techniques use FPGA algorithm. If multiplier block is used for multiplication bit stream with carrier signal, used time will rises. In addition using multiplier block obtained simulation results were analyzed and compared to other simulation results. Source consumptions of FPGA-based BASK modulation technique and BPSK modulation technique were compared. Also, for different modulation algorithm, source consumptions of BASK and BPSK modulation technique were analyzed using VHDL. Designed modulators using VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL) was realized on high speed FPGA (Field Program Programmable Gate Array). Because for used modulation technique data rate transfer is fairly important in wireless communication systems. The highest speed data rate transfer can be realized using fiber optic cables. In addition, BER (Bit Error Rate) of BASK and BPSK modulator was compared using MATLAB simulation program. Binary data rate is same for BPSK and BASK. BPSK and BASK modulations were designed on FPGA using VHDL hardware description language.

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Zhu, Juan, and Yue Chen. "Step Motor Control Based on FPGA." Applied Mechanics and Materials 397-400 (September 2013): 1226–29. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.1226.

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Design a step motor control system based on Field Programmable Gate Array (FPGA). Give the hardware circuit of this system and the program based on very high speed integrated circuit hardware description language (VHDL). Compared to step motor control system based on single chip microcomputer, the processing speed of this system is faster.

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Palanisamy, R., C. S. Boopathi, K. Selvakumar, and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (April 1, 2020): 1722. http://dx.doi.org/10.11591/ijece.v10i2.pp1722-1727.

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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.

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Palanisamy, R., and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (July 1, 2019): 81. http://dx.doi.org/10.11591/ijres.v8.i2.pp81-85.

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<p>This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.</p>

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Miriampally, Venkata Raghavendra. "Simulation of PCI Express™ Transaction Layer Using Hardware Description Language." International Journal of Informatics and Communication Technology (IJ-ICT) 4, no. 1 (April 1, 2015): 7. http://dx.doi.org/10.11591/ijict.v4i1.pp7-12.

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<p>PCI Express is a high-speed serial connection that operates more like a network than a bus.<strong> </strong>PCI Express will serve as a general purpose I/O interconnects for a wide variety of future computing and communications platforms.<strong> </strong>PCI Express (PCIe) is implemented with a split-transaction protocol that provides more bandwidth and is compatible with existing operating systems. PCI Express has three discrete logical layers: the Transaction Layer, the Data Link Layer, and the Physical Layer. This paper analyze and simulates the function of Transaction layer <strong> </strong>IP core in the System Level with top-down design method, wrote the codes to implement Transaction Layer using Very high speed hardware description language (VHDL) and provided the simulation results using Active HDL Simulation tool. The simulation result shows that the designed IP core meets the required protocol specifications for the proper functioning of PCI Express Transaction layer.</p><p> </p>

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Zhang, Zi Sheng, Chun Sheng Wang, Yi Wang, Zhan You Wang, and Deng Yuan Song. "Power and Vibration of Electrostatic Precipitator Control Based on FPGA." Advanced Materials Research 1037 (October 2014): 244–47. http://dx.doi.org/10.4028/www.scientific.net/amr.1037.244.

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In order to improve the automation level of the electrostatic precipitator, we used Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) language to compile, emulate and optimize the control system of power source and vibration. In the design of Quartus platform, we used EP1C3T144C8 Field Programmable Gate Array (FPGA) chip to realize high voltage power supply, alarm and protection system. We also realized the compilation and simulation test of each part’s function of 20 s rapping and 40 min rapping cycle. At the same time, we recorded the waveform of simulation. It demonstrated that the validity of the relevant VHDL compilation. We used this method to achieve the optimization control of the electrostatic precipitator operating parameters. It has a strong practicability.

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Zhang, Zi Sheng, Yi Wang, Chun Sheng Wang, Jin Cui, and Zhi Qiang Liu. "The Control of High Voltage Electrostatic Precipitator Based on EDA." Advanced Materials Research 910 (March 2014): 336–39. http://dx.doi.org/10.4028/www.scientific.net/amr.910.336.

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In order to achieve the automatic control of electrostatic precipitator (ESP) more efficiently and accurately, an ESP system combining hardware and software is designed. According to the requirement of the ESP system,the Electronic Design Automation (EDA) is introduced to the ESP control system and the system is divided into four modules.These sub-modules are designed and the simulation waveform of the system is ananalyzed,based on the Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) programming language and Quartus software.The results show that the security, flexibility and reliabity of the system is improved by using EDA as the control ,which is a great value for generalization.

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Shieh, Cheng Shion. "From Simulation to FPGA Control Circuit Implementation for Wind Power with Battery Charging." Advanced Materials Research 588-589 (November 2012): 777–80. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.777.

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While application of field-programmable gate array (FPGA) chip has been extensively investigated, the charging control is relatively unexplored. This paper proposes a flow chart of energy storage for wind power system with Lead-Acid battery whose charging control is constructed by Very High Speed Integrated Circuit Hardware Description Language (VHDL) code. This research focuses on the proposed digital control algorithm can be directly downloaded into field-programmable gate array (FPGA) chip after simulation finishing. This saves greatly time on hardware circuit design. A simulation is presented to illustrate the effectiveness of the proposed charging flow chart.

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Dissertations / Theses on the topic "VHDL (Very hardware description language)"

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Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

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Van, Tassel John Peter. "Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistant." Thesis, University of Cambridge, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.308190.

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Pan, Bi-Yu. "Hierarchical test generation for VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-09052009-040449/.

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Kapoor, Shekhar. "Process level test generation for VHDL behavioral models." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-05022009-040753/.

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Narayanaswamy, Sathyanarayanan. "Development of VHDL behavioral models with back annotated timing." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06112009-063442/.

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Joshi, Anand Mukund. "Behavioral delay fault modeling and test generation." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-07292009-090436/.

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Guardia, Filho Luiz Eduardo. "Sistema para controle de maquinas robotizadas utilizando dispositivos logicos programaveis." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259017.

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Orientador: Marconi Kolm Madrid
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-04T17:12:57Z (GMT). No. of bitstreams: 1 GuardiaFilho_LuizEduardo_M.pdf: 2405031 bytes, checksum: b724836217b8586950a9ffabcd235f35 (MD5) Previous issue date: 2005
Resumo: Este trabalho de mestrado teve o propósito de projetar e construir um sistema de hard-ware capaz de realizar o controle de máquinas robotizadas em tempo real. Foi dada uma abordagem usando técnicas de processamento paralelo e eletrônica reconfigurável com o uso de dispositivos lógicos programáveis. Mostrou-se em função dos resultados das implementações que o sistema proposto é eficiente para ser utilizado no controle de robôs baseado em modelos matemáticos complexos como cinemático direto/inverso, dinâmico e de visão artificial. Esse mesmo sistema prevê sua utilização para os quatro níveis hierárquicos envolvidos em plantas que se utilizam de controle automático: supervisão, tarefas, trajetória e servomecanismos. O sistema possui interfaces de comunicação USE e RS-232, conversores A/D e D/A, sistema de processamento de imagens (entradas e saídas de sinais de vídeo analógico), portas E/S, chaves e leds para propósito geral. A eficiência foi comprovada através de experimentações práticas utilizando sistemas robóticos reais como: sistema de um pêndulo acionado, robô redundante de 4GDL denominado Cobra, e solução em hardware de funções importantes no sentido da resolução dos modelos matemáticos em tempo real como funções transcendentais
Abstract: This work had as purpose the project and build of a hardware system with abilities to accomplish the real time control of robotic machines. It was given an approach using tech-niques of parallel processing and programmable electronics configuration with programmable logic devices. According to the implementation results, it was shown that this proposed sys-tem is efficient to be used for controlling robots based on complex mathematical models, like direct/inverse kinematics, dynamics and artificial vision. This system foresees its use for the four hierarchical levels involved in industrial plants that use automatic control: supervision, tasks, trajectory /path and servomechanisms. The system has USE and RS-232 communica-tion interfaces, A/D and D/A converters, image processing capabilities (with input/output for analog video signals), I/O ports, and switches and leds for general purpose. Its efficiency is demonstrated through practical experimentations using real robotic systems as: a driven pendu-lum system, a redundant 4 DOF robot called "Cobra", and a hardware solution for important functions in the sense of real time mathematical models computing, like the transcendental functions
Mestrado
Automação
Mestre em Engenharia Elétrica

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Beydoun, Ali. "Système de numérisation hautes performances à base de bancs de convertisseurs sigma-delta passe-bande." Paris 11, 2008. http://www.theses.fr/2008PA112066.

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Les systèmes de communications numériques mobiles tendent à intégrer de plus en plus d’applications (GSM, radio, TV, GPS, etc. ) tout en fonctionnant sur plusieurs normes. Cette évolution implique une reconfigurabilité en ligne des récepteurs à l’aide d’une programmation logicielle justifiant le terme de radio-logicielle. Par ailleurs, les normes de communication actuelles exigent des débits élevés. Les bandes de fréquence nécessaires sont donc étendues (jusqu’à plusieurs centaines de mégahertz). Ainsi, les systèmes de réception doivent être à très large bande. La reconfigurabilité logicielle implique la numérisation des signaux au plus près de l’antenne, les hauts débits imposent une large bande passante. Une solution pour répondre à ces exigences est l’utilisation de convertisseurs analogique-numérique à base de modulateurs sigma-delta en parallèle. Parmi les architectures possibles, on compte : l’architecture à entrelacement temporel, l’architecture à base de modulation de Hadamard et l’architecture à décomposition fréquentielle. Ces architectures sont susceptibles de traiter toute la bande de fréquences possible. Cependant, pour une norme donnée, le bon fonctionnement du récepteur ne nécessite pas la conversion de la bande totale à la résolution maximale. La largeur de bande pourra être adaptée au signal à convertir. Au cours de ce travail de thèse, nous avons proposé une nouvelle architecture de numérisation large bande constituée de modulateurs sigma-delta en parallèle, fonctionnant sur le principe de la décomposition fréquentielle FBD (Frequency Band Decomposition). Les modulateurs sont de type passe-bande à temps continu afin de permettre le fonctionnement à des fréquences élevées. Pour la partie numérique, nous avons développé un système de reconstruction du signal numérique adapté à la sortie des différents modulateurs. L’incertitude due aux dispersions technologiques dans la réalisation de circuits analogiques est l’une des causes de la dégradation de la précision des modulateurs sigma-delta à temps continu. Afin d’adapter l’architecture aux imperfections de la partie analogique, nous proposons une modification de cette architecture en ajoutant deux modulateurs supplémentaires (EFBD Extended Frequency Band Decomposition). Grâce à cette architecture à bande étendue, combinée à des algorithmes de calibration, nous corrigeons les erreurs sur le module et la phase introduites par les dispersions analogiques. Finalement, nous avons implanté le traitement numérique dans une technologie CMOS 0. 12 μm afin d’évaluer la surface nécessaire pour le traitement numérique. Cette étude théorique a permis de proposer des solutions nouvelles de conversion large bande et de les valider en vue d’une implémentation future sous forme intégrée
Mobile Communication systems tend to integrate more and more applications (GSM, radio, TV, GPS, etc. ) and different standards (GSM, UMTS, WIMAX,. . ). This evolution requires a flexible receiver able, with a single channel, to deal with each different standard and application. The principle of such a receiver is based on the concept of the Software Radio. The basic idea of the software radio is to integrate the analog-to-digital converter in the channel receiver directly after the antenna. This allows the receiver to adapt itself to different standards by reprogramming the functionality of all digital components in the channel receiver. However, the current standard communications require high flow, so the useful signal frequency bands must be extended (up to several hundred megahertz). Therefor, the A/D bandwidth must be expanded. One way to meet these requirements is the use of analog-to-digital converters based on parallel sigma-delta modulators. Three architectures were proposed on the state of the art based on this principle : Time Interleaved Sigma-Delta (TIΣΔ), Parallel Sigma-Delta (ΠΣΔ) based on Hadamard modulation and Frequency Band Decomposition (FBD). These architectures convert the entire frequency band. However, for multistandard applications, a useful signal has a limited bandwidth and thus the conversion of the entire frequency band is not optimal. This thesis proposes a new architecture for bandpass A/D converter using parallel band pass sigma-delta modulator based on the principle of the frequency band decomposition. We have used continuous time modulators to reach the high operating frequency. Moreover, a digital reconstruction system was proposed to reconstruct the digital input signal using all modulators output. Technological dispersions on analog components decrease considerably the expected resolution of the converter. Actually, they shift resonator central frequencies of the modulator from their nominal value. This leads to mismatch the digital reconstruction system already calibrated to work with nominal values. In order to overcome this problem, the idea is to extend the usual FBD architecture by adding two additional modulators (EFBD Extended Frequency Band Decomposition). The EFBD architecture allows a 5% relative error on central frequencies without a large degradation of the resolution. Moreover, three calibration algorithms were developed to achieve the expected resolution and correct mistakes on the amplitude and the phase with the new configuration (EFBD). Finally, the digital reconstruction system was implemented in 0. 12 μm CMOS technology in order to evaluate their performances in term of area and maximum operating frequency

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Shah, Sandeep R. "A framework for synthesis from VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-03022010-020143/.

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Wright, Philip A. "Rapid development of VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-11102009-020056/.

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Books on the topic "VHDL (Very hardware description language)"

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VHDL starter's guide. Upper Saddle River, N.J: Prentice Hall, 1998.

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VHDL: A starter's guide. 2nd ed. Upper Saddle River, N.J: Pearson/Prentice Hall, 2005.

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Reichardt, Jürgen. VHDL-synthese: Entwurf Digitaler Schaltungen und Systeme. Berlin: De Gruyter, 2015.

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Chang, K. C. Digital design and modeling with VHDL and synthesis. Los Alamitos, Calif: IEEE Computer Society Press, 1997.

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Barski, Mariusz. Układy cyfrowe: Podstawy projektowania i opis w języku VHDL. Gdańsk: Wydawn. Politechniki Gdańskiej, 2007.

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Kamat, Rajanish K. Harnessing VLSI System Design with EDA Tools. Dordrecht: Springer Science+Business Media B.V., 2012.

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Computer Systems Laboratory (U.S.), ed. VHSIC hardware description language (VHDL). Gaithersburg, MD: U.S. Dept. of Commerce, Technology Administration, National Institute of Standards and Technology, Computer Systems Laboratory, 1995.

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A VHDL primer. Englewood Cliffs, NJ: Prentice Hall, 1992.

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A VHDL primer. 3rd ed. Upper Saddle River, N.J: Prentice Hall PTR, 1999.

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A VHDL primer. Englewood Cliffs, N.J: Prentice Hall PTR, 1995.

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Book chapters on the topic "VHDL (Very hardware description language)"

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Pierre, Laurence. "VHDL: A Hardware Description Language and its Simulation Semantics." In Software Specification Methods, 113–30. London: Springer London, 2001. http://dx.doi.org/10.1007/978-1-4471-0701-9_7.

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Bazil Raj, A. Arockia. "Digital Circuit Design with Very-High-Speed Integrated Circuit Hardware Description Language." In FPGA-Based Embedded System Developer's Guide, 23–89. Boca Raton : Taylor & Francis, CRC Press, 2018.: CRC Press, 2018. http://dx.doi.org/10.1201/9781315156200-2.

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Bazil Raj, A. Arockia. "Floating-Point Computations with Very-High-Speed Integrated Circuit Hardware Description Language and Xilinx System Generator (SysGen) Tools." In FPGA-Based Embedded System Developer's Guide, 547–624. Boca Raton : Taylor & Francis, CRC Press, 2018.: CRC Press, 2018. http://dx.doi.org/10.1201/9781315156200-10.

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Navabi, Zainalabedin, and Naghmeh Karimi. "VHDL-AMS Hardware Description Language." In The VLSI Handbook, Second Edition, 91–1. CRC Press, 2006. http://dx.doi.org/10.1201/9781420005967.ch91.

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Oczko, Andreas, and Christel Oczko. "Putting Different Simulation Models Together – The Simulation Configuration Language VHDL/S." In Computer Hardware Description Languages and their Applications, 115–29. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-444-89208-9.50011-9.

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El Oualkadi, Ahmed. "S-? Fractional-N Phase-Locked Loop Design Using HDL and Transistor-Level Models for Wireless Communications." In Advances in Wireless Technologies and Telecommunication, 99–118. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-4666-0083-6.ch005.

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This chapter presents a systematic design of a S-? fractional-N Phase-Locked Loop based on hardware description language behavioral modeling. The proposed design consists of describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The description language models of critical PLL blocks have been described in VHDL-AMS, which is an IEEE standard, to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the overall system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models in the frequency range around 2.45 GHz for wireless applications.

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Yahya, Abid, Farid Ghani, R. Badlishah Ahmad, Mostafijur Rahman, Aini Syuhada, Othman Sidek, and M. F. M. Salleh. "Development of an Efficient and Secure Mobile Communication System with New Future Directions." In Handbook of Research on Computational Science and Engineering, 219–38. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-61350-116-0.ch010.

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This chapter presents performance of a new technique for constructing Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) encrypted codes based on a row division method. The new QC-LDPC encrypted codes are flexible in terms of large girth, multiple code rates, and large block lengths. In the proposed algorithm, the restructuring of the interconnections is developed by splitting the rows into subrows. This row division reduces the load on the processing node and ultimately reduces the hardware complexity. In this method of encrypted code construction, rows are used to form a distance graph. They are then transformed to a parity-check matrix in order to acquire the desired girth. In this work, matrices are divided into small sub-matrices, which result in improved decoding performance and reduce waiting time of the messages to be updated. Matrix sub-division increases the number of sub-matrices to be managed and memory requirement. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip.

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Liu, Jun, YaDong Zhu, XiaoPing Yang, JinLi Liu, and Zhen Wei. "Practical teaching reform in the VHDL (Very High Speed Integrated Circuit Description Language) course based on the idea of CDIO (Concept, Design, Implementation, and Operation)." In Frontiers in Computer Education, 137–40. CRC Press, 2015. http://dx.doi.org/10.1201/b18444-31.

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Conference papers on the topic "VHDL (Very hardware description language)"

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Wenzl, Matthias, Peter Roessler, and Andreas Puhm. "Checking Application Level Properties Using Assertion Synthesis." In ASME 2019 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/detc2019-97950.

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Abstract This work presents a proof-of-concept of a new approach on automatic generation of digital hardware that is able to check application-level properties of an embedded system such as a faulty system behavior at runtime. The approach makes use of assertion-based verification setups that today are very common in the area of digital hardware design with, however, the sole focus on logic simulation. Thus, a PSL-to-VHDL compiler is introduced that generates VHDL (Very High Speed Integrated Circuit Description Language) code out of PSL (Property Specification Language) assertions which can be further processed by a traditional digital logic synthesis tool. That way, runtime checker units can be automatically generated with little effort because of the already existing assertion-based test benches. Furthermore, a model railway demonstrator is presented herein as an example for a safety-critical application to prove the proposed tool flow on a use case. Implementation results based on that use case are discussed. Finally, the paper concludes with a brief outlook on related future work of the authors.

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Gray, F., and James Armstrong. "Reutilization of VHDL testbench and library components (VHSIC Hardware Description Language)." In 10th Computing in Aerospace Conference. Reston, Virigina: American Institute of Aeronautics and Astronautics, 1995. http://dx.doi.org/10.2514/6.1995-1035.

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Binns, R. J. "High-level design of analogue circuitry using an analogue hardware description language." In IEE Colloquium on Mixed-Signal AHDL/VHDL Modelling and Synthesis. IEE, 1997. http://dx.doi.org/10.1049/ic:19971118.

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Yuguo, Sun, and Chen Jin. "Embedded Fault Tree Logic Implementation Based on Complex Programmable Logic Device." In ASME 2005 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/detc2005-84886.

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To meet the requirements of an embedded mechanical fault diagnosis system development, a fault tree implementation and dynamic modification method based on CPLD (Complex Programmable Logic Device) is investigated experimentally. The mechanism of fault tree logic calculation in the CPLD chip is presented. The fault logic tree is modeled by VHDL (VHSIC Hardware Description Language) and logic graphic, respectively. The effects of the bottom events on the logic result are simulated in Max + plus II platform. The fault tree logic is downloaded into the EPM7064SLC44-10 chip by ISP (In System Programmable) technology. And evaluated in terms of power consumption, system’s volume and design flexibility. The study results show that CPLD is suit to the fault tree’s construction, contributed by the chip’s outstanding ISP function and programmable logic function. And the fault tree logic synthesis and the chip resource optimization need to be further investigated.

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Reports on the topic "VHDL (Very hardware description language)"

1

Chung, Moon Jung. Parallel Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) Simulation for Performance Modeling. Fort Belvoir, VA: Defense Technical Information Center, March 1999. http://dx.doi.org/10.21236/ada372678.

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2

Mills, Michael T. Proposed Object Oriented Programming (OOP) Enhancements to the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). Fort Belvoir, VA: Defense Technical Information Center, August 1993. http://dx.doi.org/10.21236/ada274004.

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3

Mills, Michael T. A Key Element Toward Concurrent Engineering of Hardware and Software: Binding Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) with Ada 95. Fort Belvoir, VA: Defense Technical Information Center, October 1994. http://dx.doi.org/10.21236/ada294469.

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4

Aylor, James, Robert Klenke, Ron Waxman, Paul Menchini, Jack Stinson, and Bill Anderson. VHSIC Hardware Description Language (VHDL) 200X Requirements Report/Survey. Fort Belvoir, VA: Defense Technical Information Center, November 1999. http://dx.doi.org/10.21236/ada406178.

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5

Federal Information Processing Standards Publication: VHSIC hardware description language (VHDL). Gaithersburg, MD: National Institute of Standards and Technology, 1995. http://dx.doi.org/10.6028/nist.fips.172-1-1995.

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