Relevant bibliographies by topics / VHDL (Very hardware description language)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'VHDL (Very hardware description language)'

Author: Grafiati
Published: 4 June 2021
Last updated: 4 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'VHDL (Very hardware description language).'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "VHDL (Very hardware description language)"

1

Yi, Zhao Xiang, Xiong Mei Zhang, Ning Li, and Xiao Dong Mu. "A Visual Dependency Analysis Method Based on VHDL." Applied Mechanics and Materials 738-739 (March 2015): 582–85. http://dx.doi.org/10.4028/www.scientific.net/amm.738-739.582.

Full text
Abstract:
Modern complex circuits are described in very high speed integrated circuit hardware description language (VHDL) and difficult to verify. This paper proposes a systematic and visual dependency analysis method based on VHDL. The dependency relationships including control dependency, data dependency, signal control dependency and signal data dependency are defined. The entity dependency graph is presented and its generation algorithm, which searches the dependency relationships in hardware processes and between hardware processes, are developed. The experiment of a typical keyboard demonstrates
APA, Harvard, Vancouver, ISO, and other styles
2

Shiva, Sajjan G., and Judit U. Jones. "A VHDL Based Expert System for Hardware Synthesis." VLSI Design 1, no. 2 (1994): 113–26. http://dx.doi.org/10.1155/1994/93168.

Full text
Abstract:
This paper describes an expert system for Hardware Synthesis. Details of the target digital system are input to the expert system using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The VHDL representation is first translated to a knowledge representation scheme known as a ‘hologram’ which is a combination of rule, frame and semantic network representation schemes. The hologram representation of the target system is then input to the inference engine, which matches the target system to the Knowledge Base components and selects an appropriate set for implementation, a
APA, Harvard, Vancouver, ISO, and other styles
3

Shetty, Mamtha. "Design of BPSK Modulator Using VHDL." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, no. 12 (2014): 5247–52. http://dx.doi.org/10.24297/ijct.v13i12.5276.

Full text
Abstract:
Binary Phase Shift Keying represents the simulation results of binary digital modulation schemes. Here for BASK and BPSK modulation techniques use FPGA algorithm. If multiplier block is used for multiplication bit stream with carrier signal, used time will rises. In addition using multiplier block obtained simulation results were analyzed and compared to other simulation results. Source consumptions of FPGA-based BASK modulation technique and BPSK modulation technique were compared. Also, for different modulation algorithm, source consumptions of BASK and BPSK modulation technique were analyze
APA, Harvard, Vancouver, ISO, and other styles
4

Zhu, Juan, and Yue Chen. "Step Motor Control Based on FPGA." Applied Mechanics and Materials 397-400 (September 2013): 1226–29. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.1226.

Full text
Abstract:
Design a step motor control system based on Field Programmable Gate Array (FPGA). Give the hardware circuit of this system and the program based on very high speed integrated circuit hardware description language (VHDL). Compared to step motor control system based on single chip microcomputer, the processing speed of this system is faster.
APA, Harvard, Vancouver, ISO, and other styles
5

Palanisamy, R., C. S. Boopathi, K. Selvakumar, and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1722. http://dx.doi.org/10.11591/ijece.v10i2.pp1722-1727.

Full text
Abstract:
This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse
APA, Harvard, Vancouver, ISO, and other styles
6

Palanisamy, R., and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (2019): 81. http://dx.doi.org/10.11591/ijres.v8.i2.pp81-85.

Full text
Abstract:
<p>This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switchi
APA, Harvard, Vancouver, ISO, and other styles
7

Miriampally, Venkata Raghavendra. "Simulation of PCI Express™ Transaction Layer Using Hardware Description Language." International Journal of Informatics and Communication Technology (IJ-ICT) 4, no. 1 (2015): 7. http://dx.doi.org/10.11591/ijict.v4i1.pp7-12.

Full text
Abstract:
<p>PCI Express is a high-speed serial connection that operates more like a network than a bus.<strong> </strong>PCI Express will serve as a general purpose I/O interconnects for a wide variety of future computing and communications platforms.<strong> </strong>PCI Express (PCIe) is implemented with a split-transaction protocol that provides more bandwidth and is compatible with existing operating systems. PCI Express has three discrete logical layers: the Transaction Layer, the Data Link Layer, and the Physical Layer. This paper analyze and simulates the function o
APA, Harvard, Vancouver, ISO, and other styles
8

Zhang, Zi Sheng, Chun Sheng Wang, Yi Wang, Zhan You Wang, and Deng Yuan Song. "Power and Vibration of Electrostatic Precipitator Control Based on FPGA." Advanced Materials Research 1037 (October 2014): 244–47. http://dx.doi.org/10.4028/www.scientific.net/amr.1037.244.

Full text
Abstract:
In order to improve the automation level of the electrostatic precipitator, we used Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) language to compile, emulate and optimize the control system of power source and vibration. In the design of Quartus platform, we used EP1C3T144C8 Field Programmable Gate Array (FPGA) chip to realize high voltage power supply, alarm and protection system. We also realized the compilation and simulation test of each part’s function of 20 s rapping and 40 min rapping cycle. At the same time, we recorded the waveform of simulation. It demonstr
APA, Harvard, Vancouver, ISO, and other styles
9

Zhang, Zi Sheng, Yi Wang, Chun Sheng Wang, Jin Cui, and Zhi Qiang Liu. "The Control of High Voltage Electrostatic Precipitator Based on EDA." Advanced Materials Research 910 (March 2014): 336–39. http://dx.doi.org/10.4028/www.scientific.net/amr.910.336.

Full text
Abstract:
In order to achieve the automatic control of electrostatic precipitator (ESP) more efficiently and accurately, an ESP system combining hardware and software is designed. According to the requirement of the ESP system,the Electronic Design Automation (EDA) is introduced to the ESP control system and the system is divided into four modules.These sub-modules are designed and the simulation waveform of the system is ananalyzed,based on the Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) programming language and Quartus software.The results show that the security, flexibilit
APA, Harvard, Vancouver, ISO, and other styles
10

Shieh, Cheng Shion. "From Simulation to FPGA Control Circuit Implementation for Wind Power with Battery Charging." Advanced Materials Research 588-589 (November 2012): 777–80. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.777.

Full text
Abstract:
While application of field-programmable gate array (FPGA) chip has been extensively investigated, the charging control is relatively unexplored. This paper proposes a flow chart of energy storage for wind power system with Lead-Acid battery whose charging control is constructed by Very High Speed Integrated Circuit Hardware Description Language (VHDL) code. This research focuses on the proposed digital control algorithm can be directly downloaded into field-programmable gate array (FPGA) chip after simulation finishing. This saves greatly time on hardware circuit design. A simulation is presen
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "VHDL (Very hardware description language)"

1

Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Van, Tassel John Peter. "Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistant." Thesis, University of Cambridge, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.308190.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Pan, Bi-Yu. "Hierarchical test generation for VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-09052009-040449/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Kapoor, Shekhar. "Process level test generation for VHDL behavioral models." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-05022009-040753/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Narayanaswamy, Sathyanarayanan. "Development of VHDL behavioral models with back annotated timing." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06112009-063442/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Joshi, Anand Mukund. "Behavioral delay fault modeling and test generation." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-07292009-090436/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Guardia, Filho Luiz Eduardo. "Sistema para controle de maquinas robotizadas utilizando dispositivos logicos programaveis." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259017.

Full text
Abstract:
Orientador: Marconi Kolm Madrid<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação<br>Made available in DSpace on 2018-08-04T17:12:57Z (GMT). No. of bitstreams: 1 GuardiaFilho_LuizEduardo_M.pdf: 2405031 bytes, checksum: b724836217b8586950a9ffabcd235f35 (MD5) Previous issue date: 2005<br>Resumo: Este trabalho de mestrado teve o propósito de projetar e construir um sistema de hard-ware capaz de realizar o controle de máquinas robotizadas em tempo real. Foi dada uma abordagem usando técnicas de processamento paralelo e eletrônica reco
APA, Harvard, Vancouver, ISO, and other styles
8

Beydoun, Ali. "Système de numérisation hautes performances à base de bancs de convertisseurs sigma-delta passe-bande." Paris 11, 2008. http://www.theses.fr/2008PA112066.

Full text
Abstract:
Les systèmes de communications numériques mobiles tendent à intégrer de plus en plus d’applications (GSM, radio, TV, GPS, etc. ) tout en fonctionnant sur plusieurs normes. Cette évolution implique une reconfigurabilité en ligne des récepteurs à l’aide d’une programmation logicielle justifiant le terme de radio-logicielle. Par ailleurs, les normes de communication actuelles exigent des débits élevés. Les bandes de fréquence nécessaires sont donc étendues (jusqu’à plusieurs centaines de mégahertz). Ainsi, les systèmes de réception doivent être à très large bande. La reconfigurabilité logicielle
APA, Harvard, Vancouver, ISO, and other styles
9

Shah, Sandeep R. "A framework for synthesis from VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-03022010-020143/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Wright, Philip A. "Rapid development of VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-11102009-020056/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "VHDL (Very hardware description language)"

1

VHDL starter's guide. Prentice Hall, 1998.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

VHDL: A starter's guide. 2nd ed. Pearson/Prentice Hall, 2005.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Reichardt, Jürgen. VHDL-synthese: Entwurf Digitaler Schaltungen und Systeme. De Gruyter, 2015.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Chang, K. C. Digital design and modeling with VHDL and synthesis. IEEE Computer Society Press, 1997.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Barski, Mariusz. Układy cyfrowe: Podstawy projektowania i opis w języku VHDL. Wydawn. Politechniki Gdańskiej, 2007.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Kamat, Rajanish K. Harnessing VLSI System Design with EDA Tools. Springer Science+Business Media B.V., 2012.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Computer Systems Laboratory (U.S.), ed. VHSIC hardware description language (VHDL). U.S. Dept. of Commerce, Technology Administration, National Institute of Standards and Technology, Computer Systems Laboratory, 1995.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

A VHDL primer. Prentice Hall, 1992.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

A VHDL primer. 3rd ed. Prentice Hall PTR, 1999.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

A VHDL primer. Prentice Hall PTR, 1995.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "VHDL (Very hardware description language)"

1

Pierre, Laurence. "VHDL: A Hardware Description Language and its Simulation Semantics." In Software Specification Methods. Springer London, 2001. http://dx.doi.org/10.1007/978-1-4471-0701-9_7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Bazil Raj, A. Arockia. "Digital Circuit Design with Very-High-Speed Integrated Circuit Hardware Description Language." In FPGA-Based Embedded System Developer's Guide. CRC Press, 2018. http://dx.doi.org/10.1201/9781315156200-2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Bazil Raj, A. Arockia. "Floating-Point Computations with Very-High-Speed Integrated Circuit Hardware Description Language and Xilinx System Generator (SysGen) Tools." In FPGA-Based Embedded System Developer's Guide. CRC Press, 2018. http://dx.doi.org/10.1201/9781315156200-10.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Navabi, Zainalabedin, and Naghmeh Karimi. "VHDL-AMS Hardware Description Language." In The VLSI Handbook, Second Edition. CRC Press, 2006. http://dx.doi.org/10.1201/9781420005967.ch91.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Oczko, Andreas, and Christel Oczko. "Putting Different Simulation Models Together – The Simulation Configuration Language VHDL/S." In Computer Hardware Description Languages and their Applications. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-444-89208-9.50011-9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

El Oualkadi, Ahmed. "S-? Fractional-N Phase-Locked Loop Design Using HDL and Transistor-Level Models for Wireless Communications." In Advances in Wireless Technologies and Telecommunication. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-4666-0083-6.ch005.

Full text
Abstract:
This chapter presents a systematic design of a S-? fractional-N Phase-Locked Loop based on hardware description language behavioral modeling. The proposed design consists of describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The description language models of critical PLL blocks have been described in VHDL-AMS, which is an IEEE standard, to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the overall system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models in the frequency range around 2.45 GHz for wireless applications.
APA, Harvard, Vancouver, ISO, and other styles
7

Yahya, Abid, Farid Ghani, R. Badlishah Ahmad, et al. "Development of an Efficient and Secure Mobile Communication System with New Future Directions." In Handbook of Research on Computational Science and Engineering. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-61350-116-0.ch010.

Full text
Abstract:
This chapter presents performance of a new technique for constructing Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) encrypted codes based on a row division method. The new QC-LDPC encrypted codes are flexible in terms of large girth, multiple code rates, and large block lengths. In the proposed algorithm, the restructuring of the interconnections is developed by splitting the rows into subrows. This row division reduces the load on the processing node and ultimately reduces the hardware complexity. In this method of encrypted code construction, rows are used to form a distance graph. They are then transformed to a parity-check matrix in order to acquire the desired girth. In this work, matrices are divided into small sub-matrices, which result in improved decoding performance and reduce waiting time of the messages to be updated. Matrix sub-division increases the number of sub-matrices to be managed and memory requirement. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip.
APA, Harvard, Vancouver, ISO, and other styles
8

Liu, Jun, YaDong Zhu, XiaoPing Yang, JinLi Liu, and Zhen Wei. "Practical teaching reform in the VHDL (Very High Speed Integrated Circuit Description Language) course based on the idea of CDIO (Concept, Design, Implementation, and Operation)." In Frontiers in Computer Education. CRC Press, 2015. http://dx.doi.org/10.1201/b18444-31.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "VHDL (Very hardware description language)"

1

Wenzl, Matthias, Peter Roessler, and Andreas Puhm. "Checking Application Level Properties Using Assertion Synthesis." In ASME 2019 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/detc2019-97950.

Full text
Abstract:
Abstract This work presents a proof-of-concept of a new approach on automatic generation of digital hardware that is able to check application-level properties of an embedded system such as a faulty system behavior at runtime. The approach makes use of assertion-based verification setups that today are very common in the area of digital hardware design with, however, the sole focus on logic simulation. Thus, a PSL-to-VHDL compiler is introduced that generates VHDL (Very High Speed Integrated Circuit Description Language) code out of PSL (Property Specification Language) assertions which can be
APA, Harvard, Vancouver, ISO, and other styles
2

Gray, F., and James Armstrong. "Reutilization of VHDL testbench and library components (VHSIC Hardware Description Language)." In 10th Computing in Aerospace Conference. American Institute of Aeronautics and Astronautics, 1995. http://dx.doi.org/10.2514/6.1995-1035.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Binns, R. J. "High-level design of analogue circuitry using an analogue hardware description language." In IEE Colloquium on Mixed-Signal AHDL/VHDL Modelling and Synthesis. IEE, 1997. http://dx.doi.org/10.1049/ic:19971118.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Yuguo, Sun, and Chen Jin. "Embedded Fault Tree Logic Implementation Based on Complex Programmable Logic Device." In ASME 2005 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/detc2005-84886.

Full text
Abstract:
To meet the requirements of an embedded mechanical fault diagnosis system development, a fault tree implementation and dynamic modification method based on CPLD (Complex Programmable Logic Device) is investigated experimentally. The mechanism of fault tree logic calculation in the CPLD chip is presented. The fault logic tree is modeled by VHDL (VHSIC Hardware Description Language) and logic graphic, respectively. The effects of the bottom events on the logic result are simulated in Max + plus II platform. The fault tree logic is downloaded into the EPM7064SLC44-10 chip by ISP (In System Progra
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "VHDL (Very hardware description language)"

1

Chung, Moon Jung. Parallel Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) Simulation for Performance Modeling. Defense Technical Information Center, 1999. http://dx.doi.org/10.21236/ada372678.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Mills, Michael T. Proposed Object Oriented Programming (OOP) Enhancements to the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada274004.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Mills, Michael T. A Key Element Toward Concurrent Engineering of Hardware and Software: Binding Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) with Ada 95. Defense Technical Information Center, 1994. http://dx.doi.org/10.21236/ada294469.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Aylor, James, Robert Klenke, Ron Waxman, Paul Menchini, Jack Stinson, and Bill Anderson. VHSIC Hardware Description Language (VHDL) 200X Requirements Report/Survey. Defense Technical Information Center, 1999. http://dx.doi.org/10.21236/ada406178.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Federal Information Processing Standards Publication: VHSIC hardware description language (VHDL). National Institute of Standards and Technology, 1995. http://dx.doi.org/10.6028/nist.fips.172-1-1995.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'VHDL (Very hardware description language)' for particular source types:
Journal articles Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography