Log in

Relevant bibliographies by topics / VHDL (Very hardware description language) / Dissertations / Theses

To see the other types of publications on this topic, follow the link: VHDL (Very hardware description language).

Dissertations / Theses on the topic 'VHDL (Very hardware description language)'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 dissertations / theses for your research on the topic 'VHDL (Very hardware description language).'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.

1

Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Van, Tassel John Peter. "Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistant." Thesis, University of Cambridge, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.308190.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Pan, Bi-Yu. "Hierarchical test generation for VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-09052009-040449/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Kapoor, Shekhar. "Process level test generation for VHDL behavioral models." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-05022009-040753/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Narayanaswamy, Sathyanarayanan. "Development of VHDL behavioral models with back annotated timing." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06112009-063442/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Joshi, Anand Mukund. "Behavioral delay fault modeling and test generation." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-07292009-090436/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Guardia, Filho Luiz Eduardo. "Sistema para controle de maquinas robotizadas utilizando dispositivos logicos programaveis." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259017.

Full text

Abstract:

Orientador: Marconi Kolm Madrid<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação<br>Made available in DSpace on 2018-08-04T17:12:57Z (GMT). No. of bitstreams: 1 GuardiaFilho_LuizEduardo_M.pdf: 2405031 bytes, checksum: b724836217b8586950a9ffabcd235f35 (MD5) Previous issue date: 2005<br>Resumo: Este trabalho de mestrado teve o propósito de projetar e construir um sistema de hard-ware capaz de realizar o controle de máquinas robotizadas em tempo real. Foi dada uma abordagem usando técnicas de processamento paralelo e eletrônica reco

APA, Harvard, Vancouver, ISO, and other styles

8

Beydoun, Ali. "Système de numérisation hautes performances à base de bancs de convertisseurs sigma-delta passe-bande." Paris 11, 2008. http://www.theses.fr/2008PA112066.

Full text

Abstract:

Les systèmes de communications numériques mobiles tendent à intégrer de plus en plus d’applications (GSM, radio, TV, GPS, etc. ) tout en fonctionnant sur plusieurs normes. Cette évolution implique une reconfigurabilité en ligne des récepteurs à l’aide d’une programmation logicielle justifiant le terme de radio-logicielle. Par ailleurs, les normes de communication actuelles exigent des débits élevés. Les bandes de fréquence nécessaires sont donc étendues (jusqu’à plusieurs centaines de mégahertz). Ainsi, les systèmes de réception doivent être à très large bande. La reconfigurabilité logicielle

APA, Harvard, Vancouver, ISO, and other styles

9

Shah, Sandeep R. "A framework for synthesis from VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-03022010-020143/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Wright, Philip A. "Rapid development of VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-11102009-020056/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Dailey, David M. "Integration of VHDL simulation and test verification into a Process Model Graph design environment." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-11242009-020247/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Sama, Anil. "Behavior modeling of RF systems with VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-10102009-020211/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Ardeishar, Raghu. "Automatic verification of VHDL models." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Rao, Sanat R. "A hierarchical approach to effective test generation for VHDL behavioral models." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-08042009-040513/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Manek, Meenakshi. "Natural language interface to a VHDL modeling tool." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-06232009-063212/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Honcharik, Alexander J. "Generation of VHDL from conceptual graphs of informal specifications." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-06162009-063028/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Sprunger, Steven J. "UML modeling for VHDL designs." Virtual Press, 2008. http://liblink.bsu.edu/uhtbin/catkey/1399192.

Full text

Abstract:

Unified Modeling Language (UML) allows software engineers to use a standard way of expressing a design approach at a high level. The benefits of system modeling are well accepted in the software development community. Modeling of Very High Speed Integrated Circuit Hardware Description Language (VHDL) designs, for synthesizing into hardware, is a common practice also. The research herein looks at system modeling of a design using UML, in which there are both software and hardware components. The idea is to explore modeling of the system with the ability to abstract whether the implementation of

APA, Harvard, Vancouver, ISO, and other styles

18

Edwards, Carleen Marie. "Representation and simulation of a high level language using VHDL." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-11242009-020306/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Shrivastava, Vikram M. "Mapping conceptual graphs to primitive VHDL processes." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-05022009-040536/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Barton, Jonathan L. "Hardware implementation of a synchronization state buffer in VHDL." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 67 p, 2008. http://proquest.umi.com/pqdweb?did=1459924801&sid=13&Fmt=2&clientId=8331&RQT=309&VName=PQD.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Macklin, Kendrick R. "Suitability of the SRC-6E reconfigurable computing system for generating false radar image." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2004. http://library.nps.navy.mil/uhtbin/hyperion/04Jun%5FMacklin.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Giannopoulos, Vassilis. "Efficient VHDL models for various PLD architectures /." Online version of thesis, 1995. http://hdl.handle.net/1850/12238.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Gadagkar, Ashish. "Timing distribution in VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10102009-020318/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Goeke, James A. "Design of a hardware efficient key generation algorithm with a VHDL implementation /." Online version of thesis, 1993. http://hdl.handle.net/1850/11664.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Costa, Richard Maciel. "Metodologia e projeto de ferramenta para co-simulação entre VHDL e SystemC." [s.n.], 2008. http://repositorio.unicamp.br/jspui/handle/REPOSIP/276135.

Full text

Abstract:

Orientadores: Sandro Rigo, Guido Costa Souza de Araujo<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação<br>Made available in DSpace on 2018-08-13T11:44:55Z (GMT). No. of bitstreams: 1 Costa_RichardMaciel_M.pdf: 4274440 bytes, checksum: 4094fea059358a9a5eb39c56aa5f1f3c (MD5) Previous issue date: 2008<br>Resumo: Em um passado recente os sistemas eram constituídos de partes discretas tais como microprocessadores, memórias e Application Specific Integrated Circuits (ASICs). Essa separação clara e simples tornava possível a especificação ser feita por uns pou

APA, Harvard, Vancouver, ISO, and other styles

26

Palanisamy, Karthikeyan. "High Level Preprocessor of a VHDL-based Design System." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4776.

Full text

Abstract:

This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADESfa design automation system developed at PSU, starts the synthesis process from a language called ADL. The major part of this thesis deals with transforming the ADL -based DIADES system into a VHDL -based DIADES system. In this thesis I have upgraded and modified the existing DIADES system so that it becomes a preprocessor to a comprehensive VHDL -based design system from Mentor Graphics. The high-level synthesis in the DIADES system includes two stages: data

APA, Harvard, Vancouver, ISO, and other styles

27

Chadha, Vikrampal. "Simulation of large-scale system-level models." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12162009-020334/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Chu, Ming-Cheung. "Hazard detection with VHDL in combinational logic circuits with fixed delays." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10062009-020040/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Koelmans, Albertus Maria. "STRICT : a language and tool set for the design of very large scale integrated circuits." Thesis, University of Newcastle Upon Tyne, 1996. http://hdl.handle.net/10443/2076.

Full text

Abstract:

An essential requirement for the design of large VLSI circuits is a design methodology which would allow the designer to overcome the complexity and correctness issues associated with the building of such circuits. We propose that many of the problems of the design of large circuits can be solved by using a formal design notation based upon the functional programming paradigm, that embodies design concepts that have been used extensively as the framework for software construction. The design notation should permit parallel, sequential, and recursive decompositions of a design into smaller comp

APA, Harvard, Vancouver, ISO, and other styles

30

Wilhelm, Kyle. "Aspects of hardware methodologies for the NTRU public-key cryptosystem /." Online version of thesis, 2008. http://hdl.handle.net/1850/7774.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Moustakas, Evangelos. "Design and simulation of a primitive RISC architecture using VHDL /." Online version of thesis, 1991. http://hdl.handle.net/1850/11229.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Frandina, Peter. "VHDL modeling and synthesis of the JPEG-XR inverse transform /." Online version of thesis, 2009. http://hdl.handle.net/1850/10755.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Singh, Balraj. "A parametrized CAD tool for VHDL model development with X Windows." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03242009-040819/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Imvidhaya, Ming. "VHDL simulation of the implementation of a costfunction circuit." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA240430.

Full text

Abstract:

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 1990.<br>Thesis Advisor(s): Lee, Chin-Hwa. Second Reader: Butler, Jon T. "September 1990." Description based on title screen as viewed on December 29, 2009. DTIC Identifier(s): Computerized simulation, computer aided design, logic circuits, subroutines, theses, integrated circuits. Author(s) subject terms: VHDL, costfunction, hardware description language. Includes bibliographical references (p. 77). Also available in print.

APA, Harvard, Vancouver, ISO, and other styles

35

Macklin, Kendrick R. "Benchmarking and analysis of the SRC-6E reconfigurable computing system." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Dec%5FMacklin.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Fanelli, Paul. "VHDL modeling and design of an asynchronous version of the MIPS R3000 microprocessor /." Online version of thesis, 1994. http://hdl.handle.net/1850/11157.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Chen, Wei-chun. "Simulation of a morphological image processor using VHDL. mathematical components /." Online version of thesis, 1993. http://hdl.handle.net/1850/11872.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Chen, Hao. "Simulation of a morphological image processor using VHDL. control mechanism /." Online version of thesis, 1993. http://hdl.handle.net/1850/11744.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Guthrie, Thomas G. "Design, implementation, and testing of a software interface between the AN/SPS-65(V)1 radar and the SRC-6E reconfigurable computer." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2005. http://library.nps.navy.mil/uhtbin/hyperion/05Mar%5FGuthrie.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Phillips, Walter. "VHDL design of computer vision tasks." Honors in the Major Thesis, University of Central Florida, 2001. http://digital.library.ucf.edu/cdm/ref/collection/ETH/id/240.

Full text

Abstract:

This item is only available in print in the UCF Libraries. If this is your Honors Thesis, you can help us make it available online for use by researchers around the world by following the instructions on the distribution consent form at http://library.ucf.edu/Systems/DigitalInitiatives/DigitalCollections/InternetDistributionConsentAgreementForm.pdf You may also contact the project coordinator, Kerri Bottorff, at kerri.bottorff@ucf.edu for more information.<br>Bachelors<br>Engineering<br>Computer Science

APA, Harvard, Vancouver, ISO, and other styles

41

Hoffman, Joseph A. "VHDL modeling of ASIC power dissipation." Master's thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10222009-124831/.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Oliveira, Alexandre Tomazati. "Detecção do complexo QRS em sinais cardiacos utilizando FPGA." [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/264060.

Full text

Abstract:

Orientador: Euripedes Guilherme de Oliveira Nobrega<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecanica<br>Made available in DSpace on 2018-08-15T01:47:19Z (GMT). No. of bitstreams: 1 Oliveira_AlexandreTomazati_M.pdf: 3226409 bytes, checksum: 06c44b66428a69ae6b8214fd07432ae6 (MD5) Previous issue date: 2009<br>Resumo: O eletrocardiograma (ECG) é uma ferramenta utilizada para o diagnóstico de cardiopatias e outras doenças. Este trabalho tem como objetivo a detecção do complexo QRS, com foco na onda R, que representa a contração dos ventrículos. Para

APA, Harvard, Vancouver, ISO, and other styles

43

Kantemir, Ozkan. "VHDL modeling and simulation of a digital image synthesizer for countering ISAR." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Jun%5FKantemir.pdf.

Full text

Abstract:

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003.<br>Thesis advisor(s): Douglas J. Fouts, Phillip E. Pace. Includes bibliographical references (p. 143-144). Also available online.

APA, Harvard, Vancouver, ISO, and other styles

44

Nouman, Ziad. "Užití programovatelných hradlových polí v systémech průmyslové automatizace." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-234615.

Full text

Abstract:

Tato disertační práce se zabývá využitím programovatelných hradlových polí (FPGA) v diagnostice měničů, využívajících spínaných IGBT tranzistorů. Je zaměřena na budiče těchto výkonových tranzistorů a jejich struktury. Přechodné jevy veličin, jako jsou IG, VGE, VCE během procesu přepínání (zapnutí, vypnutí), mohou poukazovat na degradaci IGBT. Pro měření a monitorování těchto veličin byla navržena nová architektura budiče IGBT. Rychlé měření a monitorování během přepínacího děje vyžaduje vysokou vzorkovací frekvenci. Proto jsou navrhovány paralelní vysokorychlostní AD převodníky (> 50 MSPS). Pr

APA, Harvard, Vancouver, ISO, and other styles

45

Raizer, Klaus 1982. "Análise de sinais de ECG com o uso de wavelets e redes neurais em FPGA." [s.n.], 2010. http://repositorio.unicamp.br/jspui/handle/REPOSIP/264098.

Full text

Abstract:

Orientador: Eurípedes Guilherme de Oliveira Nóbrega<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecânica<br>Made available in DSpace on 2018-08-16T07:47:06Z (GMT). No. of bitstreams: 1 Raizer_Klaus_M.pdf: 2682241 bytes, checksum: 765c3dc138a1e4c9258fd0201cd56a8f (MD5) Previous issue date: 2010<br>Resumo: Este trabalho apresenta a implementação de um sistema de análise de sinais de ECGs (eletrocardiogramas) embarcado em FPGA (field programmable gate array), capaz de classificar cardiopatias. A análise de ECGs é de grande importância devido a sua natu

APA, Harvard, Vancouver, ISO, and other styles

46

Hudson, Rhett Daniel. "The use of VHDL in computer-aided support of life-cycle complete product design." Thesis, Virginia Tech, 1994. http://hdl.handle.net/10919/42143.

Full text

Abstract:

Successful competition in the computer systems industry depends on a firm's ability to bring profitable products to market. The success of a product is measured by its future worth to the company. Life-cycle complete design attempts to engineer products that provide maximum future worth. Many components contribute to the overall cost of developing a product. Designing merely to reduce the cost of the components that make up the system is insufficient. <p>A product must be engineered in a manner that addresses all pertinent issues over its complete life cycle. This research examines the use of

APA, Harvard, Vancouver, ISO, and other styles

47

Antiqueira, Perci Ayres. "Implementação de modelos de redes de Petri em hardware de lógica reconfigurável." Universidade Tecnológica Federal do Paraná, 2011. http://repositorio.utfpr.edu.br/jspui/handle/1/204.

Full text

Abstract:

Neste trabalho de pesquisa, foi realizado um estudo dos principais tipos de ferramentas para modelagem de hardware buscando-se verificar as vantagens da utilização de Redes de Petri para a modelagem de sistemas dinâmicos e concorrentes e de sua implementação em hardware. Observou-se que apesar de existirem ferramentas para esta finalidade, existem pontos que podem ser trabalhados para facilitar o acesso a esta tecnologia. Assim, foi desenvolvido um método para facilitar a implementação de sistemas modelados em Redes de Petri, em hardware de lógica reconfigurável. Para isto, utilizou-se um soft

APA, Harvard, Vancouver, ISO, and other styles

48

Horsburgh, Ian J. "The development of a mass memory unit for a micro-satellite using NAND flash memory." Thesis, Stellenbosch : Stellenbosch University, 2005. http://hdl.handle.net/10019.1/50474.

Full text

Abstract:

Thesis (MScEng)--Stellenbosch University, 2005.<br>ENGLISH ABSTRACT: This thesis investigates the possible use of NAND flash memory for a mass memory unit on a micro-satellite. The investigation begins with an analysis of NAND flash memory devices including the complexity of the internal circuitry and the occurrence of bad memory sections (bad blocks). Design specifications are produced and various design architectures are discussed and evaluated. Subsequently, a four bus serial access architecture using 16- bit NAND flash devices was chosen to be developed further. A VHDL design was cr

APA, Harvard, Vancouver, ISO, and other styles

49

Souza, Fabiano Alves de [UNESP]. "Detecção de faltas em sistemas de distribuição de energia elétrica usando dispositivos programáveis." Universidade Estadual Paulista (UNESP), 2008. http://hdl.handle.net/11449/87044.

Full text

Abstract:

Made available in DSpace on 2014-06-11T19:22:31Z (GMT). No. of bitstreams: 0 Previous issue date: 2008-09-08Bitstream added on 2014-06-13T18:08:25Z : No. of bitstreams: 1 souza_fa_me_ilha.pdf: 1540078 bytes, checksum: dcdf1d9d8a1a4c7ac5611476ba3ddbee (MD5)<br>Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)<br>Atualmente as empresas do setor elétrico deparam–se cada vez mais com as exigências do mercado energético sendo obrigadas a assegurarem aos seus clientes bons níveis de continuidade e confiabilidade no serviço de fornecimento da energia elétrica e também atender os í

APA, Harvard, Vancouver, ISO, and other styles

50

Souza, Fabiano Alves de. "Detecção de faltas em sistemas de distribuição de energia elétrica usando dispositivos programáveis /." Ilha Solteira : [s.n.], 2008. http://hdl.handle.net/11449/87044.

Full text

Abstract:

Orientador: Suely Cunha Amaro Mantovani<br>Banca: Nobuo Oki<br>Banca: Luis Gustavo Wesz da Silva<br>Resumo: Atualmente as empresas do setor elétrico deparam-se cada vez mais com as exigências do mercado energético sendo obrigadas a assegurarem aos seus clientes bons níveis de continuidade e confiabilidade no serviço de fornecimento da energia elétrica e também atender os índices de continuidade do serviço estabelecidos pela agência reguladora do setor elétrico (ANEEL - Agência Nacional de Energia Elétrica). Para alcançar estes objetivos além de investir na otimização dos seus sistemas de trans

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!