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1
Yi, Zhao Xiang, Xiong Mei Zhang, Ning Li, and Xiao Dong Mu. "A Visual Dependency Analysis Method Based on VHDL." Applied Mechanics and Materials 738-739 (March 2015): 582–85. http://dx.doi.org/10.4028/www.scientific.net/amm.738-739.582.
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Modern complex circuits are described in very high speed integrated circuit hardware description language (VHDL) and difficult to verify. This paper proposes a systematic and visual dependency analysis method based on VHDL. The dependency relationships including control dependency, data dependency, signal control dependency and signal data dependency are defined. The entity dependency graph is presented and its generation algorithm, which searches the dependency relationships in hardware processes and between hardware processes, are developed. The experiment of a typical keyboard demonstrates that it is a visual and efficient method to analyze dependency relationships of VHDL for formal verification.
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Shiva, Sajjan G., and Judit U. Jones. "A VHDL Based Expert System for Hardware Synthesis." VLSI Design 1, no. 2 (January 1, 1994): 113–26. http://dx.doi.org/10.1155/1994/93168.
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This paper describes an expert system for Hardware Synthesis. Details of the target digital system are input to the expert system using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The VHDL representation is first translated to a knowledge representation scheme known as a ‘hologram’ which is a combination of rule, frame and semantic network representation schemes. The hologram representation of the target system is then input to the inference engine, which matches the target system to the Knowledge Base components and selects an appropriate set for implementation, and connects them creating a digital circuit. Some design examples are described. The expert system approach results in designs very close to designs from a human designer. In its present form, the system does not perform a design space exploration for alternate designs, but expects the designer to alter the VHDL representation, after observing the results from previous design cycles.
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Shetty, Mamtha. "Design of BPSK Modulator Using VHDL." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, no. 12 (October 23, 2014): 5247–52. http://dx.doi.org/10.24297/ijct.v13i12.5276.
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Binary Phase Shift Keying represents the simulation results of binary digital modulation schemes. Here for BASK and BPSK modulation techniques use FPGA algorithm. If multiplier block is used for multiplication bit stream with carrier signal, used time will rises. In addition using multiplier block obtained simulation results were analyzed and compared to other simulation results. Source consumptions of FPGA-based BASK modulation technique and BPSK modulation technique were compared. Also, for different modulation algorithm, source consumptions of BASK and BPSK modulation technique were analyzed using VHDL. Designed modulators using VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL) was realized on high speed FPGA (Field Program Programmable Gate Array). Because for used modulation technique data rate transfer is fairly important in wireless communication systems. The highest speed data rate transfer can be realized using fiber optic cables. In addition, BER (Bit Error Rate) of BASK and BPSK modulator was compared using MATLAB simulation program. Binary data rate is same for BPSK and BASK. BPSK and BASK modulations were designed on FPGA using VHDL hardware description language.
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Zhu, Juan, and Yue Chen. "Step Motor Control Based on FPGA." Applied Mechanics and Materials 397-400 (September 2013): 1226–29. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.1226.
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Design a step motor control system based on Field Programmable Gate Array (FPGA). Give the hardware circuit of this system and the program based on very high speed integrated circuit hardware description language (VHDL). Compared to step motor control system based on single chip microcomputer, the processing speed of this system is faster.
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Palanisamy, R., C. S. Boopathi, K. Selvakumar, and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (April 1, 2020): 1722. http://dx.doi.org/10.11591/ijece.v10i2.pp1722-1727.
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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.
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Palanisamy, R., and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (July 1, 2019): 81. http://dx.doi.org/10.11591/ijres.v8.i2.pp81-85.
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<p>This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.</p>
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Miriampally, Venkata Raghavendra. "Simulation of PCI Express™ Transaction Layer Using Hardware Description Language." International Journal of Informatics and Communication Technology (IJ-ICT) 4, no. 1 (April 1, 2015): 7. http://dx.doi.org/10.11591/ijict.v4i1.pp7-12.
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<p>PCI Express is a high-speed serial connection that operates more like a network than a bus.<strong> </strong>PCI Express will serve as a general purpose I/O interconnects for a wide variety of future computing and communications platforms.<strong> </strong>PCI Express (PCIe) is implemented with a split-transaction protocol that provides more bandwidth and is compatible with existing operating systems. PCI Express has three discrete logical layers: the Transaction Layer, the Data Link Layer, and the Physical Layer. This paper analyze and simulates the function of Transaction layer <strong> </strong>IP core in the System Level with top-down design method, wrote the codes to implement Transaction Layer using Very high speed hardware description language (VHDL) and provided the simulation results using Active HDL Simulation tool. The simulation result shows that the designed IP core meets the required protocol specifications for the proper functioning of PCI Express Transaction layer.</p><p> </p>
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Zhang, Zi Sheng, Chun Sheng Wang, Yi Wang, Zhan You Wang, and Deng Yuan Song. "Power and Vibration of Electrostatic Precipitator Control Based on FPGA." Advanced Materials Research 1037 (October 2014): 244–47. http://dx.doi.org/10.4028/www.scientific.net/amr.1037.244.
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In order to improve the automation level of the electrostatic precipitator, we used Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) language to compile, emulate and optimize the control system of power source and vibration. In the design of Quartus platform, we used EP1C3T144C8 Field Programmable Gate Array (FPGA) chip to realize high voltage power supply, alarm and protection system. We also realized the compilation and simulation test of each part’s function of 20 s rapping and 40 min rapping cycle. At the same time, we recorded the waveform of simulation. It demonstrated that the validity of the relevant VHDL compilation. We used this method to achieve the optimization control of the electrostatic precipitator operating parameters. It has a strong practicability.
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Zhang, Zi Sheng, Yi Wang, Chun Sheng Wang, Jin Cui, and Zhi Qiang Liu. "The Control of High Voltage Electrostatic Precipitator Based on EDA." Advanced Materials Research 910 (March 2014): 336–39. http://dx.doi.org/10.4028/www.scientific.net/amr.910.336.
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In order to achieve the automatic control of electrostatic precipitator (ESP) more efficiently and accurately, an ESP system combining hardware and software is designed. According to the requirement of the ESP system,the Electronic Design Automation (EDA) is introduced to the ESP control system and the system is divided into four modules.These sub-modules are designed and the simulation waveform of the system is ananalyzed,based on the Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) programming language and Quartus software.The results show that the security, flexibility and reliabity of the system is improved by using EDA as the control ,which is a great value for generalization.
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Shieh, Cheng Shion. "From Simulation to FPGA Control Circuit Implementation for Wind Power with Battery Charging." Advanced Materials Research 588-589 (November 2012): 777–80. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.777.
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While application of field-programmable gate array (FPGA) chip has been extensively investigated, the charging control is relatively unexplored. This paper proposes a flow chart of energy storage for wind power system with Lead-Acid battery whose charging control is constructed by Very High Speed Integrated Circuit Hardware Description Language (VHDL) code. This research focuses on the proposed digital control algorithm can be directly downloaded into field-programmable gate array (FPGA) chip after simulation finishing. This saves greatly time on hardware circuit design. A simulation is presented to illustrate the effectiveness of the proposed charging flow chart.
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Sahu, Gokulananda, Rajesh Kumar Patjoshi, and Rakhee Panigrahi. "An FPGA Based Novel Digital Controller for DSTATCOM to Enhance Power Quality in Distribution System." ECTI Transactions on Electrical Engineering, Electronics, and Communications 18, no. 2 (August 31, 2020): 118–29. http://dx.doi.org/10.37936/ecti-eec.2020182.240340.
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This paper proposes an FPGA based all-on-chip novel digital controller for DSTATCOM to compensate harmonics and reactive power existing in power distribution system. The proposed technique extracts reference current by considering instantaneous symmetrical component active power (ISCAP) theory based phase delay compensation (PDC) control technique. The proposed controller comprises positive sequence detector, PI-controller, low-pass filters (LPF) and hysteresis current controller. All these segments are configured on high speed, low cost field programmable gate arrays (FPGA) hardware resources intended to mitigate harmonics and compensate reactive power in power distribution network. Very high speed hardware description language (VHDL) implementation for each module are produced through system generator and implemented on SPARTAN-3 XC3S5000 FPGA chip through RT-XSG toolbox in Opal-RT platform. The performance of proposed controller is demonstrated through VHDL test bench, simulation and real-time experimental results with consideration of total harmonic distortion (THD) and power factor correction in steady state condition.
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Quynh, Nguyen Vu, Ying Shieh Kung, Pham Van Dung, Kuan Yuen Liao, and Sheng Wei Chen. "FPGA-Realization of Vector Control for PMSM Drives." Applied Mechanics and Materials 311 (February 2013): 249–54. http://dx.doi.org/10.4028/www.scientific.net/amm.311.249.
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The design and implementation of a vector control for Permanent Magnetic Synchronous Motor (PMSM) based on Field Programmable Gate Array (FPGA) technology is presented in this paper. Firstly, a Space Vector Pulse Width Modulation (SVPWM) scheme, vector control method and PI controller are derived. Secondly, the Very-High-Speed IC Hardware Description Language (VHDL) is adopted to describe the behavior of the aforementioned control algorithms. Finally, an experimental system is setup to evaluate the effectiveness and correctness of the proposed vector controller for PMSM drives.
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Kung, Ying Shieh, Nguyen Phan Thanh, and Hsin Hung Chou. "Design and Implementation of a Microprocessor-Based PI Controller for PMSM Drives." Applied Mechanics and Materials 764-765 (May 2015): 496–500. http://dx.doi.org/10.4028/www.scientific.net/amm.764-765.496.
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This work presents a hardware implementation of a simple microprocessor; then uses this microprocessor to design a PI controller for PMSM (Permanent Magnet Synchronous Motor) drives. In this paper, firstly, the mathematical model of PMSM drives is illustrated. Secondly, the architecture of a simple microprocessor based on RTL (Register Transfer Level) method is proposed and the VHDL (Very high speed IC Hardware Description Language) is adopted to describe the behavior of the simple microprocessor. Thirdly, a machine code of PI controller based on the proposed simple microprocessor is designed. Finally, a co-simulation by Simulink/ModelSim is applied and verified the performance of the microprocessor-based PI controller.
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Kamar, Sara, Abdelmoniem Fouda, Abdelhalim Zekry, and Abdelmoniem Elmahdy. "FPGA implementation of RS codec with interleaver in DVB-T using VHDL." International Journal of Engineering & Technology 6, no. 4 (November 28, 2017): 171. http://dx.doi.org/10.14419/ijet.v6i4.8205.
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Digital television (DTV) provides a huge amount of information to many users at low cost. Recently, it can be packaged and fully integrated into completely digital transmission networks. Reed-Solomon code (RS) is one type of error correcting codes that can be used to enhance the performance of DTV. Interleaving/deinterleaving process enhances the performance of channel errors by spreading out random errors, very high-speed hardware description language (VHDL) is used in electronic design automation. It can be used as a general-purpose parallel programming language.This paper presents VHDL program for Reed-Solomoncodec (204, 188) and convolutional interleaver/deinterleaver, used in Digital Video Broadcasting-terrestrial system (DVB-T), according to ETSI EN 300 744 V1.5.1 standard. The VHDL programs are implemented on Xilinx 12.3 ISE and then simulated and tested via ISE simulator then the code is synthesized on FPGA device the results are compared with IP core for Xilinx 12.3 ISE, which gives the same results.
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Ali, Fakhrulddin, Mohammed Hussein, and Sinan Ismael. "LabVIEW FPGA Implementation Of a PID Controller For D.C. Motor Speed Control." Iraqi Journal for Electrical and Electronic Engineering 6, no. 2 (December 1, 2010): 139–44. http://dx.doi.org/10.37917/ijeee.6.2.9.
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This Paper presents a novel hardware design methodology of digital control systems. For this, instead of synthesizing the control system using Very high speed integration circuit Hardware Description Language (VHDL), LabVIEW FPGA module from National Instrument (NI) is used to design the whole system that include analog capture circuit to take out the analog signals (set point and process variable) from the real world, PID controller module, and PWM signal generator module to drive the motor. The physical implementation of the digital system is based on Spartan-3E FPGA from Xilinx. Simulation studies of speed control of a D.C. motor are conducted and the effect of a sudden change in reference speed and load are also included.
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Sideris, Argyrios, Theodora Sanida, and Minas Dasygenis. "High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor." Technologies 8, no. 1 (February 10, 2020): 15. http://dx.doi.org/10.3390/technologies8010015.
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Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming language for all output lengths in the Keccak hash function (224, 256, 384 and 512). Our experiments were performed with the Nios II processor on the FPGA Arria 10 GX (10AX115N2P45E1SG). We applied two architectures, one without custom instruction and one with floating point hardware 2. Finally, we compare the results with other existing similar designs and found that the proposed design with floating point 2 optimizes throughput (Gbps) compared to existing FPGA implementations.
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Sun, Hao, Xin Wen Duan, and Yuan Liu. "Design of Digital Cymometer Based on EDA Technology." Applied Mechanics and Materials 719-720 (January 2015): 517–21. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.517.
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To overcome the shortcoming that the traditional cymometer has a relatively large delay, small measuring range, low precision, poor reliability and complicated circuit; A design of digital cymometer based on EDA technology is proposed. The design is programmed with the hardware description language of VHDL. And it takes full advantages of Max+PlusII software to compile and simulate. All the functions are downloaded into and debugged on the chip of EP1K100QC in ACEX1K series from Altera Company. The experimental results show that this system has a very high reliability and small measuring error. The function of this system completely satisfies the demand of the design.
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Zhang, Zi Sheng, Peng Bo Ge, Xiao Dong Shi, Bo Feng Liu, and Zhi Qiang Liu. "The Control System of High Voltage Electrostatic Precipitator Based on FPGA." Advanced Materials Research 823 (October 2013): 528–31. http://dx.doi.org/10.4028/www.scientific.net/amr.823.528.
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It is urgent to study a new control system for improving the efficiency of electrostatic precipitator. The System-on-a-Programmable-Chip (SOPC) development board, which belongs to the series of Cyclone of Altera Company, is used as the development platform. Analog Digital (AD) conversion module, voltage control module and overall control module of the electrostatic precipitator are designed and the simulation waveform of the system is analyzed, based on the programmable logic device EP1C12Q240C6 and Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) programming language. The results show that: by using Field Programmable Gate Array (FPGA) as the control, transformation of AD is accurate and fast and high voltage power supply is stable, which leads to a certain value for generalization.
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Kung, Ying-Shieh, Ming-Kuang Wu, Hai Linh Bui Thi and, Tz-Han Jung, Feng-Chi Lee, and Wen-Chuan Chen. "FPGA-based hardware implementation of arctangent and arccosine functions for the inverse kinematics of robot manipulator." Engineering Computations 31, no. 8 (October 28, 2014): 1679–90. http://dx.doi.org/10.1108/ec-11-2012-0290.
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Purpose – The inverse kinematics in robot manipulator have to handle the arctangent and arccosine function. However, the two functions are complicated and need much computation time so that it is difficult to be realized in the typical processing system. The purpose of this paper is to solve this problem by using Field Programmable Gate Array (FPGA) to speed up the computation power. Design/methodology/approach – The Taylor series expansion method is firstly applied to transfer arctangent and arccosine function to a polynomial form. And Look-Up Table (LUT) is used to store the parameters of the polynomial form. Then the behavior of the computation algorithm is described by Very high-speed IC Hardware Description Language (VHDL) and a co-simulation using ModelSim and Simulink is applied to evaluate the correctness of the VHDL code. Findings – The computation time of arctangent and arccosine function using by FPGA need only 320 and 420 ns, respectively, and the accuracy is <0.01°. Practical implications – Fast computation in arctangent and arccosine function can speed up the motion response of the real robot system when it needs to perform the inverse kinematics function. Originality/value – This is the first time such to combine the Taylor series method and LUT method in the computation the arctangent and arccosine function as well as to implement it with FPGA.
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Kulakovskis, Darius, and Dalius Navakauskas. "Automated Metabolic P System Placement in FPGA." Electrical, Control and Communication Engineering 10, no. 1 (July 1, 2016): 5–12. http://dx.doi.org/10.1515/ecce-2016-0001.
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Abstract An original Very High Speed Integrated Circuit Hardware Description Language (VHDL) code generation tool that can be used to automate Metabolic P (MP) system implementation in hardware such as Field Programmable Gate Arrays (FPGA) is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT), and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP), slice, and 4-input LUT usage.
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Hai Linh, Bui Thi, and Ying-Shieh Kung. "Digital Hardware Realization of Forward and Inverse Kinematics for a Five-Axis Articulated Robot Arm." Mathematical Problems in Engineering 2015 (2015): 1–10. http://dx.doi.org/10.1155/2015/906505.
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When robot arm performs a motion control, it needs to calculate a complicated algorithm of forward and inverse kinematics which consumes much CPU time and certainty slows down the motion speed of robot arm. Therefore, to solve this issue, the development of a hardware realization of forward and inverse kinematics for an articulated robot arm is investigated. In this paper, the formulation of the forward and inverse kinematics for a five-axis articulated robot arm is derived firstly. Then, the computations algorithm and its hardware implementation are described. Further, very high speed integrated circuits hardware description language (VHDL) is applied to describe the overall hardware behavior of forward and inverse kinematics. Additionally, finite state machine (FSM) is applied for reducing the hardware resource usage. Finally, for verifying the correctness of forward and inverse kinematics for the five-axis articulated robot arm, a cosimulation work is constructed by ModelSim and Simulink. The hardware of the forward and inverse kinematics is run by ModelSim and a test bench which generates stimulus to ModelSim and displays the output response is taken in Simulink. Under this design, the forward and inverse kinematics algorithms can be completed within one microsecond.
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V. Kinge, Pravin, S. J. Honale, and C. M. Bobade. "Design of AES Algorithm for 128/192/256 Key Length in FPGA." International Journal of Reconfigurable and Embedded Systems (IJRES) 3, no. 2 (July 1, 2014): 49. http://dx.doi.org/10.11591/ijres.v3.i2.pp49-53.
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<p class="p0">The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. The available AES algorithm is used for data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to AES algorithm, to obtain the encrypted image. and the encrypted image is the input to AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit AES algorithm for data encryption and decryption, also to compare the speed of operation, efficiency, security and frequency . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language (VHDL).</p>
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Lv, Fu Xing, and Ying Gao. "Speed Control Scheme for BLDC Drive with Nonlinear Fuzzy PID Control Based on DSP and FPGA." Advanced Materials Research 466-467 (February 2012): 1275–78. http://dx.doi.org/10.4028/www.scientific.net/amr.466-467.1275.
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Because of its high performance, brushless DC motors are widely used in vehicles. But the brushless DC motor speed system itself is easily influenced by the parameter variation, the cogging torque and the load disturbance. And some complex algorithms to overcome the deficiency are difficult to implement on a single DSP chip. To solve the problem, the paper represents a nonlinear PID controller based on DSP and FPGA. A functional design of FPGA in a brushless DC motor system based on FPGA and DSP was completed by using modular design method. All the function modules are programmed by Very-High-Speed Integrated Circuit Hardware Description Language (VHDL). The simulation and experiment results indicate that nonlinear PID can improve the performances of the servo system in rapidity, control accuracy, adaptability and robustness.
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Wang, Mu Lan, Jian Min Zuo, Kun Liu, and Xing Hua Zhu. "FPGA-Based Intelligent Software Hardening Chip for Computer Numerical Control System." Applied Mechanics and Materials 105-107 (September 2011): 2217–20. http://dx.doi.org/10.4028/www.scientific.net/amm.105-107.2217.
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In order to meet the development demands for high-speed and high-precision of Computer Numerical Control (CNC) machine tools, the equipped CNC systems begin to employ the technical route of software hardening. Making full use of the advanced performance of Large Scale Integrated Circuits (LSIC), this paper puts forward using Field Programmable Gates Array (FPGA) for the functional modules of CNC system, which is called Intelligent Software Hardening Chip (ISHC). The CNC system architecture with high performance is constructed based on the open system thought and ISHCs. The corresponding programs can be designed with Very high speed integrate circuit Hardware Description Language (VHDL) and downloaded into the FPGA. These hardening modules, including the arithmetic module, contour interpolation module, position control module and so on, demonstrate that the proposed schemes are reasonable and feasibility.
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Anthony Prathap, Joseph, T. S.Anandhi, K. Ramash Kumar, and B. Srikanth. "Performance evaluation and analysis of 64-quadrature amplitude modulator using Xilinx Spartan FPGA." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 570. http://dx.doi.org/10.14419/ijet.v7i2.8.10523.
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This paper proposes the design of 64-Quadrature Amplitude Modulation using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding and XILINX SPARTAN Field Programmable Gate Array (FPGA) real-time implementation for validation. QAM is used in modern digital communication applications like set-top box, satellite TV, wireless and cellular technology etc. In this paper, 64-QAM is implemented and compared with three different XILINX SPARTAN FPGA devices say 3A DSP, 3E and 6E. The power, current and thermal parameters are performed and compared. The power consumed for the design of 64 QAM using the Xilinx SPARTAN 6E FPGA device is 0.014W and 15.9 C/W of Effective TJA for the XILINX SPARTAN 3A DSP FPGA. The device utilization of the 64-QAM design using the XILINX SPARTAN 3A DSP is low.
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Kim, Kyeong-Rok, and Jae-Hyun Kim. "Wideband Waveform Generation Using MDDS and Phase Compensation for X-Band SAR." Remote Sensing 12, no. 9 (May 1, 2020): 1431. http://dx.doi.org/10.3390/rs12091431.
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This study investigated wideband waveform generation using a field programmable gate array (FPGA) for X-band high-resolution synthetic aperture radar (SAR). Due to the range resolution determined by the bandwidth, we focused on wide bandwidth generation while preserving spectrum quality. The proposed method can generate wide bandwidth using a relatively low system clock. The new approach was designed in Simulink and implemented by very-high-speed-integrated-circuits hardware description language (VHDL). We also proposed a hardware structure in accordance with the proposed method. Signal connections of FPGA and digital analog converter (DAC) are described in the design of the proposed hardware structure. The developed X-band waveform generator using the proposed method output the desired pulse waveform. For the reduction of phase error and improvement of spectrum quality at the X-band, phase error compensation and pre-distortion were applied to the waveform generator. The results of the simulation and the hardware output demonstrate that the variation and standard deviation of the phase error were improved within the frequency spectrum. Accordingly, the proposed method and the developed waveform generator have the potential to produce a high-resolution image of the area of interest.
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Mylonas, Eleftherios, Nikolaos Tzanis, Michael Birbas, and Alexios Birbas. "An Automatic Design Framework for Real-Time Power System Simulators Supporting Smart Grid Applications." Electronics 9, no. 2 (February 9, 2020): 299. http://dx.doi.org/10.3390/electronics9020299.
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Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for real-time power system simulators is needed. In this article, a prototype of this approach is presented, employing Field Programmable Gate Array (FPGA) platforms due to their reconfigurability that enables low-power, low-latency, and high-performance designs, as a first attempt towards an open source platform, compatible with the majority of hardware design suites. It comprises two major parts: (i) a user-oriented section, built in Matlab/Simulink; and (ii) a hardware-oriented section, written in Matlab and Very High Speed Integrated Circuit (VHSIC)-Hardware Description Language (VHDL) code. To verify its functionality, two test power networks were given in a schematic format, analyzed through Matlab code and turned into dedicated hardware simulators with the aid of the VHDL template. Then, simulation results from Simulink and the prototype were compared for error estimation. The results show the prototype’s successful implementation with minimal resources utilization, high performance and low latency in the order of nanoseconds in Xilinx 6- and 7-series FPGAs, therefore proving its modularity and efficient use in many different scenarios, meeting low-latency/real-time requirements while enabling further smart grid research.
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Akbatı, Onur, Hatice Didem Üzgün, and Sirin Akkaya. "Hardware-in-the-loop simulation and implementation of a fuzzy logic controller with FPGA: case study of a magnetic levitation system." Transactions of the Institute of Measurement and Control 41, no. 8 (December 13, 2018): 2150–59. http://dx.doi.org/10.1177/0142331218813425.
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This paper presents the design and implementation of a fuzzy logic controller using Very High Speed Integrated Circuit Hardware Description Language (VHDL) on a field programmable gate array (FPGA). First, a Sugeno-type fuzzy logic controller with five triangular and trapezoidal membership functions for two inputs and with nine singleton membership functions for one output is examined. The proposed structure is tested with second- and third-order system model using FPGA-in-the-loop simulation via a MATLAB/Simulink environment. Then, for different kinds of fuzzy logic controllers, a new look-up table (LUT) and interpolation-based controller implementation is proposed to eliminate the computational complexity of the primarily designed structure. As a case study, a magnetic levitation system is controlled with an adaptive neuro-fuzzy inference system (ANFIS) trained fuzzy logic controller, then it is simulated and implemented using a LUT-based controller. Finally, we provide a comparison of results.
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Li, Jian Hua, Pin Rong Lin, Fu Sheng Shi, and Cai Jun Zheng. "Study on Magnetic Induced Polarization Technology and Instruments." Applied Mechanics and Materials 336-338 (July 2013): 100–105. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.100.
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In order to solve the difficult-ground areas of electromagnetic prospecting, we study magnetic induced polarization technology and instruments. Adopting the techniques such as GPS synchronization, CPLD(Complex Programmable Logic Device), digital PWM(Pulse-Width Modulation) constant current, VHDL(Very high speed integrated circuit Hardware Description Language) programming, a magnetic induced polarization instruments have been developed, which include transmitter, receiver, and three components magnetic field compensator. Instruments have functions such as high-power constant-current supplying, frequency-selective anti-interference receiving, GPS high-precision synchronizing, and amplitude-frequency response of magnetic sensor is flat. Using gradient configuration to obser the original data include magnetic field strength, magnetic polarization rate, phase, and get the magnetometric resistivity, the percent frequency efficiency by the further processing. For magnetic induced polarization instruments, we develop performance testing and the field experiments.
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Colín-Robles, José de Jesús, Ixbalank Torres-Zúñiga, Mario A. Ibarra-Manzano, and Víctor Alcaraz-González. "FPGA-Based Implementation of an Optimization Algorithm to Maximize the Productivity of a Microbial Electrolysis Cell." Processes 9, no. 7 (June 25, 2021): 1111. http://dx.doi.org/10.3390/pr9071111.
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In this work, the design of the hardware architecture to implement an algorithm for optimizing the Hydrogen Productivity Rate (HPR) in a Microbial Electrolysis Cell (MEC) is presented. The HPR in the MEC is maximized by the golden section search algorithm in conjunction with a super-twisting controller. The development of the digital architecture in the implementation step of the optimization algorithm was developed in the Very High Description Language (VHDL) and synthesized in a Field Programmable Gate Array (FPGA). Numerical simulations demonstrated the feasibility of the proposed optimization strategy embedded in an FPGA Cyclone II. Results showed that only 21% of the total logic elements, 5.19% of dedicated logic registers, and 64% of the total eight-bits multipliers of the FPGA were used. On the other hand, the estimated power consumption required by the FPGA-embedded optimization algorithm was only 146 mW.
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Estrada, Leonel, Nimrod Vázquez, Joaquín Vaquero, Ángel de Castro, and Jaime Arau. "Real-Time Hardware in the Loop Simulation Methodology for Power Converters Using LabVIEW FPGA." Energies 13, no. 2 (January 13, 2020): 373. http://dx.doi.org/10.3390/en13020373.
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Nowadays, the use of the hardware in the loop (HIL) simulation has gained popularity among researchers all over the world. One of its main applications is the simulation of power electronics converters. However, the equipment designed for this purpose is difficult to acquire for some universities or research centers, so ad-hoc solutions for the implementation of HIL simulation in low-cost hardware for power electronics converters is a novel research topic. However, the information regarding implementation is written at a high technical level and in a specific language that is not easy for non-expert users to understand. In this paper, a systematic methodology using LabVIEW software (LabVIEW 2018) for HIL simulation is shown. A fast and easy implementation of power converter topologies is obtained by means of the differential equations that define each state of the power converter. Five simple steps are considered: designing the converter, modeling the converter, solving the model using a numerical method, programming an off-line simulation of the model using fixed-point representation, and implementing the solution of the model in a Field-Programmable Gate Array (FPGA). This methodology is intended for people with no experience in the use of languages as Very High-Speed Integrated Circuit Hardware Description Language (VHDL) for Real-Time Simulation (RTS) and HIL simulation. In order to prove the methodology’s effectiveness and easiness, two converters were simulated—a buck converter and a three-phase Voltage Source Inverter (VSI)—and compared with the simulation of commercial software (PSIM® v9.0) and a real power converter.
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Mahmood, Hadeel SH. "FPGA configuration of an alloyed correlated branch predictor used with RISC processor for educational purposes." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 265. http://dx.doi.org/10.11591/ijece.v11i1.pp265-271.
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Instructions pipelining is one of the most outstanding techniques used in improving processor speed; nonetheless, these pipelined stages are constantly facing stalls that caused by nested conditional branches. During the execution of nested conditional branches, the behavior of the running branch depends on the history information of the previous ones; therefore, these branches have the greatest effect in reducing the prediction accuracy of a branch predictor among conditional branches. The purpose of this research is to reduce the stall cycles caused by correlated branches misprediction by introducing a hardware model of a branch predictor that combines both local and global prediction techniques. This predictor integrates the prediction characteristics of the alloyed predictor with those of the correlated predictor. the predictor design which implemented in VHDL (Very high-speed IC hardware description language) was inserted in previously designed MIPS (microprocessor without interlocked pipelined stages) processor and its prediction accuracy was confirmed by executing a program using the selection sort algorithm to sort 100 input numbers of different combinations ascendingly.
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Kung, Ying-Shieh, Seng-Chi Chen, Jin-Mu Lin, and Tsung-Chun Tseng. "FPGA-realization of a speed control IC for induction motor drive." Engineering Computations 33, no. 6 (August 1, 2016): 1835–52. http://dx.doi.org/10.1108/ec-08-2015-0260.
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Purpose – The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator, the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital converter interface circuit, etc. into one field programmable gate array (FPGA). Design/methodology/approach – First, the mathematical modeling of an IM drive, the field-oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the algorithms above. Third, based on electronic design automation simulator link, a co-simulation work constructed by ModelSim and Simulink is applied to verify the proposed VHDL code for the speed controller intellectual properties (IP). Finally, the developed VHDL code will be downloaded to the FPGA for further control the IM drive. Findings – In realization aspect, it only needs 5,590 LEs, 196,608 RAM bits, and 14 embedded 9-bit multipliers in FPGA to build up a speed control IP. In computational power aspect, the operation time to complete the computation of the PI controller, the slip speed estimator, the current vector controller are only 0.28 μs, 0.72 μs, and 0.96 μs, respectively. Practical implications – Fast computation in FPGA can speed up the speed response of IM drive system to increase the running performance. Originality/value – This is the first time to realize all the function of a speed controller for IM drive within one FPGA.
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Şişik, Fatih, and Eser Sert. "Support Vector Machine working on FPGA and the segmentation method of brain MR screening." International Journal of Innovative Research in Education 4, no. 3 (October 17, 2017): 120. http://dx.doi.org/10.18844/ijire.v4i3.2549.
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Alan Programlanabilir Kapı Dizileri (Field Programmable Gate Array-FPGA) programlanabilir sayısal bloklar ve bağlantılarını içeren cihazlar olup çok esnek ve hızlı çalışabilme özelliklerine sahiptir. Programlanabilen bu sayısal kapılar sayesinde karmaşık tasarımlar kolay bir şekilde geliştirilebilmektedir. FPGA’lar küçük boyutlarda olup bilgisayardan bağımsız mobil olarak ve bilgisayarlardan daha yüksek hızlarda çalışabilmektedirler. Veri madenciliğinin görevlerinden biri olan sınıflandırma probleminin çözümü için geliştirilmiş önemli makine öğrenimi algoritmalarından biri Destek Vektör Makineleri’ dir. Literatürde Destek Vektör Makineleri’ nin diğer birçok tekniğe göre daha başarılı sonuçlar verdiği kanıtlanmıştır. Tümör analizi, yüz tanıma, robotik göz oluşturma gibi konular, araştırmacıların görüntü işleme alanında yoğun olarak üzerinde çalıştıkları güncel, önemli ve zor problemlerden bazılarıdır. Bilgisayarda yapılan tümör analizinde, grafik ve resimlerin işlenmesinde yavaş işlem yapma ve aynı zamanda mobil olmama sorunlarından, FPGA donanımı ile görüntü işlemede bu sorunların üstesinden gelinmektedir. Bu çalışmada FPGA donanımında çalışan destek vektör makinası kullanılarak daha gerçekçi tümör analizi yapılarak tümörlü bölgelerin bulunması ve gerekli analiz sonuçlarının gösterilmesi amaçlanmaktadır. Böylece sağlık alanında da kullanılabilecek yararlı bir donanımın tasarımı gerçekleştirilecektir. Dolayısıyla gömülü sistemlerle anlatılan bu işlem süreçlerini gerçekleştiren çalışma sayısı çok az olduğundan çalışma özgün değer taşımaktadır. Buna ek olarak, FPGA’ ya özgü donanım tanımlama dillerinden biri olan Çok Yüksek Hızlı Tümleşik Devre Tanımlama Dili (Very High Speed Integrated Circuit Hardware Description Language- VHDL) kullanılacaktır. Bölütleme sonucunun değerlendirilmesi için Uniformity Measure (UM) kullanılmıştır. UM değerlendirme sonucunun başarılı olduğu görülmüştür.
Anahtar Kelimeler: Alan Programlanabilir Kapı Dizileri, FPGA, çok yüksek hızlı tümleşik devre tanımlama dili, vhdl, segmentasyon, destek vektör makinesi
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Pogra, Vivek, Amandeep Singh, Santosh Kumar Vishvakarma, and Balwinder Raj. "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Applications." Sensor Letters 18, no. 9 (September 1, 2020): 700–705. http://dx.doi.org/10.1166/sl.2020.4239.
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This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to SPI feature along with DMA on ASIC for IoT applications. It is described in very high speed integrated circuit hardware description language (VHDL) at register transfer level (RTL) and simulation is done on the Vivado 2016.2.
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Prashanth, B. U. V., Mohammed Riyaz Ahmed, and Manjunath R. Kounte. "Design and implementation of DA FIR filter for bio-inspired computing architecture." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (April 1, 2021): 1709. http://dx.doi.org/10.11591/ijece.v11i2.pp1709-1718.
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This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability.
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Jhang, Jyun-Yu, Kuang-Hui Tang, Chuan-Kuei Huang, Cheng-Jian Lin, and Kuu-Young Young. "FPGA Implementation of a Functional Neuro-Fuzzy Network for Nonlinear System Control." Electronics 7, no. 8 (August 11, 2018): 145. http://dx.doi.org/10.3390/electronics7080145.
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This study used Xilinx Field Programmable Gate Arrays (FPGAs) to implement a functional neuro-fuzzy network (FNFN) for solving nonlinear control problems. A functional link neural network (FLNN) was used as the consequent part of the proposed FNFN model. This study adopted the linear independent functions and the orthogonal polynomials in a functional expansion of the FLNN. Thus, the design of the FNFN model could improve the control accuracy. The learning algorithm of the FNFN model was divided into structure learning and parameter learning. The entropy measurement was adopted in the structure learning to determine the generated new fuzzy rule, whereas the gradient descent method in the parameter learning was used to adjust the parameters of the membership functions and the weights of the FLNN. In order to obtain high speed operation and real-time application, a very high speed integrated circuit hardware description language (VHDL) was used to design the FNFN controller and was implemented on FPGA. Finally, the experimental results demonstrated that the proposed hardware implementation of the FNFN model confirmed the viability in the temperature control of a water bath and the backing control of a car.
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Amer Abbas, Yasir, Razali Jidin, Norziana Jamil, Muhammad Reza Z’aba, and Mohamad Afendee Mohamed. "Photon: a new mix columns architecture on FPGA." International Journal of Engineering & Technology 7, no. 2.14 (April 6, 2018): 138. http://dx.doi.org/10.14419/ijet.v7i2.14.12814.
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Lightweight cryptography is an important element in smart devices that require data security as one of the features. These smart devices utilize cryptography when transferring sensitive data. Most of the smart devices are resource constrained devices and thus possess limited computing capability and low memory space. The PHOTON hash function algorithm is a promising lightweight cryptography approach for resource-constrained devices. It has a complex operation called MixColumns. This paper presents a new MixColumns architecture for PHOTON implemented on Field Programmable Gate Array (FPGA) device. In our design, the number of complex multiplication opera-tions is reduced by utilizing comparators that are based on four-bit Galois operations. The efficient PHOTON hardware design was coded using a very high speed integrated circuit hardware description language, VHDL. The design was successfully synthesized, mapped, simu-lated and tested on two FPGA evaluation boards namely, Sparten3 and Artix-7. The results show that the proposed design achieve a throughput of 582 Mbps and an efficiency of 1.55 Gbps/slice for Spartan3, while a throughput of 1.41 Gbps and efficiency of 8.66 Gbps/slice are obtained for Artix-7. The performance on both platforms has superseded performance of existing implementations in litera-ture.
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Faleh Hassan, Raaed. "Performance Investigation of Digital Lowpass IIR Filter Based on Different Platforms." International journal of electrical and computer engineering systems 12, no. 2 (June 21, 2021): 105–11. http://dx.doi.org/10.32985/ijeces.12.2.5.
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The work presented in this paper illuminates the design and simulation of a recursive or Infinite Impulse Response (IIR) filter. The proposed design algorithm employs the Genetic Algorithm to determine the filter coefficients to satisfy the required performance. The effectiveness of different platforms on filter design and performance has been studied in this paper. Three different platforms are considered to implement and verify the designed filter’s work through simulation. The first platform is the MATLAB/SIMULINK software package used to implement the Biquad form filter. This technique is the basis for the software implementation of the designed IIR filter. The HDL – Cosimulation technique is considered the second one; it inspired to take advantage of the existing tools in SIMULINK to convert the designed filter algorithm to the Very high-speed integrated circuit Hardware Description Language (VHDL) format. The System Generator is employed as the third technique, in which the designed filter is implemented as a hardware structure based on basic unit blocks provided by Xilinx System Generator. This technique facilitates the implementation of the designed filter in the FPGA target device. Simulation results show that the performance of the designed filter is remarkably reliable even with severe noise levels.
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Han, Bang Cheng, Dan He, Fang Zheng Guo, Yu Wang, and Bing Nan Huang. "The FPGA-Based Phase-Locked Loop Speed Control System of BLDCM for Magnetically Suspended Control Moment Gyroscope." Applied Mechanics and Materials 80-81 (July 2011): 1249–57. http://dx.doi.org/10.4028/www.scientific.net/amm.80-81.1249.
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A phase-locked loop (PLL) control system based on field programmable gates array (FPGA) is proposed through analyzing the model of three-phase unipolar-driven BLDCM (brushless direct current motor) to enhance the reliability and accurate steady-state speed for magnetically suspended control moment gyroscope (MSCMG). The numerical operation module, PLL module and current-loop control module are designed based on FPGA using very-high-speed integrated circuit hardware description language (VHDL) to realize the control law of the digital system. The pulse width modulation (PWM) generating module for Buck converter, the commutation signal generating module for the inverter and ADC module are designed for driving the motor and sampling the current signal. The PLL is analyzed and optimized in the paper and all the modules are verified using the software of ModelSim and the experiments. The simulation and experiment results on BLDCM of MSCMG show that the stability of the motor velocity can reach 0.01% and 0.02% respectively by the PLL technology based on FPGA, which is difficult to be obtained by conventional proportion integral different (PID) speed control.
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H Bailmare, Ravi, S. J. Honale, and Pravin V Kinge. "Design and Implementation of Adaptive FIR filter using Systolic Architecture." International Journal of Reconfigurable and Embedded Systems (IJRES) 3, no. 2 (July 1, 2014): 54. http://dx.doi.org/10.11591/ijres.v3.i2.pp54-61.
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<p>The tremendous growth of computer and Internet technology wants a data to be process with a high speed and in a powerful manner. In such complex environment, the conventional methods of performing multiplications are not suitable to obtain the perfect solution. To obtain perfect solution parallel computing is use in contradiction. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture is used. Systolic architecture is an arrangement of processor where data flows synchronously across array element. This project demonstrates an effective design for adaptive filter using Systolic architecture for DLMS algorithm, synthesized and simulated on Xilinx ISE Project navigator tool in very high speed integrated circuit hardware description language (VHDL) and Field Programmable Gate Arrays (FPGAs). Here, by combining the concept of pipelining and parallel processing in to the systolic architecture the computing speed increases.</p>
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Vu Quynh, Nguyen. "The Fuzzy PI Controller for PMSM’s Speed to Track the Standard Model." Mathematical Problems in Engineering 2020 (July 13, 2020): 1–20. http://dx.doi.org/10.1155/2020/1698213.
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This paper proposes a fuzzy PI controller to control the speed of a permanent magnet synchronous motor (PMSM). The structure of the system includes the speed loop controller (SLC) and the current loop controller (CLC). The speed loop controller is the fuzzy PI and standard model (SM). The CLC includes vector control and the space vector pulse width modulation (SVPWM). It compiles two closed-loop control systems for the PMSM. This research uses a very high-speed integrated circuit hardware description language (VHDL) to implement the proposed algorithm and embed it into Matlab/Simulink for simulation. Based on the PMSM parameter, this article tests the controller’s correctness with some of the load cases by changing the combined inertia and viscous friction of rotor and load. After success in simulation, the system is tested again by experiment on the FPGA kit. The simulation and experiment results show that when the load changes, the PMSM speed is still stable. The novelty of this research is that it compares two kinds of controllers between simulation and experiment results.
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Prasad, Hanuman, and Tanmoy Maity. "Modeling and reliability analysis of three phase z-source AC-AC converter." Archives of Electrical Engineering 66, no. 4 (December 20, 2017): 731–43. http://dx.doi.org/10.1515/aee-2017-0055.
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Abstract This paper presents the small signal modeling using the state space averaging technique and reliability analysis of a three-phase z-source ac-ac converter. By controlling the shoot-through duty ratio, it can operate in buck-boost mode and maintain desired output voltage during voltage sag and surge condition. It has faster dynamic response and higher efficiency as compared to the traditional voltage regulator. Small signal analysis derives different control transfer functions and this leads to design a suitable controller for a closed loop system during supply voltage variation. The closed loop system of the converter with a PID controller eliminates the transients in output voltage and provides steady state regulated output. The proposed model designed in the RT-LAB and executed in a field programming gate array (FPGA)-based real-time digital simulator at a fixedtime step of 10 μs and a constant switching frequency of 10 kHz. The simulator was developed using very high speed integrated circuit hardware description language (VHDL), making it versatile and moveable. Hardware-in-the-loop (HIL) simulation results are presented to justify the MATLAB simulation results during supply voltage variation of the three phase z-source ac-ac converter. The reliability analysis has been applied to the converter to find out the failure rate of its different components.
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Faeq, Mays K., and Safaa S. Omran. "Cache coherency controller for MESI protocol based on FPGA." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (April 1, 2021): 1043. http://dx.doi.org/10.11591/ijece.v11i2.pp1043-1052.
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In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultanously for more than one job or all the cores working in parallel for the same job. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So if one core requestes a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores.This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using very high speed integrated circuit hardware description language (VHDL) coding and implemented using ISE Xilinx software. The protocol used in this design is the modified, exclusive, shared and invalid (MESI) protocol. Test results were taken by using test bench, and showed all the states of the protocol are working correctly.
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Mayer, Kayol Soares, Candice Müller, Fernando Cesar Comparsi de Castro, and Maria Cristina Felippetto de Castro. "A New CPFSK Demodulation Approach for Software Defined Radio." Journal of Circuits, Systems and Computers 28, no. 14 (February 8, 2019): 1950243. http://dx.doi.org/10.1142/s0218126619502438.
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This paper proposes a new coherent Frequency-Shift Keying (FSK) demodulation technique for software defined radio platform, based on a new Digital Phase Locked Loop (DPLL) architecture. The proposed DPLL addresses the frequency dependence on classic DPLL architectures found in the literature. In classical approaches, the loop filter constants are dependent on the frequency level of the FSK transmitted symbols. The proposed approach applies a simpler feedback loop, with a single integrator and a phase detector architecture based on the small-angle approximation [Formula: see text], which resulted in a DPLL totally independent of frequency. The proposed demodulator has been implemented in Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) and evaluated for continuous-phase frequency shift keying (CPFSK) and Gaussian minimum shift keying (GMSK) signals. For CPFSK signals, the demodulator has been evaluated for 2, 4 and 8 frequency levels, with modulation indexes [Formula: see text], [Formula: see text] and [Formula: see text], respectively. For evaluation of GMSK signals, several Gaussian filter bandwidths were considered. In addition, a brief analysis for 2-CPFSK and GMSK is presented over multipath and carrier frequency offset. Results show that the proposed method presents a significantly reduced bit error rate when compared to other coherent methods presented in the literature.
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Swarup Kumar, J. N. V. R., and D. Suresh. "Automated Secured Data Delivery for Next Generation Optical Networks." Asian Journal of Computer Science and Technology 7, S1 (November 5, 2018): 104–7. http://dx.doi.org/10.51983/ajcst-2018.7.s1.1794.
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The present cloud benefit measurements truly are stunning. By one year from now 80% of all new programming will be accessible as a cloud benefit, 58% of all Internet activity is guage to be video in only two years and before the decade’s over, 20 billion brilliant gadgets will be associated with the system. There is no uncertainty this will make difficulties wherever in the system. However, with this test, there regularly comes chance to go into the new optical system; never again is it only an asset for transporting bits. What’s more, it’s more than expanding limit. What’s new is the requirement for specialist organizations’ optical systems to end up increasingly “coordinated” and “consumable” enabling them to understand the undiscovered capability of their system. It ought to be a basic element of the developing cloud framework associating clients to their substance and applications. Security is a basic necessity for the system in light of the fact that the touchy data can be gotten to remotely and this makes the whole framework helpless against pernicious assaults. This paper exhibits the AES-256 calculation with respect to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL) for a secured information transmission in the Agile Optical Networks (AON).
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Rudnicki, Kamil, Tomasz P. Stefański, and Wojciech Żebrowski. "Open-Source Coprocessor for Integer Multiple Precision Arithmetic." Electronics 9, no. 7 (July 14, 2020): 1141. http://dx.doi.org/10.3390/electronics9071141.
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This paper presents an open-source digital circuit of the coprocessor for an integer multiple-precision arithmetic (MPA). The purpose of this coprocessor is to support a central processing unit (CPU) by offloading computations requiring integer precision higher than 32/64 bits. The coprocessor is developed using the very high speed integrated circuit hardware description language (VHDL) as an intellectual property (IP) core. Therefore, it can be implemented within field programmable gate arrays (FPGAs) at various scales, e.g., within a system on chip (SoC), combining CPU cores and FPGA within a single chip as well as FPGA acceleration cards. The coprocessor handles integer numbers with precisions in the range 64 bits–32 kbits, with the limb size set to 64 bits. In our solution, the sign-magnitude representation is used to increase the efficiency of the multiplication operation as well as to provide compatibility with existing software libraries for MPA. The coprocessor is benchmarked in factorial ( n ! ), exponentiation ( n n ) and discrete Green’s function (DGF) computations on Xilinx Zynq-7000 SoC on TySOM-1 board from Aldec. In all benchmarks, the coprocessor demonstrates better runtimes than a CPU core (ARM Cortex A9) executing the same computations using a software MPA library. For sufficiently large input parameters, our coprocessor is up to three times faster when implemented in FPGA on SoC, rising to a factor of ten in DGF computations. The open-source coprocessor code is licensed under the Mozilla Public License.
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Wei Chun, Quek, Pang Wai Leong, Chan Kah Yoong, Lee It Ee, and Chung Gwo Chin. "HDL Modelling of Low-CostMemory Fault Detection Tester." Journal of Engineering Technology and Applied Physics 2, no. 2 (December 15, 2020): 17–23. http://dx.doi.org/10.33093/jetap.2020.2.2.3.
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Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE)to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly(at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has in spired us to design a low-cost memory tester. A low-cost memory fault detection tester with all the major fault detection algorithms that used in industry is modelled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) in this paper to support the need of the low-cost ATE memory tester. The fault detection algorithms modelled are MATS+ (Modified Algorithm Test Sequence), MATS++, March C, March C-, March X ,March Y, zero-one and checkerboard scan tests. PERL program is used to analyse the simulation results and a log file will be generated at the end of the memory test. Extensive simulation and experimental test results show that the memory tester modelled covers all the memory test algorithms used in the industry. The low-cost memory fault detection tester designed provides the 100% fault detection coverage for all memory defects.
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Aldair, Ammar. "FPGA Based Modified Fuzzy PID Controller for Pitch Angle of Bench-top Helicopter." Iraqi Journal for Electrical and Electronic Engineering 8, no. 8 (June 1, 2012): 12–24. http://dx.doi.org/10.37917/ijeee.8.1.2.
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Fuzzy PID controller design is still a complex task due to the involvement of a large number of parameters in defining the fuzzy rule base. To reduce the huge number of fuzzy rules required in the normal design for fuzzy PID controller, the fuzzy PID controller is represented as Proportional-Derivative Fuzzy (PDF) controller and Proportional-Integral Fuzzy (PIF) controller connected in parallel through a summer. The PIF controller design has been simplified by replacing the PIF controller by PDF controller with accumulating output. In this paper, the modified Fuzzy PID controller design for bench-top helicopter has been presented. The proposed Fuzzy PID controller has been described using Very High Speed Integrated Circuit Hardware Description Language (VHDL) and implemented using the Field Programmable Gate Array (FPGA) board. The bench-top helicopter has been used to test the proposed controller. The results have been compared with the conventional PID controller and Internal Model Control Tuned PID (IMC-PID) Controller. Simulation results show that the modified Fuzzy PID controller produces superior control performance than the other two controllers in handling the nonlinearity of the helicopter system. The output signal from the FPGA board is compared with the output of the modified Fuzzy PID controller to show that the FPGA board works like the Fuzzy PID controller. The result shows that the plant responses with the FPGA board are much similar to the plant responses when using simulation software based controller.
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Sciuto, D. "VHDL( VHSIC Hardware Description Language)." Journal of Systems Architecture 42, no. 2 (September 1996): 95–96. http://dx.doi.org/10.1016/1383-7621(96)00015-x.
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