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Journal articles on the topic 'VHDL (Very hardware description language)'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

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1

Yi, Zhao Xiang, Xiong Mei Zhang, Ning Li, and Xiao Dong Mu. "A Visual Dependency Analysis Method Based on VHDL." Applied Mechanics and Materials 738-739 (March 2015): 582–85. http://dx.doi.org/10.4028/www.scientific.net/amm.738-739.582.

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Modern complex circuits are described in very high speed integrated circuit hardware description language (VHDL) and difficult to verify. This paper proposes a systematic and visual dependency analysis method based on VHDL. The dependency relationships including control dependency, data dependency, signal control dependency and signal data dependency are defined. The entity dependency graph is presented and its generation algorithm, which searches the dependency relationships in hardware processes and between hardware processes, are developed. The experiment of a typical keyboard demonstrates

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2

Shiva, Sajjan G., and Judit U. Jones. "A VHDL Based Expert System for Hardware Synthesis." VLSI Design 1, no. 2 (1994): 113–26. http://dx.doi.org/10.1155/1994/93168.

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This paper describes an expert system for Hardware Synthesis. Details of the target digital system are input to the expert system using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The VHDL representation is first translated to a knowledge representation scheme known as a ‘hologram’ which is a combination of rule, frame and semantic network representation schemes. The hologram representation of the target system is then input to the inference engine, which matches the target system to the Knowledge Base components and selects an appropriate set for implementation, a

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Shetty, Mamtha. "Design of BPSK Modulator Using VHDL." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, no. 12 (2014): 5247–52. http://dx.doi.org/10.24297/ijct.v13i12.5276.

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Binary Phase Shift Keying represents the simulation results of binary digital modulation schemes. Here for BASK and BPSK modulation techniques use FPGA algorithm. If multiplier block is used for multiplication bit stream with carrier signal, used time will rises. In addition using multiplier block obtained simulation results were analyzed and compared to other simulation results. Source consumptions of FPGA-based BASK modulation technique and BPSK modulation technique were compared. Also, for different modulation algorithm, source consumptions of BASK and BPSK modulation technique were analyze

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Zhu, Juan, and Yue Chen. "Step Motor Control Based on FPGA." Applied Mechanics and Materials 397-400 (September 2013): 1226–29. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.1226.

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Design a step motor control system based on Field Programmable Gate Array (FPGA). Give the hardware circuit of this system and the program based on very high speed integrated circuit hardware description language (VHDL). Compared to step motor control system based on single chip microcomputer, the processing speed of this system is faster.

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Palanisamy, R., C. S. Boopathi, K. Selvakumar, and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1722. http://dx.doi.org/10.11591/ijece.v10i2.pp1722-1727.

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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse

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Palanisamy, R., and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (2019): 81. http://dx.doi.org/10.11591/ijres.v8.i2.pp81-85.

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<p>This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switchi

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Miriampally, Venkata Raghavendra. "Simulation of PCI Express™ Transaction Layer Using Hardware Description Language." International Journal of Informatics and Communication Technology (IJ-ICT) 4, no. 1 (2015): 7. http://dx.doi.org/10.11591/ijict.v4i1.pp7-12.

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<p>PCI Express is a high-speed serial connection that operates more like a network than a bus.<strong> </strong>PCI Express will serve as a general purpose I/O interconnects for a wide variety of future computing and communications platforms.<strong> </strong>PCI Express (PCIe) is implemented with a split-transaction protocol that provides more bandwidth and is compatible with existing operating systems. PCI Express has three discrete logical layers: the Transaction Layer, the Data Link Layer, and the Physical Layer. This paper analyze and simulates the function o

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Zhang, Zi Sheng, Chun Sheng Wang, Yi Wang, Zhan You Wang, and Deng Yuan Song. "Power and Vibration of Electrostatic Precipitator Control Based on FPGA." Advanced Materials Research 1037 (October 2014): 244–47. http://dx.doi.org/10.4028/www.scientific.net/amr.1037.244.

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In order to improve the automation level of the electrostatic precipitator, we used Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) language to compile, emulate and optimize the control system of power source and vibration. In the design of Quartus platform, we used EP1C3T144C8 Field Programmable Gate Array (FPGA) chip to realize high voltage power supply, alarm and protection system. We also realized the compilation and simulation test of each part’s function of 20 s rapping and 40 min rapping cycle. At the same time, we recorded the waveform of simulation. It demonstr

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9

Zhang, Zi Sheng, Yi Wang, Chun Sheng Wang, Jin Cui, and Zhi Qiang Liu. "The Control of High Voltage Electrostatic Precipitator Based on EDA." Advanced Materials Research 910 (March 2014): 336–39. http://dx.doi.org/10.4028/www.scientific.net/amr.910.336.

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In order to achieve the automatic control of electrostatic precipitator (ESP) more efficiently and accurately, an ESP system combining hardware and software is designed. According to the requirement of the ESP system,the Electronic Design Automation (EDA) is introduced to the ESP control system and the system is divided into four modules.These sub-modules are designed and the simulation waveform of the system is ananalyzed,based on the Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) programming language and Quartus software.The results show that the security, flexibilit

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Shieh, Cheng Shion. "From Simulation to FPGA Control Circuit Implementation for Wind Power with Battery Charging." Advanced Materials Research 588-589 (November 2012): 777–80. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.777.

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While application of field-programmable gate array (FPGA) chip has been extensively investigated, the charging control is relatively unexplored. This paper proposes a flow chart of energy storage for wind power system with Lead-Acid battery whose charging control is constructed by Very High Speed Integrated Circuit Hardware Description Language (VHDL) code. This research focuses on the proposed digital control algorithm can be directly downloaded into field-programmable gate array (FPGA) chip after simulation finishing. This saves greatly time on hardware circuit design. A simulation is presen

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Sahu, Gokulananda, Rajesh Kumar Patjoshi, and Rakhee Panigrahi. "An FPGA Based Novel Digital Controller for DSTATCOM to Enhance Power Quality in Distribution System." ECTI Transactions on Electrical Engineering, Electronics, and Communications 18, no. 2 (2020): 118–29. http://dx.doi.org/10.37936/ecti-eec.2020182.240340.

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This paper proposes an FPGA based all-on-chip novel digital controller for DSTATCOM to compensate harmonics and reactive power existing in power distribution system. The proposed technique extracts reference current by considering instantaneous symmetrical component active power (ISCAP) theory based phase delay compensation (PDC) control technique. The proposed controller comprises positive sequence detector, PI-controller, low-pass filters (LPF) and hysteresis current controller. All these segments are configured on high speed, low cost field programmable gate arrays (FPGA) hardware resources

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Quynh, Nguyen Vu, Ying Shieh Kung, Pham Van Dung, Kuan Yuen Liao, and Sheng Wei Chen. "FPGA-Realization of Vector Control for PMSM Drives." Applied Mechanics and Materials 311 (February 2013): 249–54. http://dx.doi.org/10.4028/www.scientific.net/amm.311.249.

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The design and implementation of a vector control for Permanent Magnetic Synchronous Motor (PMSM) based on Field Programmable Gate Array (FPGA) technology is presented in this paper. Firstly, a Space Vector Pulse Width Modulation (SVPWM) scheme, vector control method and PI controller are derived. Secondly, the Very-High-Speed IC Hardware Description Language (VHDL) is adopted to describe the behavior of the aforementioned control algorithms. Finally, an experimental system is setup to evaluate the effectiveness and correctness of the proposed vector controller for PMSM drives.

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Kung, Ying Shieh, Nguyen Phan Thanh, and Hsin Hung Chou. "Design and Implementation of a Microprocessor-Based PI Controller for PMSM Drives." Applied Mechanics and Materials 764-765 (May 2015): 496–500. http://dx.doi.org/10.4028/www.scientific.net/amm.764-765.496.

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This work presents a hardware implementation of a simple microprocessor; then uses this microprocessor to design a PI controller for PMSM (Permanent Magnet Synchronous Motor) drives. In this paper, firstly, the mathematical model of PMSM drives is illustrated. Secondly, the architecture of a simple microprocessor based on RTL (Register Transfer Level) method is proposed and the VHDL (Very high speed IC Hardware Description Language) is adopted to describe the behavior of the simple microprocessor. Thirdly, a machine code of PI controller based on the proposed simple microprocessor is designed.

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Kamar, Sara, Abdelmoniem Fouda, Abdelhalim Zekry, and Abdelmoniem Elmahdy. "FPGA implementation of RS codec with interleaver in DVB-T using VHDL." International Journal of Engineering & Technology 6, no. 4 (2017): 171. http://dx.doi.org/10.14419/ijet.v6i4.8205.

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Digital television (DTV) provides a huge amount of information to many users at low cost. Recently, it can be packaged and fully integrated into completely digital transmission networks. Reed-Solomon code (RS) is one type of error correcting codes that can be used to enhance the performance of DTV. Interleaving/deinterleaving process enhances the performance of channel errors by spreading out random errors, very high-speed hardware description language (VHDL) is used in electronic design automation. It can be used as a general-purpose parallel programming language.This paper presents VHDL prog

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Ali, Fakhrulddin, Mohammed Hussein, and Sinan Ismael. "LabVIEW FPGA Implementation Of a PID Controller For D.C. Motor Speed Control." Iraqi Journal for Electrical and Electronic Engineering 6, no. 2 (2010): 139–44. http://dx.doi.org/10.37917/ijeee.6.2.9.

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This Paper presents a novel hardware design methodology of digital control systems. For this, instead of synthesizing the control system using Very high speed integration circuit Hardware Description Language (VHDL), LabVIEW FPGA module from National Instrument (NI) is used to design the whole system that include analog capture circuit to take out the analog signals (set point and process variable) from the real world, PID controller module, and PWM signal generator module to drive the motor. The physical implementation of the digital system is based on Spartan-3E FPGA from Xilinx. Simulation

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Sideris, Argyrios, Theodora Sanida, and Minas Dasygenis. "High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor." Technologies 8, no. 1 (2020): 15. http://dx.doi.org/10.3390/technologies8010015.

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Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL

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Sun, Hao, Xin Wen Duan, and Yuan Liu. "Design of Digital Cymometer Based on EDA Technology." Applied Mechanics and Materials 719-720 (January 2015): 517–21. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.517.

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To overcome the shortcoming that the traditional cymometer has a relatively large delay, small measuring range, low precision, poor reliability and complicated circuit; A design of digital cymometer based on EDA technology is proposed. The design is programmed with the hardware description language of VHDL. And it takes full advantages of Max+PlusII software to compile and simulate. All the functions are downloaded into and debugged on the chip of EP1K100QC in ACEX1K series from Altera Company. The experimental results show that this system has a very high reliability and small measuring error

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18

Zhang, Zi Sheng, Peng Bo Ge, Xiao Dong Shi, Bo Feng Liu, and Zhi Qiang Liu. "The Control System of High Voltage Electrostatic Precipitator Based on FPGA." Advanced Materials Research 823 (October 2013): 528–31. http://dx.doi.org/10.4028/www.scientific.net/amr.823.528.

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It is urgent to study a new control system for improving the efficiency of electrostatic precipitator. The System-on-a-Programmable-Chip (SOPC) development board, which belongs to the series of Cyclone of Altera Company, is used as the development platform. Analog Digital (AD) conversion module, voltage control module and overall control module of the electrostatic precipitator are designed and the simulation waveform of the system is analyzed, based on the programmable logic device EP1C12Q240C6 and Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) programming language. T

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19

Kung, Ying-Shieh, Ming-Kuang Wu, Hai Linh Bui Thi and, Tz-Han Jung, Feng-Chi Lee, and Wen-Chuan Chen. "FPGA-based hardware implementation of arctangent and arccosine functions for the inverse kinematics of robot manipulator." Engineering Computations 31, no. 8 (2014): 1679–90. http://dx.doi.org/10.1108/ec-11-2012-0290.

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Purpose – The inverse kinematics in robot manipulator have to handle the arctangent and arccosine function. However, the two functions are complicated and need much computation time so that it is difficult to be realized in the typical processing system. The purpose of this paper is to solve this problem by using Field Programmable Gate Array (FPGA) to speed up the computation power. Design/methodology/approach – The Taylor series expansion method is firstly applied to transfer arctangent and arccosine function to a polynomial form. And Look-Up Table (LUT) is used to store the parameters of th

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Kulakovskis, Darius, and Dalius Navakauskas. "Automated Metabolic P System Placement in FPGA." Electrical, Control and Communication Engineering 10, no. 1 (2016): 5–12. http://dx.doi.org/10.1515/ecce-2016-0001.

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Abstract An original Very High Speed Integrated Circuit Hardware Description Language (VHDL) code generation tool that can be used to automate Metabolic P (MP) system implementation in hardware such as Field Programmable Gate Arrays (FPGA) is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed

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Hai Linh, Bui Thi, and Ying-Shieh Kung. "Digital Hardware Realization of Forward and Inverse Kinematics for a Five-Axis Articulated Robot Arm." Mathematical Problems in Engineering 2015 (2015): 1–10. http://dx.doi.org/10.1155/2015/906505.

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When robot arm performs a motion control, it needs to calculate a complicated algorithm of forward and inverse kinematics which consumes much CPU time and certainty slows down the motion speed of robot arm. Therefore, to solve this issue, the development of a hardware realization of forward and inverse kinematics for an articulated robot arm is investigated. In this paper, the formulation of the forward and inverse kinematics for a five-axis articulated robot arm is derived firstly. Then, the computations algorithm and its hardware implementation are described. Further, very high speed integra

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V. Kinge, Pravin, S. J. Honale, and C. M. Bobade. "Design of AES Algorithm for 128/192/256 Key Length in FPGA." International Journal of Reconfigurable and Embedded Systems (IJRES) 3, no. 2 (2014): 49. http://dx.doi.org/10.11591/ijres.v3.i2.pp49-53.

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<p class="p0">The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. The available AES algorithm is used for data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to AES algorithm, to obtain the encrypted image. and the encrypted image is the input to AES Decryption t

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Lv, Fu Xing, and Ying Gao. "Speed Control Scheme for BLDC Drive with Nonlinear Fuzzy PID Control Based on DSP and FPGA." Advanced Materials Research 466-467 (February 2012): 1275–78. http://dx.doi.org/10.4028/www.scientific.net/amr.466-467.1275.

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Because of its high performance, brushless DC motors are widely used in vehicles. But the brushless DC motor speed system itself is easily influenced by the parameter variation, the cogging torque and the load disturbance. And some complex algorithms to overcome the deficiency are difficult to implement on a single DSP chip. To solve the problem, the paper represents a nonlinear PID controller based on DSP and FPGA. A functional design of FPGA in a brushless DC motor system based on FPGA and DSP was completed by using modular design method. All the function modules are programmed by Very-High-

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Wang, Mu Lan, Jian Min Zuo, Kun Liu, and Xing Hua Zhu. "FPGA-Based Intelligent Software Hardening Chip for Computer Numerical Control System." Applied Mechanics and Materials 105-107 (September 2011): 2217–20. http://dx.doi.org/10.4028/www.scientific.net/amm.105-107.2217.

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In order to meet the development demands for high-speed and high-precision of Computer Numerical Control (CNC) machine tools, the equipped CNC systems begin to employ the technical route of software hardening. Making full use of the advanced performance of Large Scale Integrated Circuits (LSIC), this paper puts forward using Field Programmable Gates Array (FPGA) for the functional modules of CNC system, which is called Intelligent Software Hardening Chip (ISHC). The CNC system architecture with high performance is constructed based on the open system thought and ISHCs. The corresponding progra

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Anthony Prathap, Joseph, T. S.Anandhi, K. Ramash Kumar, and B. Srikanth. "Performance evaluation and analysis of 64-quadrature amplitude modulator using Xilinx Spartan FPGA." International Journal of Engineering & Technology 7, no. 2.8 (2018): 570. http://dx.doi.org/10.14419/ijet.v7i2.8.10523.

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This paper proposes the design of 64-Quadrature Amplitude Modulation using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding and XILINX SPARTAN Field Programmable Gate Array (FPGA) real-time implementation for validation. QAM is used in modern digital communication applications like set-top box, satellite TV, wireless and cellular technology etc. In this paper, 64-QAM is implemented and compared with three different XILINX SPARTAN FPGA devices say 3A DSP, 3E and 6E. The power, current and thermal parameters are performed and compared. The power consumed for the

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Kim, Kyeong-Rok, and Jae-Hyun Kim. "Wideband Waveform Generation Using MDDS and Phase Compensation for X-Band SAR." Remote Sensing 12, no. 9 (2020): 1431. http://dx.doi.org/10.3390/rs12091431.

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This study investigated wideband waveform generation using a field programmable gate array (FPGA) for X-band high-resolution synthetic aperture radar (SAR). Due to the range resolution determined by the bandwidth, we focused on wide bandwidth generation while preserving spectrum quality. The proposed method can generate wide bandwidth using a relatively low system clock. The new approach was designed in Simulink and implemented by very-high-speed-integrated-circuits hardware description language (VHDL). We also proposed a hardware structure in accordance with the proposed method. Signal connec

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Mylonas, Eleftherios, Nikolaos Tzanis, Michael Birbas, and Alexios Birbas. "An Automatic Design Framework for Real-Time Power System Simulators Supporting Smart Grid Applications." Electronics 9, no. 2 (2020): 299. http://dx.doi.org/10.3390/electronics9020299.

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Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for r

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Akbatı, Onur, Hatice Didem Üzgün, and Sirin Akkaya. "Hardware-in-the-loop simulation and implementation of a fuzzy logic controller with FPGA: case study of a magnetic levitation system." Transactions of the Institute of Measurement and Control 41, no. 8 (2018): 2150–59. http://dx.doi.org/10.1177/0142331218813425.

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This paper presents the design and implementation of a fuzzy logic controller using Very High Speed Integrated Circuit Hardware Description Language (VHDL) on a field programmable gate array (FPGA). First, a Sugeno-type fuzzy logic controller with five triangular and trapezoidal membership functions for two inputs and with nine singleton membership functions for one output is examined. The proposed structure is tested with second- and third-order system model using FPGA-in-the-loop simulation via a MATLAB/Simulink environment. Then, for different kinds of fuzzy logic controllers, a new look-up

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Li, Jian Hua, Pin Rong Lin, Fu Sheng Shi, and Cai Jun Zheng. "Study on Magnetic Induced Polarization Technology and Instruments." Applied Mechanics and Materials 336-338 (July 2013): 100–105. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.100.

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In order to solve the difficult-ground areas of electromagnetic prospecting, we study magnetic induced polarization technology and instruments. Adopting the techniques such as GPS synchronization, CPLD(Complex Programmable Logic Device), digital PWM(Pulse-Width Modulation) constant current, VHDL(Very high speed integrated circuit Hardware Description Language) programming, a magnetic induced polarization instruments have been developed, which include transmitter, receiver, and three components magnetic field compensator. Instruments have functions such as high-power constant-current supplying,

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Colín-Robles, José de Jesús, Ixbalank Torres-Zúñiga, Mario A. Ibarra-Manzano, and Víctor Alcaraz-González. "FPGA-Based Implementation of an Optimization Algorithm to Maximize the Productivity of a Microbial Electrolysis Cell." Processes 9, no. 7 (2021): 1111. http://dx.doi.org/10.3390/pr9071111.

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In this work, the design of the hardware architecture to implement an algorithm for optimizing the Hydrogen Productivity Rate (HPR) in a Microbial Electrolysis Cell (MEC) is presented. The HPR in the MEC is maximized by the golden section search algorithm in conjunction with a super-twisting controller. The development of the digital architecture in the implementation step of the optimization algorithm was developed in the Very High Description Language (VHDL) and synthesized in a Field Programmable Gate Array (FPGA). Numerical simulations demonstrated the feasibility of the proposed optimizat

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Estrada, Leonel, Nimrod Vázquez, Joaquín Vaquero, Ángel de Castro, and Jaime Arau. "Real-Time Hardware in the Loop Simulation Methodology for Power Converters Using LabVIEW FPGA." Energies 13, no. 2 (2020): 373. http://dx.doi.org/10.3390/en13020373.

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Nowadays, the use of the hardware in the loop (HIL) simulation has gained popularity among researchers all over the world. One of its main applications is the simulation of power electronics converters. However, the equipment designed for this purpose is difficult to acquire for some universities or research centers, so ad-hoc solutions for the implementation of HIL simulation in low-cost hardware for power electronics converters is a novel research topic. However, the information regarding implementation is written at a high technical level and in a specific language that is not easy for non-

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Mahmood, Hadeel SH. "FPGA configuration of an alloyed correlated branch predictor used with RISC processor for educational purposes." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 265. http://dx.doi.org/10.11591/ijece.v11i1.pp265-271.

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Instructions pipelining is one of the most outstanding techniques used in improving processor speed; nonetheless, these pipelined stages are constantly facing stalls that caused by nested conditional branches. During the execution of nested conditional branches, the behavior of the running branch depends on the history information of the previous ones; therefore, these branches have the greatest effect in reducing the prediction accuracy of a branch predictor among conditional branches. The purpose of this research is to reduce the stall cycles caused by correlated branches misprediction by in

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Kung, Ying-Shieh, Seng-Chi Chen, Jin-Mu Lin, and Tsung-Chun Tseng. "FPGA-realization of a speed control IC for induction motor drive." Engineering Computations 33, no. 6 (2016): 1835–52. http://dx.doi.org/10.1108/ec-08-2015-0260.

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Purpose – The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator, the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital converter interface circuit, etc. into one field programmable gate array (FPGA). Design/methodology/approach – First, the mathematical modeling of an IM drive, the field-oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware description language (

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Şişik, Fatih, and Eser Sert. "Support Vector Machine working on FPGA and the segmentation method of brain MR screening." International Journal of Innovative Research in Education 4, no. 3 (2017): 120. http://dx.doi.org/10.18844/ijire.v4i3.2549.

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Alan Programlanabilir Kapı Dizileri (Field Programmable Gate Array-FPGA) programlanabilir sayısal bloklar ve bağlantılarını içeren cihazlar olup çok esnek ve hızlı çalışabilme özelliklerine sahiptir. Programlanabilen bu sayısal kapılar sayesinde karmaşık tasarımlar kolay bir şekilde geliştirilebilmektedir. FPGA’lar küçük boyutlarda olup bilgisayardan bağımsız mobil olarak ve bilgisayarlardan daha yüksek hızlarda çalışabilmektedirler. Veri madenciliğinin görevlerinden biri olan sınıflandırma probleminin çözümü için geliştirilmiş önemli makine öğrenimi algoritmalarından biri Destek Vektör Makine

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Pogra, Vivek, Amandeep Singh, Santosh Kumar Vishvakarma, and Balwinder Raj. "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Applications." Sensor Letters 18, no. 9 (2020): 700–705. http://dx.doi.org/10.1166/sl.2020.4239.

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This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modu

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Prashanth, B. U. V., Mohammed Riyaz Ahmed, and Manjunath R. Kounte. "Design and implementation of DA FIR filter for bio-inspired computing architecture." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1709. http://dx.doi.org/10.11591/ijece.v11i2.pp1709-1718.

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This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization a

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Jhang, Jyun-Yu, Kuang-Hui Tang, Chuan-Kuei Huang, Cheng-Jian Lin, and Kuu-Young Young. "FPGA Implementation of a Functional Neuro-Fuzzy Network for Nonlinear System Control." Electronics 7, no. 8 (2018): 145. http://dx.doi.org/10.3390/electronics7080145.

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This study used Xilinx Field Programmable Gate Arrays (FPGAs) to implement a functional neuro-fuzzy network (FNFN) for solving nonlinear control problems. A functional link neural network (FLNN) was used as the consequent part of the proposed FNFN model. This study adopted the linear independent functions and the orthogonal polynomials in a functional expansion of the FLNN. Thus, the design of the FNFN model could improve the control accuracy. The learning algorithm of the FNFN model was divided into structure learning and parameter learning. The entropy measurement was adopted in the structur

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Amer Abbas, Yasir, Razali Jidin, Norziana Jamil, Muhammad Reza Z’aba, and Mohamad Afendee Mohamed. "Photon: a new mix columns architecture on FPGA." International Journal of Engineering & Technology 7, no. 2.14 (2018): 138. http://dx.doi.org/10.14419/ijet.v7i2.14.12814.

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Lightweight cryptography is an important element in smart devices that require data security as one of the features. These smart devices utilize cryptography when transferring sensitive data. Most of the smart devices are resource constrained devices and thus possess limited computing capability and low memory space. The PHOTON hash function algorithm is a promising lightweight cryptography approach for resource-constrained devices. It has a complex operation called MixColumns. This paper presents a new MixColumns architecture for PHOTON implemented on Field Programmable Gate Array (FPGA) devi

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Faleh Hassan, Raaed. "Performance Investigation of Digital Lowpass IIR Filter Based on Different Platforms." International journal of electrical and computer engineering systems 12, no. 2 (2021): 105–11. http://dx.doi.org/10.32985/ijeces.12.2.5.

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The work presented in this paper illuminates the design and simulation of a recursive or Infinite Impulse Response (IIR) filter. The proposed design algorithm employs the Genetic Algorithm to determine the filter coefficients to satisfy the required performance. The effectiveness of different platforms on filter design and performance has been studied in this paper. Three different platforms are considered to implement and verify the designed filter’s work through simulation. The first platform is the MATLAB/SIMULINK software package used to implement the Biquad form filter. This technique is

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Han, Bang Cheng, Dan He, Fang Zheng Guo, Yu Wang, and Bing Nan Huang. "The FPGA-Based Phase-Locked Loop Speed Control System of BLDCM for Magnetically Suspended Control Moment Gyroscope." Applied Mechanics and Materials 80-81 (July 2011): 1249–57. http://dx.doi.org/10.4028/www.scientific.net/amm.80-81.1249.

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A phase-locked loop (PLL) control system based on field programmable gates array (FPGA) is proposed through analyzing the model of three-phase unipolar-driven BLDCM (brushless direct current motor) to enhance the reliability and accurate steady-state speed for magnetically suspended control moment gyroscope (MSCMG). The numerical operation module, PLL module and current-loop control module are designed based on FPGA using very-high-speed integrated circuit hardware description language (VHDL) to realize the control law of the digital system. The pulse width modulation (PWM) generating module f

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H Bailmare, Ravi, S. J. Honale, and Pravin V Kinge. "Design and Implementation of Adaptive FIR filter using Systolic Architecture." International Journal of Reconfigurable and Embedded Systems (IJRES) 3, no. 2 (2014): 54. http://dx.doi.org/10.11591/ijres.v3.i2.pp54-61.

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<p>The tremendous growth of computer and Internet technology wants a data to be process with a high speed and in a powerful manner. In such complex environment, the conventional methods of performing multiplications are not suitable to obtain the perfect solution. To obtain perfect solution parallel computing is use in contradiction. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture

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Vu Quynh, Nguyen. "The Fuzzy PI Controller for PMSM’s Speed to Track the Standard Model." Mathematical Problems in Engineering 2020 (July 13, 2020): 1–20. http://dx.doi.org/10.1155/2020/1698213.

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This paper proposes a fuzzy PI controller to control the speed of a permanent magnet synchronous motor (PMSM). The structure of the system includes the speed loop controller (SLC) and the current loop controller (CLC). The speed loop controller is the fuzzy PI and standard model (SM). The CLC includes vector control and the space vector pulse width modulation (SVPWM). It compiles two closed-loop control systems for the PMSM. This research uses a very high-speed integrated circuit hardware description language (VHDL) to implement the proposed algorithm and embed it into Matlab/Simulink for simu

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Prasad, Hanuman, and Tanmoy Maity. "Modeling and reliability analysis of three phase z-source AC-AC converter." Archives of Electrical Engineering 66, no. 4 (2017): 731–43. http://dx.doi.org/10.1515/aee-2017-0055.

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Abstract This paper presents the small signal modeling using the state space averaging technique and reliability analysis of a three-phase z-source ac-ac converter. By controlling the shoot-through duty ratio, it can operate in buck-boost mode and maintain desired output voltage during voltage sag and surge condition. It has faster dynamic response and higher efficiency as compared to the traditional voltage regulator. Small signal analysis derives different control transfer functions and this leads to design a suitable controller for a closed loop system during supply voltage variation. The c

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Faeq, Mays K., and Safaa S. Omran. "Cache coherency controller for MESI protocol based on FPGA." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1043. http://dx.doi.org/10.11591/ijece.v11i2.pp1043-1052.

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In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultanously for more than one job or all the cores working in parallel for the same job. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So if one core requestes a block of data from main memory to its cache, there should be a protocol to declare the situation of

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Mayer, Kayol Soares, Candice Müller, Fernando Cesar Comparsi de Castro, and Maria Cristina Felippetto de Castro. "A New CPFSK Demodulation Approach for Software Defined Radio." Journal of Circuits, Systems and Computers 28, no. 14 (2019): 1950243. http://dx.doi.org/10.1142/s0218126619502438.

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This paper proposes a new coherent Frequency-Shift Keying (FSK) demodulation technique for software defined radio platform, based on a new Digital Phase Locked Loop (DPLL) architecture. The proposed DPLL addresses the frequency dependence on classic DPLL architectures found in the literature. In classical approaches, the loop filter constants are dependent on the frequency level of the FSK transmitted symbols. The proposed approach applies a simpler feedback loop, with a single integrator and a phase detector architecture based on the small-angle approximation [Formula: see text], which result

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Swarup Kumar, J. N. V. R., and D. Suresh. "Automated Secured Data Delivery for Next Generation Optical Networks." Asian Journal of Computer Science and Technology 7, S1 (2018): 104–7. http://dx.doi.org/10.51983/ajcst-2018.7.s1.1794.

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The present cloud benefit measurements truly are stunning. By one year from now 80% of all new programming will be accessible as a cloud benefit, 58% of all Internet activity is guage to be video in only two years and before the decade’s over, 20 billion brilliant gadgets will be associated with the system. There is no uncertainty this will make difficulties wherever in the system. However, with this test, there regularly comes chance to go into the new optical system; never again is it only an asset for transporting bits. What’s more, it’s more than expanding limit. What’s new is the requirem

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Rudnicki, Kamil, Tomasz P. Stefański, and Wojciech Żebrowski. "Open-Source Coprocessor for Integer Multiple Precision Arithmetic." Electronics 9, no. 7 (2020): 1141. http://dx.doi.org/10.3390/electronics9071141.

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This paper presents an open-source digital circuit of the coprocessor for an integer multiple-precision arithmetic (MPA). The purpose of this coprocessor is to support a central processing unit (CPU) by offloading computations requiring integer precision higher than 32/64 bits. The coprocessor is developed using the very high speed integrated circuit hardware description language (VHDL) as an intellectual property (IP) core. Therefore, it can be implemented within field programmable gate arrays (FPGAs) at various scales, e.g., within a system on chip (SoC), combining CPU cores and FPGA within

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Wei Chun, Quek, Pang Wai Leong, Chan Kah Yoong, Lee It Ee, and Chung Gwo Chin. "HDL Modelling of Low-CostMemory Fault Detection Tester." Journal of Engineering Technology and Applied Physics 2, no. 2 (2020): 17–23. http://dx.doi.org/10.33093/jetap.2020.2.2.3.

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Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE)to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly(at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has in spired us to desi

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Aldair, Ammar. "FPGA Based Modified Fuzzy PID Controller for Pitch Angle of Bench-top Helicopter." Iraqi Journal for Electrical and Electronic Engineering 8, no. 8 (2012): 12–24. http://dx.doi.org/10.37917/ijeee.8.1.2.

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Fuzzy PID controller design is still a complex task due to the involvement of a large number of parameters in defining the fuzzy rule base. To reduce the huge number of fuzzy rules required in the normal design for fuzzy PID controller, the fuzzy PID controller is represented as Proportional-Derivative Fuzzy (PDF) controller and Proportional-Integral Fuzzy (PIF) controller connected in parallel through a summer. The PIF controller design has been simplified by replacing the PIF controller by PDF controller with accumulating output. In this paper, the modified Fuzzy PID controller design for be

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Sciuto, D. "VHDL( VHSIC Hardware Description Language)." Journal of Systems Architecture 42, no. 2 (1996): 95–96. http://dx.doi.org/10.1016/1383-7621(96)00015-x.

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