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Relevant bibliographies by topics / VHDL (VHSIC hardware description language)

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Academic literature on the topic 'VHDL (VHSIC hardware description language)'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

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Journal articles on the topic "VHDL (VHSIC hardware description language)"

1

Sciuto, D. "VHDL( VHSIC Hardware Description Language)." Journal of Systems Architecture 42, no. 2 (September 1996): 95–96. http://dx.doi.org/10.1016/1383-7621(96)00015-x.

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Mahmudi, Ali, Sentot Achmadi, and Michael. "Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes." MATEC Web of Conferences 164 (2018): 01003. http://dx.doi.org/10.1051/matecconf/201816401003.

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In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained.

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Shetty, Mamtha. "Design of BPSK Modulator Using VHDL." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, no. 12 (October 23, 2014): 5247–52. http://dx.doi.org/10.24297/ijct.v13i12.5276.

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Binary Phase Shift Keying represents the simulation results of binary digital modulation schemes. Here for BASK and BPSK modulation techniques use FPGA algorithm. If multiplier block is used for multiplication bit stream with carrier signal, used time will rises. In addition using multiplier block obtained simulation results were analyzed and compared to other simulation results. Source consumptions of FPGA-based BASK modulation technique and BPSK modulation technique were compared. Also, for different modulation algorithm, source consumptions of BASK and BPSK modulation technique were analyzed using VHDL. Designed modulators using VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL) was realized on high speed FPGA (Field Program Programmable Gate Array). Because for used modulation technique data rate transfer is fairly important in wireless communication systems. The highest speed data rate transfer can be realized using fiber optic cables. In addition, BER (Bit Error Rate) of BASK and BPSK modulator was compared using MATLAB simulation program. Binary data rate is same for BPSK and BASK. BPSK and BASK modulations were designed on FPGA using VHDL hardware description language.

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Ameur, Noura Ben, Nouri Masmoudi, and Mourad Loulou. "FPGA-Based Design Δ–Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit." Journal of Circuits, Systems and Computers 24, no. 03 (February 10, 2015): 1550037. http://dx.doi.org/10.1142/s0218126615500371.

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This paper, focus on synthesis design of a Δ–Σ digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio DAC. The features of the design are high-precision, fast processing and low-cost. The related work is done with the MATLAB & QUARTUS II simulators.

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Cesar, da Costa, and Oliveira Santin Christian. "Design and simulation of direct torque control of induction motors using VHSIC Hardware Description Language (VHDL)." Scientific Research and Essays 12, no. 11 (June 15, 2017): 103–12. http://dx.doi.org/10.5897/sre2017.6501.

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Montiel-Ross, Oscar, Jorge Quiñones, and Roberto Sepúlveda. "Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors." Advances in Fuzzy Systems 2012 (2012): 1–11. http://dx.doi.org/10.1155/2012/475894.

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This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor.

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Chou, Hsin-Hung, Ying-Shieh Kung, Tai-Wei Tsui, and Stone Cheng. "FPGA-BASED MOTION CONTROLLER FOR WAFER-HANDLING ROBOT." Transactions of the Canadian Society for Mechanical Engineering 37, no. 3 (September 2013): 427–37. http://dx.doi.org/10.1139/tcsme-2013-0032.

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This study applies FPGA (Field Programmable Gate Arrays) technology to implement a motion controller for wafer-handling robot which has three-DOF (Degree of Freedom) motion. The proposed FPGA-based motion controller has two modules. The first module is Nios II processor which is used to realize the motion trajectory computation and the three-axis position/speed controllers. The second module is demonstrated to implement the three-axis current vector controllers by using FPGA hardware, and VHDL (VHSIC Hardware Description Language) is adopted to describe the controller behavior. Therefore, a fully digital motion controller for wafer-handling robot, such as one trajectory planning, three current vector controllers and three position/speed controllers are all implemented with an FPGA chip.

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SHARMA, SUBHASH KUMAR, SHRI PRAKASH DUBEY, and ANIL KUMAR MISHRA. "Development of Library Components for Floating Point Processor." Journal of Ultra Scientist of Physical Sciences Section A 33, no. 4 (June 15, 2021): 42–50. http://dx.doi.org/10.22147/jusps-a/330402.

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This paper deals with development of an n-bit binary to decimal conversion, decimal to n bit binary conversion and decimal to IEEE-754 conversion for floating point arithmetic logic unit (FPALU) using VHDL. Normally most of the industries now a days are using either 4-bit conversion of ALU or 8-bit conversions of ALU, so we have generalized this, thus we need not to worry about the bit size of conversion of ALU. It has solved all the problems of 4-bit, 8-bit, 16-bit conversions of ALU’s and so on. Hence, we have utilized VHSIC Hardware Description Language and Xilinx in accomplishing this task of development of conversions processes of ALU

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Rampa, Vittorio. "Design and Implementation of a Low Complexity Multiuser Detector for Hybrid CDMA Systems." Journal of Communications Software and Systems 1, no. 1 (April 6, 2017): 42. http://dx.doi.org/10.24138/jcomss.v1i1.316.

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In hybrid CDMA systems, multiuser detection (MUD) algorithms are adopted at the base station to reduce both multiple access and inter-symbol interference by exploitingspace-time (ST) signal processing techniques. Linear ST-MUD algorithms solve a linear problem where the system matrix has a block-Toeplitz shape. While exact inversion techniques impose an intolerable computational load, reduced complexity algorithms may be efficiently employed even if they show suboptimal behavior introducing performance degradation and nearfar effects. The block-Fourier MUD algorithm is generally considered the most effective one. However, the block-Bareiss MUD algorithm, that has been recently reintroduced, shows also good performance and low computational complexity comparingfavorably with the block-Fourier one. In this paper, both MUD algorithms will be compared, along with other well known ones, in terms of complexity, performance figures, hardware feasibility and implementation issues. Finally a short hardware description of the block-Bareiss and block-Fourier algorithms will be presented along with the FPGA (Field Programmable Gate Array) implementation of the block-Fourier using standard VHDL (VHSIC Hardware Description Language) design.

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Kung, Ying-Shieh, Jin-Mu Lin, Yu-Jen Chen, and Hsin-Hung Chou. "ModelSim/Simulink Cosimulation and FPGA Realization of a Multiaxis Motion Controller." Mathematical Problems in Engineering 2015 (2015): 1–17. http://dx.doi.org/10.1155/2015/202474.

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This paper is to implement a multiaxis servo controller and a motion trajectory planning within one chip. At first, SoPC (system on a programmable chip) technology which is composed of an Altera FPGA (field programmable gate arrays) chip and an embedded soft-core Nios II processor is taken as the development of a multiaxis motion control IC. The multiaxis motion control IC has two modules. The first module is Nios II processor which realizes the motion trajectory planning by software. It includes the step, circular, window, star, and helical motion trajectory. The second module presents a function of the multiaxis position/speed/current controller IP (intellectual property) by hardware. And VHDL (VHSIC Hardware Description Language) is applied to describe the multiaxis servo controller behavior. Before the FPGA realization, a cosimulation work by ModelSim/Simulink is applied to test the VHDL code. Then, this IP combined by Nios II processor will be downloaded to FPGA. Therefore, a fully digital multiaxis motion controller can be realized by a single FPGA chip. Finally, to verify the effectiveness and correctness of the proposed multiaxis motion control IP, a three-axis motion platform (XYZtable) is constructed and some experimental results are presented.

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Dissertations / Theses on the topic "VHDL (VHSIC hardware description language)"

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Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

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Read, Simon. "Formal methods for VLSI design." Thesis, University of Manchester, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239786.

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Shah, Sandeep R. "A framework for synthesis from VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-03022010-020143/.

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Wright, Philip A. "Rapid development of VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-11102009-020056/.

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Dailey, David M. "Integration of VHDL simulation and test verification into a Process Model Graph design environment." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-11242009-020247/.

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Sama, Anil. "Behavior modeling of RF systems with VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-10102009-020211/.

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Van, Tassel John Peter. "Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistant." Thesis, University of Cambridge, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.308190.

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Ardeishar, Raghu. "Automatic verification of VHDL models." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/.

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Rao, Sanat R. "A hierarchical approach to effective test generation for VHDL behavioral models." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-08042009-040513/.

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Manek, Meenakshi. "Natural language interface to a VHDL modeling tool." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-06232009-063212/.

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Books on the topic "VHDL (VHSIC hardware description language)"

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Computer Systems Laboratory (U.S.), ed. VHSIC hardware description language (VHDL). Gaithersburg, MD: U.S. Dept. of Commerce, Technology Administration, National Institute of Standards and Technology, Computer Systems Laboratory, 1995.

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A VHDL primer. Englewood Cliffs, NJ: Prentice Hall, 1992.

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A VHDL primer. 3rd ed. Upper Saddle River, N.J: Prentice Hall PTR, 1999.

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A VHDL primer. Englewood Cliffs, N.J: Prentice Hall PTR, 1995.

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Pellerin, David. VHDL made easy! Upper Saddle River, N.J: Prentice Hall, 1997.

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6

1945-, Schaefer Carl F., and Ussery Cary 1962-, eds. VHDL, hardware description and design. Boston: Kluwer Academic Publishers, 1989.

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1945-, Langstraat Patricia, ed. A guide to VHDL. Boston: Kluwer Academic Publishers, 1992.

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1945-, Langstraat Patricia, ed. A guide to VHDL. 2nd ed. Boston: Kluwer Academic Publishers, 1993.

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IEEE Computer Society. Design Automation Standards Subcommittee. IEEE standard VHDL language reference manual. New York: Institute of Electrical and Electronics Engineers, 2009.

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Coelho, David R. The VHDL handbook. Boston: Kluwer Academic Publishers, 1989.

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Book chapters on the topic "VHDL (VHSIC hardware description language)"

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Pierre, Laurence. "VHDL: A Hardware Description Language and its Simulation Semantics." In Software Specification Methods, 113–30. London: Springer London, 2001. http://dx.doi.org/10.1007/978-1-4471-0701-9_7.

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Navabi, Zainalabedin, and Naghmeh Karimi. "VHDL-AMS Hardware Description Language." In The VLSI Handbook, Second Edition, 91–1. CRC Press, 2006. http://dx.doi.org/10.1201/9781420005967.ch91.

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Oczko, Andreas, and Christel Oczko. "Putting Different Simulation Models Together – The Simulation Configuration Language VHDL/S." In Computer Hardware Description Languages and their Applications, 115–29. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-444-89208-9.50011-9.

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El Oualkadi, Ahmed. "S-? Fractional-N Phase-Locked Loop Design Using HDL and Transistor-Level Models for Wireless Communications." In Advances in Wireless Technologies and Telecommunication, 99–118. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-4666-0083-6.ch005.

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This chapter presents a systematic design of a S-? fractional-N Phase-Locked Loop based on hardware description language behavioral modeling. The proposed design consists of describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The description language models of critical PLL blocks have been described in VHDL-AMS, which is an IEEE standard, to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the overall system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models in the frequency range around 2.45 GHz for wireless applications.

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Yahya, Abid, Farid Ghani, R. Badlishah Ahmad, Mostafijur Rahman, Aini Syuhada, Othman Sidek, and M. F. M. Salleh. "Development of an Efficient and Secure Mobile Communication System with New Future Directions." In Handbook of Research on Computational Science and Engineering, 219–38. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-61350-116-0.ch010.

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This chapter presents performance of a new technique for constructing Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) encrypted codes based on a row division method. The new QC-LDPC encrypted codes are flexible in terms of large girth, multiple code rates, and large block lengths. In the proposed algorithm, the restructuring of the interconnections is developed by splitting the rows into subrows. This row division reduces the load on the processing node and ultimately reduces the hardware complexity. In this method of encrypted code construction, rows are used to form a distance graph. They are then transformed to a parity-check matrix in order to acquire the desired girth. In this work, matrices are divided into small sub-matrices, which result in improved decoding performance and reduce waiting time of the messages to be updated. Matrix sub-division increases the number of sub-matrices to be managed and memory requirement. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip.

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Conference papers on the topic "VHDL (VHSIC hardware description language)"

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Gray, F., and James Armstrong. "Reutilization of VHDL testbench and library components (VHSIC Hardware Description Language)." In 10th Computing in Aerospace Conference. Reston, Virigina: American Institute of Aeronautics and Astronautics, 1995. http://dx.doi.org/10.2514/6.1995-1035.

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Yuguo, Sun, and Chen Jin. "Embedded Fault Tree Logic Implementation Based on Complex Programmable Logic Device." In ASME 2005 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/detc2005-84886.

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To meet the requirements of an embedded mechanical fault diagnosis system development, a fault tree implementation and dynamic modification method based on CPLD (Complex Programmable Logic Device) is investigated experimentally. The mechanism of fault tree logic calculation in the CPLD chip is presented. The fault logic tree is modeled by VHDL (VHSIC Hardware Description Language) and logic graphic, respectively. The effects of the bottom events on the logic result are simulated in Max + plus II platform. The fault tree logic is downloaded into the EPM7064SLC44-10 chip by ISP (In System Programmable) technology. And evaluated in terms of power consumption, system’s volume and design flexibility. The study results show that CPLD is suit to the fault tree’s construction, contributed by the chip’s outstanding ISP function and programmable logic function. And the fault tree logic synthesis and the chip resource optimization need to be further investigated.

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Waxman, R., J. H. Aylor, and E. Marschner. "The VHSIC hardware description language (IEEE standard 1076): language features revisited." In COMPCON Spring 88. IEEE, 1988. http://dx.doi.org/10.1109/cmpcon.1988.4880.

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Binns, R. J. "High-level design of analogue circuitry using an analogue hardware description language." In IEE Colloquium on Mixed-Signal AHDL/VHDL Modelling and Synthesis. IEE, 1997. http://dx.doi.org/10.1049/ic:19971118.

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Wenzl, Matthias, Peter Roessler, and Andreas Puhm. "Checking Application Level Properties Using Assertion Synthesis." In ASME 2019 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/detc2019-97950.

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Abstract This work presents a proof-of-concept of a new approach on automatic generation of digital hardware that is able to check application-level properties of an embedded system such as a faulty system behavior at runtime. The approach makes use of assertion-based verification setups that today are very common in the area of digital hardware design with, however, the sole focus on logic simulation. Thus, a PSL-to-VHDL compiler is introduced that generates VHDL (Very High Speed Integrated Circuit Description Language) code out of PSL (Property Specification Language) assertions which can be further processed by a traditional digital logic synthesis tool. That way, runtime checker units can be automatically generated with little effort because of the already existing assertion-based test benches. Furthermore, a model railway demonstrator is presented herein as an example for a safety-critical application to prove the proposed tool flow on a use case. Implementation results based on that use case are discussed. Finally, the paper concludes with a brief outlook on related future work of the authors.

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Reports on the topic "VHDL (VHSIC hardware description language)"

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Aylor, James, Robert Klenke, Ron Waxman, Paul Menchini, Jack Stinson, and Bill Anderson. VHSIC Hardware Description Language (VHDL) 200X Requirements Report/Survey. Fort Belvoir, VA: Defense Technical Information Center, November 1999. http://dx.doi.org/10.21236/ada406178.

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Chung, Moon Jung. Parallel Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) Simulation for Performance Modeling. Fort Belvoir, VA: Defense Technical Information Center, March 1999. http://dx.doi.org/10.21236/ada372678.

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Mills, Michael T. Proposed Object Oriented Programming (OOP) Enhancements to the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). Fort Belvoir, VA: Defense Technical Information Center, August 1993. http://dx.doi.org/10.21236/ada274004.

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Mills, Michael T. A Key Element Toward Concurrent Engineering of Hardware and Software: Binding Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) with Ada 95. Fort Belvoir, VA: Defense Technical Information Center, October 1994. http://dx.doi.org/10.21236/ada294469.

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Federal Information Processing Standards Publication: VHSIC hardware description language (VHDL). Gaithersburg, MD: National Institute of Standards and Technology, 1995. http://dx.doi.org/10.6028/nist.fips.172-1-1995.

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