Dissertations / Theses on the topic 'VHDL (VHSIC hardware description language)'
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Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.
Full textRead, Simon. "Formal methods for VLSI design." Thesis, University of Manchester, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239786.
Full textShah, Sandeep R. "A framework for synthesis from VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-03022010-020143/.
Full textWright, Philip A. "Rapid development of VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-11102009-020056/.
Full textDailey, David M. "Integration of VHDL simulation and test verification into a Process Model Graph design environment." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-11242009-020247/.
Full textSama, Anil. "Behavior modeling of RF systems with VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-10102009-020211/.
Full textVan, Tassel John Peter. "Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistant." Thesis, University of Cambridge, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.308190.
Full textArdeishar, Raghu. "Automatic verification of VHDL models." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/.
Full textRao, Sanat R. "A hierarchical approach to effective test generation for VHDL behavioral models." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-08042009-040513/.
Full textManek, Meenakshi. "Natural language interface to a VHDL modeling tool." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-06232009-063212/.
Full textHoncharik, Alexander J. "Generation of VHDL from conceptual graphs of informal specifications." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-06162009-063028/.
Full textSprunger, Steven J. "UML modeling for VHDL designs." Virtual Press, 2008. http://liblink.bsu.edu/uhtbin/catkey/1399192.
Full textDepartment of Computer Science
Edwards, Carleen Marie. "Representation and simulation of a high level language using VHDL." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-11242009-020306/.
Full textShrivastava, Vikram M. "Mapping conceptual graphs to primitive VHDL processes." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-05022009-040536/.
Full textBarton, Jonathan L. "Hardware implementation of a synchronization state buffer in VHDL." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 67 p, 2008. http://proquest.umi.com/pqdweb?did=1459924801&sid=13&Fmt=2&clientId=8331&RQT=309&VName=PQD.
Full textMacklin, Kendrick R. "Suitability of the SRC-6E reconfigurable computing system for generating false radar image." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2004. http://library.nps.navy.mil/uhtbin/hyperion/04Jun%5FMacklin.pdf.
Full textPan, Bi-Yu. "Hierarchical test generation for VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-09052009-040449/.
Full textGiannopoulos, Vassilis. "Efficient VHDL models for various PLD architectures /." Online version of thesis, 1995. http://hdl.handle.net/1850/12238.
Full textGadagkar, Ashish. "Timing distribution in VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10102009-020318/.
Full textGoeke, James A. "Design of a hardware efficient key generation algorithm with a VHDL implementation /." Online version of thesis, 1993. http://hdl.handle.net/1850/11664.
Full textCosta, Richard Maciel. "Metodologia e projeto de ferramenta para co-simulação entre VHDL e SystemC." [s.n.], 2008. http://repositorio.unicamp.br/jspui/handle/REPOSIP/276135.
Full textDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação
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Resumo: Em um passado recente os sistemas eram constituídos de partes discretas tais como microprocessadores, memórias e Application Specific Integrated Circuits (ASICs). Essa separação clara e simples tornava possível a especificação ser feita por uns poucos projetistas utilizando uma abordagem top-down: a partir de um modelo comportamental ou Register-Transfer Level (descritos em VHDL, por exemplo), progressivamente refinando o modelo ate o nível Transistor-to-Transistor. Entretanto, o avanço contínuo do processo de miniaturização de transistores possibilitou a criação de sistemas completos integrados em um único chip (também chamados de System-on-chip). Dado que esses sistemas s~ao tipicamente constituídos por diversos componentes complexos, um nível mais alto de abstração - o de sistema - foi criado, juntamente com suas linguagens associadas (como a linguagem SystemC), para facilitar o trabalho dos projetistas. As linguagens utilizadas para modelar no nível de sistema são diferentes das linguagens utilizadas para modelar nos níveis comportamental e Register-Transfer. Assim, surge o problema de como co-verificar componentes descritos em diferentes níveis de abstração; característica desejável para projetos de grande porte, já que fornece uma garantia de interoperabilidade entre os componentes no sistema final. Este trabalho, então, apresenta uma metodologia para resolver o problema de co-simulação entre a linguagem de descrição de hardware VHDL e a linguagem de descrição de sistema SystemC através do uso da Verilog Procedural Interface (VPI). Alem da metodologia em si, descreve-se o trabalho no sentido de criar um arcabouço para validar a metodologia e testes comparativos entre a implementação feita e uma ferramenta comercial popular.
Abstract: In a recent past, systems were mostly constituted by well-separated parts such as microprocessors, memories and Application Specific Integrated Circuits (ASICs). That simple and clear organization allowed entire systems to be designed by only a few designers through a top-down approach: from the behavioral or register transfer model (using VHDL, for instance) advancing to the transistor-to-transistor level. However, the continuous advance of the process of shrinking transistors made it possible to create entire systems integrated in a single die (called System-on-chip). Because these systems are usually constituted by many complex components, a higher abstraction level - the system level - was created, together with the associated languages, to ease the work of the designers. The languages used to model on the system level are diferent from the languages used to model on the behavioral and register-transfer levels. Therefore, the problem of how to co-verify components written in diferent abstraction levels arises; this co-verification is desirable for big projects, since it provides a way to check if the components of the target system are working together. This project presents a methodology to solve the co-simulation problem between the hardware description language VHDL and the system description languagem SystemC through the use of the Verilog Procedural Interface (VPI). We describe the methodology and also describe the framework used to validate the methodology and comparative tests between this framework and a well-known comercial tool.
Mestrado
Arquitetura de Computadores
Mestre em Ciência da Computação
Palanisamy, Karthikeyan. "High Level Preprocessor of a VHDL-based Design System." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4776.
Full textChadha, Vikrampal. "Simulation of large-scale system-level models." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12162009-020334/.
Full textChu, Ming-Cheung. "Hazard detection with VHDL in combinational logic circuits with fixed delays." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10062009-020040/.
Full textWilhelm, Kyle. "Aspects of hardware methodologies for the NTRU public-key cryptosystem /." Online version of thesis, 2008. http://hdl.handle.net/1850/7774.
Full textMoustakas, Evangelos. "Design and simulation of a primitive RISC architecture using VHDL /." Online version of thesis, 1991. http://hdl.handle.net/1850/11229.
Full textFrandina, Peter. "VHDL modeling and synthesis of the JPEG-XR inverse transform /." Online version of thesis, 2009. http://hdl.handle.net/1850/10755.
Full textSingh, Balraj. "A parametrized CAD tool for VHDL model development with X Windows." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03242009-040819/.
Full textImvidhaya, Ming. "VHDL simulation of the implementation of a costfunction circuit." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA240430.
Full textThesis Advisor(s): Lee, Chin-Hwa. Second Reader: Butler, Jon T. "September 1990." Description based on title screen as viewed on December 29, 2009. DTIC Identifier(s): Computerized simulation, computer aided design, logic circuits, subroutines, theses, integrated circuits. Author(s) subject terms: VHDL, costfunction, hardware description language. Includes bibliographical references (p. 77). Also available in print.
Kapoor, Shekhar. "Process level test generation for VHDL behavioral models." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-05022009-040753/.
Full textMacklin, Kendrick R. "Benchmarking and analysis of the SRC-6E reconfigurable computing system." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Dec%5FMacklin.pdf.
Full textFanelli, Paul. "VHDL modeling and design of an asynchronous version of the MIPS R3000 microprocessor /." Online version of thesis, 1994. http://hdl.handle.net/1850/11157.
Full textChen, Wei-chun. "Simulation of a morphological image processor using VHDL. mathematical components /." Online version of thesis, 1993. http://hdl.handle.net/1850/11872.
Full textChen, Hao. "Simulation of a morphological image processor using VHDL. control mechanism /." Online version of thesis, 1993. http://hdl.handle.net/1850/11744.
Full textNarayanaswamy, Sathyanarayanan. "Development of VHDL behavioral models with back annotated timing." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06112009-063442/.
Full textGuthrie, Thomas G. "Design, implementation, and testing of a software interface between the AN/SPS-65(V)1 radar and the SRC-6E reconfigurable computer." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2005. http://library.nps.navy.mil/uhtbin/hyperion/05Mar%5FGuthrie.pdf.
Full textPhillips, Walter. "VHDL design of computer vision tasks." Honors in the Major Thesis, University of Central Florida, 2001. http://digital.library.ucf.edu/cdm/ref/collection/ETH/id/240.
Full textBachelors
Engineering
Computer Science
Hoffman, Joseph A. "VHDL modeling of ASIC power dissipation." Master's thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10222009-124831/.
Full textOliveira, Alexandre Tomazati. "Detecção do complexo QRS em sinais cardiacos utilizando FPGA." [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/264060.
Full textDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecanica
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Resumo: O eletrocardiograma (ECG) é uma ferramenta utilizada para o diagnóstico de cardiopatias e outras doenças. Este trabalho tem como objetivo a detecção do complexo QRS, com foco na onda R, que representa a contração dos ventrículos. Para isso, são apresentadas duas técnicas de processamento do sinal de ECG. A primeira utiliza o algoritmo proposto por Pan & Tompkins que consiste em um banco de filtros digitais. A segunda faz uso da transformada wavelet discreta, que permite a localização de características de sinais tanto no tempo quanto na frequência. É apresentado um comparativo da eficácia dos dois algoritmos com base na sua implementação através de FPGA, utilizando dois métodos, o processamento serial em microcontrolador programado em C e o paralelo inteiramente em VHDL, com o intuito de comparar os tempos de processamento. Os resultados sugerem que trabalhos futuros poderão ser baseados na investigação de outras famílias wavelets para a detecção do complexo QRS em sinais de ECG, bem como explorar outros métodos de implementação de filtros em FPGA.
Abstract: The electrocardiogram (ECG) is a tool used for diagnosis of diseases related to the heart. This work has the purpose of detecting QRS complex, focusing on the R wave, which represents the ventricles'contraction. It is presented two techniques of processing ECG signals. The first uses Pan & Tompkins algorithm based on digital filtering. The second uses the discrete wavelet transform, which represents the characteristics of the signal simultaneously in time and frequency. It is presented a comparison of the efficacy of both algorithms, which are implemented in FPGA, using serial processing based on a C programmed microcontroller, and parallel processing entirely in VHDL, with the purpose of comparing the time of processing. The results suggest that future work can be based on the investigation of other wavelets family for detecting QRS complex in ECG signals and other methods of implementing filters in FPGA.
Mestrado
Mecanica dos Sólidos e Projeto Mecanico
Mestre em Engenharia Mecânica
Kantemir, Ozkan. "VHDL modeling and simulation of a digital image synthesizer for countering ISAR." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Jun%5FKantemir.pdf.
Full textThesis advisor(s): Douglas J. Fouts, Phillip E. Pace. Includes bibliographical references (p. 143-144). Also available online.
Raizer, Klaus 1982. "Análise de sinais de ECG com o uso de wavelets e redes neurais em FPGA." [s.n.], 2010. http://repositorio.unicamp.br/jspui/handle/REPOSIP/264098.
Full textDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecânica
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Resumo: Este trabalho apresenta a implementação de um sistema de análise de sinais de ECGs (eletrocardiogramas) embarcado em FPGA (field programmable gate array), capaz de classificar cardiopatias. A análise de ECGs é de grande importância devido a sua natureza potencialmente não-invasiva, baixo custo e alta eficiência na identificação de patologias cardíacas. Visto que um sinal de ECG pode ser composto por horas de gravação da atividade cardíaca, uma abordagem computacional para a sua análise torna-se um instrumento valioso para a redução do tempo e dos erros de diagnóstico. No presente trabalho uma série de características são extraídas dos pulsos de ECG, que foram obtidos a partir dos sinais do banco de dados MIT-BIH, através da decomposição por transformada wavelet discreta. Essas características foram então utilizadas para treinar uma Rede Neural do tipo feedforward para discernir pulsos normais de pulsos anômalos. Uma versão da rede neural foi então programada em VHDL e em seguida implementada em um Kit da Xilinx modelo Spartan 3E para a classificação pulso a pulso dos sinais de ECG. As implicações dessa arquitetura são discutidas e os resultados são apresentados
Abstract: this work presents an implementation of an embedded ECG (electrocardiogram) signal analysis system using FPGA (field programmable gate array), capable of classifying cardiopathies. The importance of ECG analysis is mainly due to its potentially non-invasive nature, low cost and high efficiency to identify heart pathologies. Since a single ECG signal can be the record of hours of heart activity, a computational approach to its analysis is invaluable to reduce diagnostic errors and the time taken by the process. In the present work, features are extracted from ECG pulses, obtained from the MIT-BIH database, by decomposing them with the Discrete Wavelet Transform. These features are then used to train a Backpropagation Neural Network in order to discriminate normal ECG pulses from anomalous ones. The neural network is programmed in VHDL and uploaded into a Spartan 3E Xilinx development kit, which performs a pulse-by-pulse classification. The implications of such architecture are discussed and its results are presented
Mestrado
Mecanica dos Sólidos e Projeto Mecanico
Mestre em Engenharia Mecânica
Hudson, Rhett Daniel. "The use of VHDL in computer-aided support of life-cycle complete product design." Thesis, Virginia Tech, 1994. http://hdl.handle.net/10919/42143.
Full textA product must be engineered in a manner that addresses all pertinent issues over its
complete life cycle. This research examines the use of the VHSIC Hardware Description
Language as a computer-aided engineering tool for life-cycle complete engineering.
VHDL is traditionally used to model the functional behavior of digital systems. This thesis
provides an overview of a life-cycle complete design process and describes the use of
VHDL to support that process. A case study is presented to illustrate the use of VHDL
for life-cycle complete modeling.
Master of Science
Antiqueira, Perci Ayres. "Implementação de modelos de redes de Petri em hardware de lógica reconfigurável." Universidade Tecnológica Federal do Paraná, 2011. http://repositorio.utfpr.edu.br/jspui/handle/1/204.
Full textIn this research work, was performed a study of main types of hardware modeling tools searching to verify the advantages of utilizing for modeling dynamic and concurrent systems and for its hardware implementation. It was observed that even though there are tools for this purpose, exists some points that may be worked out to facilitate access to this technology. So, was developed a method for facilitate implementation of systems modeled in Petri nets, in reconfigurable logic hardware. For that, was utilized a capture software where, from the graphic of the Petri net model, is generated a description in PNML (Petri Net Markup Language) format. From this description, is generated a hardware description file in VHDL (VHSIC Hardware Description Language) format, that may be loaded in a reconfigurable logic circuit. To make possible this stage, was performed the development of tool that generate a file in VHDL language from the description in PNML format. The developed tool is described in details, showing all stages and criteria utilized in the conversion. To validate the method, is showed an application example for this toll with the implementation in FPGA (Field Programmable Gate Arrow), of a Petri net modeling a hypothetic industrial plant. Finally, a performance comparison is made between the model executed in hardware and the model executed in software.
Joshi, Anand Mukund. "Behavioral delay fault modeling and test generation." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-07292009-090436/.
Full textGuardia, Filho Luiz Eduardo. "Sistema para controle de maquinas robotizadas utilizando dispositivos logicos programaveis." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259017.
Full textDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Este trabalho de mestrado teve o propósito de projetar e construir um sistema de hard-ware capaz de realizar o controle de máquinas robotizadas em tempo real. Foi dada uma abordagem usando técnicas de processamento paralelo e eletrônica reconfigurável com o uso de dispositivos lógicos programáveis. Mostrou-se em função dos resultados das implementações que o sistema proposto é eficiente para ser utilizado no controle de robôs baseado em modelos matemáticos complexos como cinemático direto/inverso, dinâmico e de visão artificial. Esse mesmo sistema prevê sua utilização para os quatro níveis hierárquicos envolvidos em plantas que se utilizam de controle automático: supervisão, tarefas, trajetória e servomecanismos. O sistema possui interfaces de comunicação USE e RS-232, conversores A/D e D/A, sistema de processamento de imagens (entradas e saídas de sinais de vídeo analógico), portas E/S, chaves e leds para propósito geral. A eficiência foi comprovada através de experimentações práticas utilizando sistemas robóticos reais como: sistema de um pêndulo acionado, robô redundante de 4GDL denominado Cobra, e solução em hardware de funções importantes no sentido da resolução dos modelos matemáticos em tempo real como funções transcendentais
Abstract: This work had as purpose the project and build of a hardware system with abilities to accomplish the real time control of robotic machines. It was given an approach using tech-niques of parallel processing and programmable electronics configuration with programmable logic devices. According to the implementation results, it was shown that this proposed sys-tem is efficient to be used for controlling robots based on complex mathematical models, like direct/inverse kinematics, dynamics and artificial vision. This system foresees its use for the four hierarchical levels involved in industrial plants that use automatic control: supervision, tasks, trajectory /path and servomechanisms. The system has USE and RS-232 communica-tion interfaces, A/D and D/A converters, image processing capabilities (with input/output for analog video signals), I/O ports, and switches and leds for general purpose. Its efficiency is demonstrated through practical experimentations using real robotic systems as: a driven pendu-lum system, a redundant 4 DOF robot called "Cobra", and a hardware solution for important functions in the sense of real time mathematical models computing, like the transcendental functions
Mestrado
Automação
Mestre em Engenharia Elétrica
Horsburgh, Ian J. "The development of a mass memory unit for a micro-satellite using NAND flash memory." Thesis, Stellenbosch : Stellenbosch University, 2005. http://hdl.handle.net/10019.1/50474.
Full textENGLISH ABSTRACT: This thesis investigates the possible use of NAND flash memory for a mass memory unit on a micro-satellite. The investigation begins with an analysis of NAND flash memory devices including the complexity of the internal circuitry and the occurrence of bad memory sections (bad blocks). Design specifications are produced and various design architectures are discussed and evaluated. Subsequently, a four bus serial access architecture using 16- bit NAND flash devices was chosen to be developed further. A VHDL design was created in order to realise the intended system functionality. The main functions of the design include a sustained write data rate of 24 MB/s, bad block management, multiple image storing, error checking and correction, defective device handling and reading while writing. The design was simulated extensively using NAND flash simulation models. Finally, a demonstration test board was designed and produced. This board includes an FPGA and an array of 16 8-bit NAND flash devices. The board was tested sucessfully and a write data rate of 12 MB/s was achieved along with all the other main functions.
AFRIKAANSE OPSOMMING: Hierdie tesis ondersoek die moontlike gebruik van NAND flash tegnologie as die geheue eenheid van ’n mikrosatelliet. As ’n beginpunt word NAND flash tegnologie ondersoek in terme van die kompleksiteit van interne stroombane en die voorkoms van defektiewe geheuesegmente. Daarna word ontwerpspesifikasies voortgebring en verskillende ontwerpsmoontlikhede met mekaar vergelyk. Vanuit hierdie oorwegings is daar besluit om die oplossing te implementeer met ’n vier-bus seri¨ele struktuur bestaande uit 16-bis NAND flash toestelle. Om die ontwerpspesifikasies te realiseer, is ’n VHDL stelsel geskep. Die belangrikste funksies van hierdie stelsel is ’n konstante skryftempo van 24 MB/s, die bestuur van defektiewe geheuesegmente, die stoor van meer as een beeld, foutopsporing en -herstel, optimale werking in die geval van defektiewe geheuetoestelle en laastens, die gelyktydige lees en skryf van data. Die stelsel is breedvoerig getoets met NAND flash simulasiemodelle. Ten slotte is ’n fisiese demonstrasiebord, bestaande uit ’n FPGA en 16 8-bis NAND flash toestelle, ontwerp en gebou. Fisiese metings was ’n sukses. ’n Skryftempo van 12 MB/s is gehaal, tesame met die korrekte werking van die ander hooffunksies.
Souza, Fabiano Alves de [UNESP]. "Detecção de faltas em sistemas de distribuição de energia elétrica usando dispositivos programáveis." Universidade Estadual Paulista (UNESP), 2008. http://hdl.handle.net/11449/87044.
Full textCoordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
Atualmente as empresas do setor elétrico deparam–se cada vez mais com as exigências do mercado energético sendo obrigadas a assegurarem aos seus clientes bons níveis de continuidade e confiabilidade no serviço de fornecimento da energia elétrica e também atender os índices de continuidade do serviço estabelecidos pela agência reguladora do setor elétrico (ANEEL – Agência Nacional de Energia Elétrica). Para alcançar estes objetivos além de investir na otimização dos seus sistemas de transmissão e distribuição, as empresas responsáveis têm investido na automação de suas operações, buscando alternativas que reduzam os tempos de interrupção por faltas permanentes nos sistemas de potência. Através de informações disponíveis em uma subestação, é possível estabelecer um procedimento para determinar e classificar condições de faltas, localizando o elemento de proteção acionado, e assim fornecer o apoio à tomada de decisão no ambiente de subestações de sistemas de distribuição de energia elétrica. Neste trabalho é proposta uma metodologia que fornece respostas rápidas (controle on line), para detecção e classificação de faltas em sistemas de distribuição de energia elétrica através de informações analógicas disponíveis em uma subestação, tais como amostras de sinais de tensões e correntes na saída dos alimentadores, com uma arquitetura reconfigurável paralela que usa dispositivos lógicos programáveis (Programables Logics Devices – PLDs) -FPGAs e a linguagem de descrição de hardware – VDHL (Very High Speed Integraded Circuit – VHSIC). Para validar o sistema proposto, foram gerados dados de forma aleatória, compatíveis com informações fornecidas em tempo real pelo sistema SCADA (supervisory control and data-acquisition) de uma subestação real. Os resultados obtidos com as simulações realizadas, mostram que a...
Currently companies of the energy industry is facing increasingly with the requirements of the energy market are obliged to ensure their customers good levels of continuity in service and reliability of supply of electric energy and also meet the rates of continuity of service established by the agency regulator of the energy industry (ANEEL - National Electric Energy Agency). To achieve these goals than to invest in optimization of its transmission and distribution systems, the companies responsible have invested in automation of its operations, seeking alternatives that reduce the time of interruption by failures in the systems of permanent power. Through information available in a substation, it is possible to establish a procedure for identifying and classifying conditions of absence, finding the element of protection driven, and thus provide support for decision-making within the environment of substations to distribution systems for power. This work is proposed a methodology that provides quick answers (control online), for detection and classification of faults in distribution systems of electric energy through analog information available on a substation, such as samples for signs of tensions and currents in the output of feeders, with an architecture that uses parallel reconfigurable programmable logic devices (Programables Logics Devices - PLDs)-FPGAs and the language of description of hardware - VDHL (Very High Speed Circuit Integraded - VHSIC). To validate the proposed system, data were generated at random, consistent with information provided by the system in real time SCADA (supervisory control and data-acquisition) of a real substation. The results obtained with the simulations conducted, show that the proposed methodology, presents satisfactory results, and times of reasonable answers.
Souza, Fabiano Alves de. "Detecção de faltas em sistemas de distribuição de energia elétrica usando dispositivos programáveis /." Ilha Solteira : [s.n.], 2008. http://hdl.handle.net/11449/87044.
Full textBanca: Nobuo Oki
Banca: Luis Gustavo Wesz da Silva
Resumo: Atualmente as empresas do setor elétrico deparam-se cada vez mais com as exigências do mercado energético sendo obrigadas a assegurarem aos seus clientes bons níveis de continuidade e confiabilidade no serviço de fornecimento da energia elétrica e também atender os índices de continuidade do serviço estabelecidos pela agência reguladora do setor elétrico (ANEEL - Agência Nacional de Energia Elétrica). Para alcançar estes objetivos além de investir na otimização dos seus sistemas de transmissão e distribuição, as empresas responsáveis têm investido na automação de suas operações, buscando alternativas que reduzam os tempos de interrupção por faltas permanentes nos sistemas de potência. Através de informações disponíveis em uma subestação, é possível estabelecer um procedimento para determinar e classificar condições de faltas, localizando o elemento de proteção acionado, e assim fornecer o apoio à tomada de decisão no ambiente de subestações de sistemas de distribuição de energia elétrica. Neste trabalho é proposta uma metodologia que fornece respostas rápidas (controle on line), para detecção e classificação de faltas em sistemas de distribuição de energia elétrica através de informações analógicas disponíveis em uma subestação, tais como amostras de sinais de tensões e correntes na saída dos alimentadores, com uma arquitetura reconfigurável paralela que usa dispositivos lógicos programáveis (Programables Logics Devices - PLDs) -FPGAs e a linguagem de descrição de hardware - VDHL (Very High Speed Integraded Circuit - VHSIC). Para validar o sistema proposto, foram gerados dados de forma aleatória, compatíveis com informações fornecidas em tempo real pelo sistema SCADA (supervisory control and data-acquisition) de uma subestação real. Os resultados obtidos com as simulações realizadas, mostram que a... (Resumo completo, clicar acesso eletrônico abaixo)
Abstract: Currently companies of the energy industry is facing increasingly with the requirements of the energy market are obliged to ensure their customers good levels of continuity in service and reliability of supply of electric energy and also meet the rates of continuity of service established by the agency regulator of the energy industry (ANEEL - National Electric Energy Agency). To achieve these goals than to invest in optimization of its transmission and distribution systems, the companies responsible have invested in automation of its operations, seeking alternatives that reduce the time of interruption by failures in the systems of permanent power. Through information available in a substation, it is possible to establish a procedure for identifying and classifying conditions of absence, finding the element of protection driven, and thus provide support for decision-making within the environment of substations to distribution systems for power. This work is proposed a methodology that provides quick answers (control online), for detection and classification of faults in distribution systems of electric energy through analog information available on a substation, such as samples for signs of tensions and currents in the output of feeders, with an architecture that uses parallel reconfigurable programmable logic devices (Programables Logics Devices - PLDs)-FPGAs and the language of description of hardware - VDHL (Very High Speed Circuit Integraded - VHSIC). To validate the proposed system, data were generated at random, consistent with information provided by the system in real time SCADA (supervisory control and data-acquisition) of a real substation. The results obtained with the simulations conducted, show that the proposed methodology, presents satisfactory results, and times of reasonable answers.
Mestre
Oliveira, Alisson Antônio de. "Estudo e implementação de operações em ponto fixo em FPGA com VHDL 2008: aplicação em controle de sistemas em tempo discreto." Universidade Tecnológica Federal do Paraná, 2012. http://repositorio.utfpr.edu.br/jspui/handle/1/473.
Full textThere are machines that need large processing speed for its correct working, these machines have a critical time response processing. When it is considered that aspect coupled with the need for control of static and dynamic behavior of a system arrives at the controller with strong demands on runtime. This dissertation compares discrete controllers implemented in fixed point with different accuracies, using for both the simulation of the behavior of controllers manufactured in Matlab command language and VHDL 2008. VHDL 2008 still in development and standardization by the IEEE. The VHDL language is used in FPGAs that are high speed devices with parallel processing capability. The main objective of this work is the study and implementation of discrete controllers in FPGA with the help of the VHDL 2008 language, determining its strengths and limitations, particularly in regard to the structure of programming, error analysis and demand for resources. Results show that accuracy still need some improvements a standard to the VHDL 4.0, known as VHDL 2008, is delivered to the market a stable standard. However, knowing it limitations, it is possible implementations and use in conversion of analog signals to discrete, such as control and dynamic systems simulation like servomechanisms.
Hofmann, Maicon Bruno. "Implementação em FPGA de compensadores de desvios para conversor analógico digital intercalado." Universidade Tecnológica Federal do Paraná, 2016. http://repositorio.utfpr.edu.br/jspui/handle/1/1809.
Full textThis work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.