Journal articles: 'VHDL (VHSIC hardware description language)'

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Sciuto, D. "VHDL( VHSIC Hardware Description Language)." Journal of Systems Architecture 42, no. 2 (September 1996): 95–96. http://dx.doi.org/10.1016/1383-7621(96)00015-x.

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Mahmudi, Ali, Sentot Achmadi, and Michael. "Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes." MATEC Web of Conferences 164 (2018): 01003. http://dx.doi.org/10.1051/matecconf/201816401003.

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In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained.

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Shetty, Mamtha. "Design of BPSK Modulator Using VHDL." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, no. 12 (October 23, 2014): 5247–52. http://dx.doi.org/10.24297/ijct.v13i12.5276.

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Binary Phase Shift Keying represents the simulation results of binary digital modulation schemes. Here for BASK and BPSK modulation techniques use FPGA algorithm. If multiplier block is used for multiplication bit stream with carrier signal, used time will rises. In addition using multiplier block obtained simulation results were analyzed and compared to other simulation results. Source consumptions of FPGA-based BASK modulation technique and BPSK modulation technique were compared. Also, for different modulation algorithm, source consumptions of BASK and BPSK modulation technique were analyzed using VHDL. Designed modulators using VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL) was realized on high speed FPGA (Field Program Programmable Gate Array). Because for used modulation technique data rate transfer is fairly important in wireless communication systems. The highest speed data rate transfer can be realized using fiber optic cables. In addition, BER (Bit Error Rate) of BASK and BPSK modulator was compared using MATLAB simulation program. Binary data rate is same for BPSK and BASK. BPSK and BASK modulations were designed on FPGA using VHDL hardware description language.

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Ameur, Noura Ben, Nouri Masmoudi, and Mourad Loulou. "FPGA-Based Design Δ–Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit." Journal of Circuits, Systems and Computers 24, no. 03 (February 10, 2015): 1550037. http://dx.doi.org/10.1142/s0218126615500371.

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This paper, focus on synthesis design of a Δ–Σ digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio DAC. The features of the design are high-precision, fast processing and low-cost. The related work is done with the MATLAB & QUARTUS II simulators.

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Cesar, da Costa, and Oliveira Santin Christian. "Design and simulation of direct torque control of induction motors using VHSIC Hardware Description Language (VHDL)." Scientific Research and Essays 12, no. 11 (June 15, 2017): 103–12. http://dx.doi.org/10.5897/sre2017.6501.

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Montiel-Ross, Oscar, Jorge Quiñones, and Roberto Sepúlveda. "Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors." Advances in Fuzzy Systems 2012 (2012): 1–11. http://dx.doi.org/10.1155/2012/475894.

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This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor.

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Chou, Hsin-Hung, Ying-Shieh Kung, Tai-Wei Tsui, and Stone Cheng. "FPGA-BASED MOTION CONTROLLER FOR WAFER-HANDLING ROBOT." Transactions of the Canadian Society for Mechanical Engineering 37, no. 3 (September 2013): 427–37. http://dx.doi.org/10.1139/tcsme-2013-0032.

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This study applies FPGA (Field Programmable Gate Arrays) technology to implement a motion controller for wafer-handling robot which has three-DOF (Degree of Freedom) motion. The proposed FPGA-based motion controller has two modules. The first module is Nios II processor which is used to realize the motion trajectory computation and the three-axis position/speed controllers. The second module is demonstrated to implement the three-axis current vector controllers by using FPGA hardware, and VHDL (VHSIC Hardware Description Language) is adopted to describe the controller behavior. Therefore, a fully digital motion controller for wafer-handling robot, such as one trajectory planning, three current vector controllers and three position/speed controllers are all implemented with an FPGA chip.

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SHARMA, SUBHASH KUMAR, SHRI PRAKASH DUBEY, and ANIL KUMAR MISHRA. "Development of Library Components for Floating Point Processor." Journal of Ultra Scientist of Physical Sciences Section A 33, no. 4 (June 15, 2021): 42–50. http://dx.doi.org/10.22147/jusps-a/330402.

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This paper deals with development of an n-bit binary to decimal conversion, decimal to n bit binary conversion and decimal to IEEE-754 conversion for floating point arithmetic logic unit (FPALU) using VHDL. Normally most of the industries now a days are using either 4-bit conversion of ALU or 8-bit conversions of ALU, so we have generalized this, thus we need not to worry about the bit size of conversion of ALU. It has solved all the problems of 4-bit, 8-bit, 16-bit conversions of ALU’s and so on. Hence, we have utilized VHSIC Hardware Description Language and Xilinx in accomplishing this task of development of conversions processes of ALU

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Rampa, Vittorio. "Design and Implementation of a Low Complexity Multiuser Detector for Hybrid CDMA Systems." Journal of Communications Software and Systems 1, no. 1 (April 6, 2017): 42. http://dx.doi.org/10.24138/jcomss.v1i1.316.

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In hybrid CDMA systems, multiuser detection (MUD) algorithms are adopted at the base station to reduce both multiple access and inter-symbol interference by exploitingspace-time (ST) signal processing techniques. Linear ST-MUD algorithms solve a linear problem where the system matrix has a block-Toeplitz shape. While exact inversion techniques impose an intolerable computational load, reduced complexity algorithms may be efficiently employed even if they show suboptimal behavior introducing performance degradation and nearfar effects. The block-Fourier MUD algorithm is generally considered the most effective one. However, the block-Bareiss MUD algorithm, that has been recently reintroduced, shows also good performance and low computational complexity comparingfavorably with the block-Fourier one. In this paper, both MUD algorithms will be compared, along with other well known ones, in terms of complexity, performance figures, hardware feasibility and implementation issues. Finally a short hardware description of the block-Bareiss and block-Fourier algorithms will be presented along with the FPGA (Field Programmable Gate Array) implementation of the block-Fourier using standard VHDL (VHSIC Hardware Description Language) design.

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Kung, Ying-Shieh, Jin-Mu Lin, Yu-Jen Chen, and Hsin-Hung Chou. "ModelSim/Simulink Cosimulation and FPGA Realization of a Multiaxis Motion Controller." Mathematical Problems in Engineering 2015 (2015): 1–17. http://dx.doi.org/10.1155/2015/202474.

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This paper is to implement a multiaxis servo controller and a motion trajectory planning within one chip. At first, SoPC (system on a programmable chip) technology which is composed of an Altera FPGA (field programmable gate arrays) chip and an embedded soft-core Nios II processor is taken as the development of a multiaxis motion control IC. The multiaxis motion control IC has two modules. The first module is Nios II processor which realizes the motion trajectory planning by software. It includes the step, circular, window, star, and helical motion trajectory. The second module presents a function of the multiaxis position/speed/current controller IP (intellectual property) by hardware. And VHDL (VHSIC Hardware Description Language) is applied to describe the multiaxis servo controller behavior. Before the FPGA realization, a cosimulation work by ModelSim/Simulink is applied to test the VHDL code. Then, this IP combined by Nios II processor will be downloaded to FPGA. Therefore, a fully digital multiaxis motion controller can be realized by a single FPGA chip. Finally, to verify the effectiveness and correctness of the proposed multiaxis motion control IP, a three-axis motion platform (XYZtable) is constructed and some experimental results are presented.

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Chou, Hsin Hung, Ying Shieh Kung, Tai Wei Tsui, and Stone Cheng. "Realization of a Motion Control System for Wafer-Handling Robot Using SoPC Technology." Applied Mechanics and Materials 284-287 (January 2013): 1909–13. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.1909.

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The novel FPGA (Field Programmable Gate Arrays) can embed a processor to be an SoPC (System-on-a-Programmable-Chip) environment which allows user to design the applications by mixing hardware and software. Therefore, a motion control system of wafer-handling robot based on the SoPC technology is presented in this paper. In FPGA, it is consists of two modules. The first module is Nios II processor which is used to realize the motion trajectory planning and three-axis position/speed controllers by software. The program developed in Nios II processor uses C language. The second module is presented to implement three-axis current vector controllers by hardware, and VHDL (VHSIC Hardware Description Language) is applied to describe the controller behavior. Therefore, a fully digital motion controller for wafer-handling robot, such as three current vector controllers, three position/speed controller and one trajectory planning are all can implemented by a single FPGA chip. Finally, an experimental system constructed by an FPGA experimental board, one three-DOF wafer-handling robot, and three inverters is set up to demonstrate the correctness and effectiveness of the proposed SoPC-based motion control system of wafer-handling robot.

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Zamiri, Elyas, Alberto Sanchez, Marina Yushkova, Maria Sofia Martínez-García, and Angel de Castro. "Comparison of Different Design Alternatives for Hardware-in-the-Loop of Power Converters." Electronics 10, no. 8 (April 13, 2021): 926. http://dx.doi.org/10.3390/electronics10080926.

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This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods and numerical formats considering possible synthesis tools (Precision and Vivado), and it comprises an analytical discussion in terms of area and speed. The different models are synthesized as ad-hoc modules in general-purpose FPGAs, but also using the NI myRIO device as an example of a commercial tool capable of implementing HIL models. The comparison confirms that the optimum design alternative must be chosen based on the application (complexity, frequency, etc.) and designers’ constraints, such as available area, coding expertise, and design effort.

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Ameur, Noura Ben. "A Low-Phase Noise ADPLL Based on a PRBS-Dithered DDS Enhancement Circuit." Journal of Circuits, Systems and Computers 26, no. 05 (February 8, 2017): 1750076. http://dx.doi.org/10.1142/s0218126617500761.

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This paper aims to design an all-digital phase-locked loop (ADPLL) intended for professional digital audio data conversion applications. The method used for designing is based on an analogy between analog PLL and ADPLL. Managing a low-jitter effect, a comparative study between discrete voltage-controlled oscillator (DVCO) and direct digital synthesis (DDS) based on a pseudorandom binary sequence (PRBS) generator is performed. The features of the design in this work are high-precision and low harmonic distortion DDS which is combined with ADPLL. For model-based design validation, a rapid register transfer level (RTL) with VHSIC hardware description language (VHDL) is practiced and the dynamic performance result indicates a significant improvement in total harmonic distortion (THD) ([Formula: see text][Formula: see text]dB) and a better resolution of 18.97[Formula: see text]bits for audio applications based on the aid of phase dithering DDS enhancement circuit.

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El-Medany, Wael, Alauddin Al-Omary, Riyadh Al-Hakim, and Taher Homeed. "Reconfigurable SRTM System for Road Traffic in Kingdom of Bahrain." Transport and Telecommunication Journal 17, no. 4 (December 1, 2016): 298–306. http://dx.doi.org/10.1515/ttj-2016-0026.

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Abstract This paper presents reconfigurable hardware architecture for smart road traffic system based on Field Programmable Gate Array (FPGA). The design can be reconfigured for different timing of the traffic signals according to the received and collected data read by the different sensors on the road; the design has been described using VHDL (VHSIC Hardware Description Language). The SRTM (Smart Road Traffic Management) System has some more features that help passenger to avoid traffic jamming by sending the collected information through web/mobile applications to find the best road between the start and destination points, which will be displayed on Google maps, at the same time it will also shows the points of traffic jamming on Google maps. SRTM system can also manage emergency vehicles such as ambulance and fire fighter and also can send snapshots and video streaming for different roads and junctions to show the points of traffic jamming. The design has been simulated and tested using ModelSim PE student edition 10.4. Spartan 3 FPGA starter kit from Xilinx has been used for implementing and testing the design in a hardware level.

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Motupalle, Haritha, and Syed Jahangir Badashah. "A Novel VLSI Architecture for SPHIT Encoder." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 10, no. 4 (August 15, 2013): 1522–30. http://dx.doi.org/10.24297/ijct.v10i4.3252.

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In this Paper we propose a highly scalable image compression scheme based on the set partitioning in hierarchical trees (SPIHT) algorithm. Our algorithm called highly scalable SPIHT (HS-SPIHT), supports spatial and SNR scalability and provides a bit stream that can be easily adapted (reordered) to given bandwidth and resolution requirements by a simple transcoder (parser). The HS-SPIHT algorithm adds the spatial scalability feature without sacrificing the SNR embeddedness property as found in the original SPIHT bit stream. HS-SPIHT finds applications in progressive Web browsing, flexible image storage and retrieval, and image transmission over heterogeneous networks. Here we have written the core processor Microblaze is designed in VHDL (VHSIC hardware description language), implemented using XILINX ISE 8.1 Design suite the algorithm is written in system C Language and tested in SPARTAN-3 FPGA kit by interfacing a test circuit with the PC using the RS232 cable. The test results are seen to be satisfactory. The area taken and the speed of the algorithm are also evaluated.

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Mylonas, Eleftherios, Nikolaos Tzanis, Michael Birbas, and Alexios Birbas. "An Automatic Design Framework for Real-Time Power System Simulators Supporting Smart Grid Applications." Electronics 9, no. 2 (February 9, 2020): 299. http://dx.doi.org/10.3390/electronics9020299.

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Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for real-time power system simulators is needed. In this article, a prototype of this approach is presented, employing Field Programmable Gate Array (FPGA) platforms due to their reconfigurability that enables low-power, low-latency, and high-performance designs, as a first attempt towards an open source platform, compatible with the majority of hardware design suites. It comprises two major parts: (i) a user-oriented section, built in Matlab/Simulink; and (ii) a hardware-oriented section, written in Matlab and Very High Speed Integrated Circuit (VHSIC)-Hardware Description Language (VHDL) code. To verify its functionality, two test power networks were given in a schematic format, analyzed through Matlab code and turned into dedicated hardware simulators with the aid of the VHDL template. Then, simulation results from Simulink and the prototype were compared for error estimation. The results show the prototype’s successful implementation with minimal resources utilization, high performance and low latency in the order of nanoseconds in Xilinx 6- and 7-series FPGAs, therefore proving its modularity and efficient use in many different scenarios, meeting low-latency/real-time requirements while enabling further smart grid research.

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Batista, Edson A., Moacyr A. G. de Brito, João C. Siqueira, Jeandro C. Dias, Raphael C. Gomez, Maurilio F. R. Catharino, and Matheus B. Gomes. "A Multifunctional Smart Meter Using ANN-PSO Flux Estimation and Harmonic Active Compensation with Fuzzy Voltage Regulation." Sensors 21, no. 12 (June 17, 2021): 4154. http://dx.doi.org/10.3390/s21124154.

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This paper aims to present the analysis and development of a complete electronic smart meter that is able to perform four-quadrant measurements, act as a three-phase shunt active power filter (APF), and control three-phase induction motors by stator flux estimation. A transmission control protocol together with Internet protocol (TCP/IP) communication protocol for the remote access of measurement data is embedded into the application to securely transmit reliable information. An artificial neural network trained with particle swarm optimization is used for stator flux estimation, and a fuzzy logic controller is adopted to regulate the power converter DC bus voltage. The present work gathers knowledge from multidisciplinary fields, and all applied techniques have not been proposed altogether before. All control functions are embedded into a field-programmable gate array (FPGA) device, using VHSIC Hardware Description Language (VHDL), to enhance efficiency taking advantage of parallelism and high speed. An FPGA-in-the-loop cosimulation technique was first applied to prove the control functions’ functionality, and, later, experimental evaluations are conducted to finally prove equipment operation and reliability.

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El Makhloufi, Assaad, Nisrine Chekroun, Noha Tagmouti, Samir El Adib, and Naoufal Raissouni. "Improvements in space radiation-tolerant FPGA implementation of land surface temperature-split window algorithm." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 5 (October 1, 2021): 3844. http://dx.doi.org/10.11591/ijece.v11i5.pp3844-3854.

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The trend in satellite remote sensing assignments has continuously been concerning using hardware devices with more flexibility, smaller size, and higher computational power. Therefore, field programmable gate arrays (FPGA) technology is often used by the developers of the scientific community and equipment for carrying out different satellite remote sensing algorithms. This article explains hardware implementation of land surface temperature split window (LST-SW) algorithm based on the FPGA. To get a high-speed process and real-time application, VHSIC hardware description language (VHDL) was employed to design the LST-SW algorithm. The paper presents the benefits of the used Virtex-4QV of radiation tolerant series FPGA. The experimental results revealed that the suggested implementation of the algorithm using Virtex4QV achieved higher throughput of 435.392 Mbps, and faster processing time with value of 2.95 ms. Furthermore, a comparison between the proposed implementation and existing work demonstrated that the proposed implementation has better performance in terms of area utilization; 1.17% reduction in number of Slice used and 1.06% reduction in of LUTs. Moreover, the significant advantage of area utilization would be the none use of block RAMs comparing to existing work using three blocks RAMs. Finally, comparison results show improvements using the proposed implementation with rates of 2.28% higher frequency, 3.66 x higher throughput, and 1.19% faster processing time.

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Mayer, Kayol Soares, Candice Müller, Fernando Cesar Comparsi de Castro, and Maria Cristina Felippetto de Castro. "A New CPFSK Demodulation Approach for Software Defined Radio." Journal of Circuits, Systems and Computers 28, no. 14 (February 8, 2019): 1950243. http://dx.doi.org/10.1142/s0218126619502438.

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This paper proposes a new coherent Frequency-Shift Keying (FSK) demodulation technique for software defined radio platform, based on a new Digital Phase Locked Loop (DPLL) architecture. The proposed DPLL addresses the frequency dependence on classic DPLL architectures found in the literature. In classical approaches, the loop filter constants are dependent on the frequency level of the FSK transmitted symbols. The proposed approach applies a simpler feedback loop, with a single integrator and a phase detector architecture based on the small-angle approximation [Formula: see text], which resulted in a DPLL totally independent of frequency. The proposed demodulator has been implemented in Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) and evaluated for continuous-phase frequency shift keying (CPFSK) and Gaussian minimum shift keying (GMSK) signals. For CPFSK signals, the demodulator has been evaluated for 2, 4 and 8 frequency levels, with modulation indexes [Formula: see text], [Formula: see text] and [Formula: see text], respectively. For evaluation of GMSK signals, several Gaussian filter bandwidths were considered. In addition, a brief analysis for 2-CPFSK and GMSK is presented over multipath and carrier frequency offset. Results show that the proposed method presents a significantly reduced bit error rate when compared to other coherent methods presented in the literature.

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Shahdad, Lipsett, Marschner, Sheehan, and Cohen. "VHSIC Hardware Description Language." Computer 18, no. 2 (February 1985): 94–103. http://dx.doi.org/10.1109/mc.1985.1662802.

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Dickinson, Brian. "VHDL '92: The new features of the VHDL hardware description language." Microprocessors and Microsystems 19, no. 2 (January 1995): 106–7. http://dx.doi.org/10.1016/0141-9331(95)90002-0.

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Tezak, Nikolas, Armand Niederberger, Dmitri S. Pavlichin, Gopal Sarma, and Hideo Mabuchi. "Specification of photonic circuits using quantum hardware description language." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1979 (November 28, 2012): 5270–90. http://dx.doi.org/10.1098/rsta.2011.0526.

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Following the simple observation that the interconnection of a set of quantum optical input–output devices can be specified using structural mode VHSIC hardware description language, we demonstrate a computer-aided schematic capture workflow for modelling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations of motion, illustrate our approach using simple examples based on linear and cavity-nonlinear optical components, and demonstrate a computational approach to hierarchical model reduction.

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Soe, Ei Phyu, Myint Myint Soe, and Htet Htet Yi. "Analysis and Synthesis of Elevator Controller Based On VHSIC Hardware Description Language." International Journal of Scientific and Research Publications (IJSRP) 9, no. 4 (April 6, 2019): p8806. http://dx.doi.org/10.29322/ijsrp.9.04.2019.p8806.

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Doligalski, Michał, and Marian Adamski. "Hierarchical Configurable Petri Net Modeling in VHDL." International Journal of Electronics and Telecommunications 58, no. 4 (December 1, 2012): 397–402. http://dx.doi.org/10.2478/v10177-012-0054-y.

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Abstract The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dual model is an alternative way for behavioral description of the discrete control process. Dual model consists of two correlated models: UML state machine diagram and hierarchical configurable Petri net (HCfgPN). HCfgPN are Petri nets variant with direct support of exceptions handling mechanism. Logical synthesis of dual model is realized by the description of HCfgPN model by means of hardware description language. The paper presents placesoriented method for HCfgPN description in VHDL language

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Varga, László, Gábor Hosszú, and Ferenc Kovács. "Design Procedure Based on VHDL Language Transformations." VLSI Design 14, no. 4 (January 1, 2002): 349–54. http://dx.doi.org/10.1080/10655140290011159.

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One of the major problems within the VHDL based behavioral synthesis is to start the design on higher abstraction level than the register transfer level (RTL). VHDL semantics was designed strictly for simulation, therefore it was not considered as high-level synthesis language. A novel synthesis procedure was developed, which uses the methodology of high level synthesis. It starts from an abstract VHDL model and produces an RTL VHDL description through successive language transformations while preserving the VHDL standard simulation semantics. The steps of the synthesis do not use graph representation or other meta-language, but apply the standard VHDL only. This VHDL representation is simulatable and accessible, functional verification can be performed by simulation at any time, and the simulation results can be used to guide the synthesis process. The output VHDL format is suitable to continue the design flow with RTL based synthesis tools.

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Yanbing Li and M. Leeser. "HML, a novel hardware description language and its translation to VHDL." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, no. 1 (February 2000): 1–8. http://dx.doi.org/10.1109/92.820756.

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Yi, Zhao Xiang, Xiong Mei Zhang, Ning Li, and Xiao Dong Mu. "A Visual Dependency Analysis Method Based on VHDL." Applied Mechanics and Materials 738-739 (March 2015): 582–85. http://dx.doi.org/10.4028/www.scientific.net/amm.738-739.582.

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Modern complex circuits are described in very high speed integrated circuit hardware description language (VHDL) and difficult to verify. This paper proposes a systematic and visual dependency analysis method based on VHDL. The dependency relationships including control dependency, data dependency, signal control dependency and signal data dependency are defined. The entity dependency graph is presented and its generation algorithm, which searches the dependency relationships in hardware processes and between hardware processes, are developed. The experiment of a typical keyboard demonstrates that it is a visual and efficient method to analyze dependency relationships of VHDL for formal verification.

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Christen, E., and K. Bakalar. "VHDL-AMS-a hardware description language for analog and mixed-signal applications." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46, no. 10 (1999): 1263–72. http://dx.doi.org/10.1109/82.799677.

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Khan, Wilayat, Basim Azam, Noman Shahid, Abdul Moeed Khan, and Ahtisham Shaheen. "Formal Verification of Digital Circuits Using Simulator with Mathematical Foundation." Applied Mechanics and Materials 892 (June 2019): 134–42. http://dx.doi.org/10.4028/www.scientific.net/amm.892.134.

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To ease hardware design process, circuits are normally designed in description languages such as Verilog and VHDL. The correctness of circuits is normally checked by exhaustive simulation in simulators such as Icarus and VCS. Both the description languages Verilog/VHDL and simulators Icarus/VCS do not have mathematical foundations and hence are not reliable and cannot be used to mathematically prove correctness of circuit designs. Hardware description languages with mathematical (formal) foundation such as VeriFormal, on the other hand, are more reliable, trustworthy and can be used for robust design. In this paper, we report our results of formal verifications of two simple hardware circuits designed in the formal description language VeriFormal. Using the VeriFormal simulator and the accompanied type checker tools, we prove reliability properties type safety, functional correctness and functional equivalence of the digital circuits.

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Shiva, Sajjan G., and Judit U. Jones. "A VHDL Based Expert System for Hardware Synthesis." VLSI Design 1, no. 2 (January 1, 1994): 113–26. http://dx.doi.org/10.1155/1994/93168.

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This paper describes an expert system for Hardware Synthesis. Details of the target digital system are input to the expert system using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The VHDL representation is first translated to a knowledge representation scheme known as a ‘hologram’ which is a combination of rule, frame and semantic network representation schemes. The hologram representation of the target system is then input to the inference engine, which matches the target system to the Knowledge Base components and selects an appropriate set for implementation, and connects them creating a digital circuit. Some design examples are described. The expert system approach results in designs very close to designs from a human designer. In its present form, the system does not perform a design space exploration for alternate designs, but expects the designer to alter the VHDL representation, after observing the results from previous design cycles.

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Sun, Si Tong, An Gang Tian, and De Cai Zhuang. "The Design of Electronic Code Lock." Advanced Materials Research 267 (June 2011): 1001–4. http://dx.doi.org/10.4028/www.scientific.net/amr.267.1001.

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In this paper, by using EDA technology, Quartus II6.0 working platform and VHDL hardware description language, an electronic code lock based on the programmable gate array FPGA is designed with a top-down design.

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Alami Hassani, Aicha, Mohcine Zouak, and Mostafa Mrabti. "Contribution to Synchronization and Tracking Modelisation in a CDMA Receiver." Journal of Engineering 2013 (2013): 1–7. http://dx.doi.org/10.1155/2013/936495.

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We propose and analyze a noncoherent receiver with PN code tracking for direct sequence code division multiple access (DS-CDMA) communication systems. We employ the delay-lock loop (DLL) architectures for the tracking stage. The choice of DLL parameters is studied with special focus on DS-CDMA communication systems and orthogonality conditions. We described the modeling and simulation of the NCO using hardware description language VHDL. Details of the VHDL implementation are shown.

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Memon, Farida, Aamir Hussain Memon, Shahnawaz Talpur, Fayaz Ahmed Memon, and Rafia Naz Memon. "Design and Co-Simulation of Depth Estimation Using Simulink HDL Coder and Modelsim." July 2016 35, no. 3 (July 1, 2016): 473–82. http://dx.doi.org/10.22581/muet1982.1603.17.

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In this paper a novel VHDL design procedure of depth estimation algorithm using HDL (Hardware Description Language) Coder is presented. A framework is developed that takes depth estimation algorithm described in MATLAB as input and generates VHDL code, which dramatically decreases the time required to implement an application on FPGAs (Field Programmable Gate Arrays). In the first phase, design is carriedout in MATLAB. Using HDL Coder, MATLAB floating- point design is converted to an efficient fixed-point design and generated VHDL Code and test-bench from fixed point MATLAB code. Further, the generated VHDL code of design is verified with co-simulation using Mentor Graphic ModelSim10.3d software. Simulation results are presented which indicate that VHDL simulations match with the MATLAB simulations and confirm the efficiency of presented methodology.

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Zhu, Juan, and Yue Chen. "Step Motor Control Based on FPGA." Applied Mechanics and Materials 397-400 (September 2013): 1226–29. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.1226.

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Design a step motor control system based on Field Programmable Gate Array (FPGA). Give the hardware circuit of this system and the program based on very high speed integrated circuit hardware description language (VHDL). Compared to step motor control system based on single chip microcomputer, the processing speed of this system is faster.

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Szecówka, Przemysław M., and Patryk W. Marucha. "Dedicated Digital Hardware for DVB-CSA Encryption." International Journal of Electronics and Telecommunications 58, no. 3 (September 2012): 241–46. http://dx.doi.org/10.2478/v10177-012-0033-3.

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Abstract DVB-CSA (Digital Video Broadcast – Common Scrambling Algorithm) is encryption method commonly used to protect the paid channels of digital television. The paper presents a study of its implementation in specialized digital hardware. The algorithm was successfully converted to logic architecture, coded in hardware description language (VHDL), verified and synthesized for programmable logic device (FPGA). For Xlinx Spartan 3 implementation, the expected throughput may be estimated to 100 Mbps in pipelined mode.

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Hu, Xiao Li, Li Ding, and Zhi Gang Zhang. "The Design of Digital Filter Based on DSP Builder." Applied Mechanics and Materials 602-605 (August 2014): 2641–44. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2641.

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This paper model digital FIR low-pass by using the Toolbox of the DSP Builder in MATLAB and convert to VHDL hardware description language, compile and simulation through QUARTUS II software automatically, download and verified by EPF10K20RC208-4.The design combine MATLAB software with FPGA hardware organic ally and completes the transplant of the FIR low-pass filter.

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Palanisamy, R., C. S. Boopathi, K. Selvakumar, and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (April 1, 2020): 1722. http://dx.doi.org/10.11591/ijece.v10i2.pp1722-1727.

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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.

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Palanisamy, R., and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (July 1, 2019): 81. http://dx.doi.org/10.11591/ijres.v8.i2.pp81-85.

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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.

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Miriampally, Venkata Raghavendra. "Simulation of PCI Express™ Transaction Layer Using Hardware Description Language." International Journal of Informatics and Communication Technology (IJ-ICT) 4, no. 1 (April 1, 2015): 7. http://dx.doi.org/10.11591/ijict.v4i1.pp7-12.

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PCI Express is a high-speed serial connection that operates more like a network than a bus. PCI Express will serve as a general purpose I/O interconnects for a wide variety of future computing and communications platforms. PCI Express (PCIe) is implemented with a split-transaction protocol that provides more bandwidth and is compatible with existing operating systems. PCI Express has three discrete logical layers: the Transaction Layer, the Data Link Layer, and the Physical Layer. This paper analyze and simulates the function of Transaction layer IP core in the System Level with top-down design method, wrote the codes to implement Transaction Layer using Very high speed hardware description language (VHDL) and provided the simulation results using Active HDL Simulation tool. The simulation result shows that the designed IP core meets the required protocol specifications for the proper functioning of PCI Express Transaction layer.

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Tural-Polat, Sadiye Nergis. "A Complete Embedded System Design of Breakout Game." Journal of Circuits, Systems and Computers 26, no. 12 (August 2017): 1750188. http://dx.doi.org/10.1142/s0218126617501882.

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In this paper, we synthesize a Breakout game code which runs on an FPGA development and education board. For this purpose, an original Breakout game code that runs exclusively on the FPGA board is designed in VHDL hardware description language. The strength of this design is that the code does not require any SRAM modules for storage which eliminates the memory requirements and results in faster operation. Altera DE0 development and education board is used for the implementation. However, since only the standard VHDL functions is used in the code, it can run on any other FPGA boards.

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PIERRE, LAURENCE. "INDUCTION-ORIENTED VERIFICATION OF REPLICATED ARCHITECTURES DESCRIBED IN VHDL." Journal of Circuits, Systems and Computers 10, no. 03n04 (June 2000): 181–204. http://dx.doi.org/10.1142/s0218126600000159.

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This paper is concerned with the application of theorem proving techniques to the formal proof of hardware. More precisely, we aim at providing a methodology for applying provers like Nqthm or Acl2 to the formal verification of parameterized replicated circuits. Nqthm (the Boyer–Moore theorem prover) and its successor Acl2 are induction-based systems; their formalisms are respectively a simplified Lisp-like language and Common Lisp. Hence, the circuits we consider must be given a purely functional representation. Moreover, our work puts the emphasis on the integration of formal proof techniques in CAD (Computer Aided Design) environments which support Hardware Description Languages in which replication is expressed by iteration. Therefore, we associate with the iterative statement of the VHDL language a functional semantics that guarantees an easy translation from VHDL to Nqthm/Acl2 while simplifying the subsequent inductive proofs. The approach has been successfully applied to one-dimensional as well as two-dimensional structures.

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Wang, Ji Chang, and Huan Huan Quan. "Applied Mechanics and Applied Technology in Fuel Injection Pump Bench Rotational Speed Measurement System Design Based on CPLD." Advanced Materials Research 910 (March 2014): 316–19. http://dx.doi.org/10.4028/www.scientific.net/amr.910.316.

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In the article, proposing one kind of design plan about rotational speed measurement system design based CPLD. Various modules design has completed according to EDA tools and VHDL hardware description language. The feasibility of the speed measurement system design was verified based on the experiment. At present, the system has been successfully application in the fuel injection pump test-bed.

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Zhang, Zi Sheng, Chun Sheng Wang, Yi Wang, Zhan You Wang, and Deng Yuan Song. "Power and Vibration of Electrostatic Precipitator Control Based on FPGA." Advanced Materials Research 1037 (October 2014): 244–47. http://dx.doi.org/10.4028/www.scientific.net/amr.1037.244.

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In order to improve the automation level of the electrostatic precipitator, we used Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) language to compile, emulate and optimize the control system of power source and vibration. In the design of Quartus platform, we used EP1C3T144C8 Field Programmable Gate Array (FPGA) chip to realize high voltage power supply, alarm and protection system. We also realized the compilation and simulation test of each part’s function of 20 s rapping and 40 min rapping cycle. At the same time, we recorded the waveform of simulation. It demonstrated that the validity of the relevant VHDL compilation. We used this method to achieve the optimization control of the electrostatic precipitator operating parameters. It has a strong practicability.

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Zhu, Juan Hua, Ang Wu, and Juan Fang Zhu. "Research and Design of Digital Clock Based on FPGA." Advanced Materials Research 187 (February 2011): 741–45. http://dx.doi.org/10.4028/www.scientific.net/amr.187.741.

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A digital clock system designed by using VHDL hardware description language is presented in this paper. The proposed architecture fully utilizes the digital clock system available on FPGA chips based top-down design method in the Quartus II development environment. The Clock system is divided into four design modules: core module, frequency_division module, display module and tune module. It not only can time accurately and display time, but also can reset and adjust time. The LED lights will flash and the loudspeaker will tell time on the hour. The architecture is implemented and verified experimentally on a FPGA board. Because of the universality of digital clock and the portability of VHDL language, it can be applied directly in various designs based on FPGA chip.

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Zheng, Hua Qiang, Li Fu Ma, Yang Liu, and Fei Cai. "Real-Time Video Convert System Design Based on LVDS." Advanced Materials Research 159 (December 2010): 514–21. http://dx.doi.org/10.4028/www.scientific.net/amr.159.514.

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In this paper, we designed a real-time video convert system for the imaging devices which used digital precision progressive scan monochrome camera or the similar camera and as video signal sensor. System hardware circuit design based on LVDS transmission chip, multiformat video decoder chip: ADV718X and the Cyclone II series FPGA. System software design based on hardware description language, verilog HDL and VHDL. The system could real-time capture, process CVBS and output LVDS video data without the system computer.

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Zhang, Hai Yan. "IP Core Design of 8253 Based on Quartus II." Applied Mechanics and Materials 380-384 (August 2013): 2941–44. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.2941.

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Provided by ALTERA FPGA/CPLD Quartus II development software development platform. programmable timer/counter 8253s functions and internal circuitry as the basis, combined with programmable gate array (FPGA) products FLEX10KE characteristics, using VHDL hardware description language and schematic Figure two ways 8253 for hierarchical, modular, parameterized logic design. The completed design will be configured to the chip of FLEX10KE,and Proved to be correct.

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Zhang, Wei Ping. "The Design and Implementation of Reconfigurable Cipher Unit on FPGA." Advanced Materials Research 760-762 (September 2013): 339–43. http://dx.doi.org/10.4028/www.scientific.net/amr.760-762.339.

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Encryption is the core of security technology. The paper managed to design and implement a kind of reconfigurable cipher unit based on the 3DES/AES and optimized by FPGA technology, which can effectively support diverse cryptographic algorithms and can meet the demand on system performance and flexibility. The unit uses hardware description language VHDL, layout and wire on QuartusII8.0. Finally the system is downloaded to DE2 for testing. The design hardware structure is simple, flexibility, security, which can be widely used in the field of information security.

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Kamar, Sara, Abdelmoniem Fouda, Abdelhalim Zekry, and Abdelmoniem Elmahdy. "FPGA implementation of RS codec with interleaver in DVB-T using VHDL." International Journal of Engineering & Technology 6, no. 4 (November 28, 2017): 171. http://dx.doi.org/10.14419/ijet.v6i4.8205.

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Digital television (DTV) provides a huge amount of information to many users at low cost. Recently, it can be packaged and fully integrated into completely digital transmission networks. Reed-Solomon code (RS) is one type of error correcting codes that can be used to enhance the performance of DTV. Interleaving/deinterleaving process enhances the performance of channel errors by spreading out random errors, very high-speed hardware description language (VHDL) is used in electronic design automation. It can be used as a general-purpose parallel programming language.This paper presents VHDL program for Reed-Solomoncodec (204, 188) and convolutional interleaver/deinterleaver, used in Digital Video Broadcasting-terrestrial system (DVB-T), according to ETSI EN 300 744 V1.5.1 standard. The VHDL programs are implemented on Xilinx 12.3 ISE and then simulated and tested via ISE simulator then the code is synthesized on FPGA device the results are compared with IP core for Xilinx 12.3 ISE, which gives the same results.

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Wang, Hua Pei, Dong Ji, and Dong Chen. "Design of High-Performance Vehicle Multi-Axis Optical Encoder Data Acquisition System Based on PC104 Bus." Applied Mechanics and Materials 333-335 (July 2013): 428–31. http://dx.doi.org/10.4028/www.scientific.net/amm.333-335.428.

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A high-performance vehicle multi-axis optical encoder data acquisition system based on PC104 bus is introduced. The paper puts emphases on the main function of the system module. VHDL hardware description language is used to design the modules, and ModelSim is introduced to implement logic and sequential simulation. An experiment is carried on in Altera EPF10K40 chip. Both the simulation and experimental results verify the correctness and validity of the method.

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Zhang, Zi Sheng, Yi Wang, Chun Sheng Wang, Jin Cui, and Zhi Qiang Liu. "The Control of High Voltage Electrostatic Precipitator Based on EDA." Advanced Materials Research 910 (March 2014): 336–39. http://dx.doi.org/10.4028/www.scientific.net/amr.910.336.

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In order to achieve the automatic control of electrostatic precipitator (ESP) more efficiently and accurately, an ESP system combining hardware and software is designed. According to the requirement of the ESP system,the Electronic Design Automation (EDA) is introduced to the ESP control system and the system is divided into four modules.These sub-modules are designed and the simulation waveform of the system is ananalyzed,based on the Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) programming language and Quartus software.The results show that the security, flexibility and reliabity of the system is improved by using EDA as the control ,which is a great value for generalization.

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Journal articles on the topic 'VHDL (VHSIC hardware description language)'

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