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Relevant bibliographies by topics / VHSIC Hardware Description Language (VHDL)

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Academic literature on the topic 'VHSIC Hardware Description Language (VHDL)'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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Journal articles on the topic "VHSIC Hardware Description Language (VHDL)"

1

Sciuto, D. "VHDL( VHSIC Hardware Description Language)." Journal of Systems Architecture 42, no. 2 (1996): 95–96. http://dx.doi.org/10.1016/1383-7621(96)00015-x.

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Mahmudi, Ali, Sentot Achmadi, and Michael. "Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes." MATEC Web of Conferences 164 (2018): 01003. http://dx.doi.org/10.1051/matecconf/201816401003.

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In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained.

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Patil, Archana. "Design and Simulation of Clock Divider using VHDL." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 05 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem33837.

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This paper presents the diesign and simulation of clock divider circuit using VHDL(VHSIC Hardware Description Language) on an FPGA(Field Programmable Gate Array). The clock divider circuit is a fundamental component in digital system for generating lower frequency clocks from a higher frequency reference clock. The paper starts up with simple divider where the clock is divided by even numbers, odd numbers and then later expands it into non- integer dividers. Keywords:- clock divider, D flipflop, FPGA

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Shetty, Mamtha. "Design of BPSK Modulator Using VHDL." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, no. 12 (2014): 5247–52. http://dx.doi.org/10.24297/ijct.v13i12.5276.

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Binary Phase Shift Keying represents the simulation results of binary digital modulation schemes. Here for BASK and BPSK modulation techniques use FPGA algorithm. If multiplier block is used for multiplication bit stream with carrier signal, used time will rises. In addition using multiplier block obtained simulation results were analyzed and compared to other simulation results. Source consumptions of FPGA-based BASK modulation technique and BPSK modulation technique were compared. Also, for different modulation algorithm, source consumptions of BASK and BPSK modulation technique were analyze

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NUHA, MUHAMMAD ULIN, HARI ARIEF DHARMAWAN, and SETYAWAN PURNOMO SAKTI. "Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10." ELKOMIKA: Jurnal Teknik Energi Elektrik, Teknik Telekomunikasi, & Teknik Elektronika 10, no. 1 (2022): 16. http://dx.doi.org/10.26760/elkomika.v10i1.16.

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ABSTRAKDesain arsitektur ADC (Analog to Digital Converter) multi kanal simultan pada perangkat kontroller dapat mengurangi jumlah intruksi (task) program yang harus dijalankan oleh mikroprosessor dan dapat digunakan untuk membentuk pengukuran simultan. Paper ini memaparkan desain ADC SAR (Successive Approximation Register) 10-bit dua kanal simultan menggunakan Board FPGA (Field Programmable Gate Array) Altera DE10. FPGA dikonfigurasi untuk difungsikan sebagai sirkuit logika SAR dua kanal menggunakan bahasa VHDL (VHSIC-Very High Speed Integrated Circuit Hardware Description Language). Hasil pen

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Ameur, Noura Ben, Nouri Masmoudi та Mourad Loulou. "FPGA-Based Design Δ–Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit". Journal of Circuits, Systems and Computers 24, № 03 (2015): 1550037. http://dx.doi.org/10.1142/s0218126615500371.

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This paper, focus on synthesis design of a Δ–Σ digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio D

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Pavani, Ms K. "Fault Diagnosis and Redundant Technique for 24 Hours Clock Design Using VHDL." International Journal for Research in Applied Science and Engineering Technology 13, no. 7 (2025): 17–21. https://doi.org/10.22214/ijraset.2025.72917.

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In digital systems, precise timekeeping and fault tolerance are essential, especially in mission-critical applications. This project presents the design and implementation of a 24-hour digital clock using VHDL (VHSIC Hardware Description Language) with integrated fault diagnosis and redundancy techniques. The primary objective is to ensure the accurate display of time and the continuous operation of the clock even in the presence of faults. A redundant architecture is employed to provide backup operations in case of component failure, and diagnostic logic is incorporated to detect and isolate

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Montiel-Ross, Oscar, Jorge Quiñones, and Roberto Sepúlveda. "Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors." Advances in Fuzzy Systems 2012 (2012): 1–11. http://dx.doi.org/10.1155/2012/475894.

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This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy P

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Chou, Hsin-Hung, Ying-Shieh Kung, Tai-Wei Tsui, and Stone Cheng. "FPGA-BASED MOTION CONTROLLER FOR WAFER-HANDLING ROBOT." Transactions of the Canadian Society for Mechanical Engineering 37, no. 3 (2013): 427–37. http://dx.doi.org/10.1139/tcsme-2013-0032.

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This study applies FPGA (Field Programmable Gate Arrays) technology to implement a motion controller for wafer-handling robot which has three-DOF (Degree of Freedom) motion. The proposed FPGA-based motion controller has two modules. The first module is Nios II processor which is used to realize the motion trajectory computation and the three-axis position/speed controllers. The second module is demonstrated to implement the three-axis current vector controllers by using FPGA hardware, and VHDL (VHSIC Hardware Description Language) is adopted to describe the controller behavior. Therefore, a fu

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Cesar, da Costa, and Oliveira Santin Christian. "Design and simulation of direct torque control of induction motors using VHSIC Hardware Description Language (VHDL)." Scientific Research and Essays 12, no. 11 (2017): 103–12. http://dx.doi.org/10.5897/sre2017.6501.

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Dissertations / Theses on the topic "VHSIC Hardware Description Language (VHDL)"

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Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

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Read, Simon. "Formal methods for VLSI design." Thesis, University of Manchester, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239786.

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Shah, Sandeep R. "A framework for synthesis from VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-03022010-020143/.

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Wright, Philip A. "Rapid development of VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-11102009-020056/.

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Dailey, David M. "Integration of VHDL simulation and test verification into a Process Model Graph design environment." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-11242009-020247/.

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Sama, Anil. "Behavior modeling of RF systems with VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-10102009-020211/.

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Van, Tassel John Peter. "Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistant." Thesis, University of Cambridge, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.308190.

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Ardeishar, Raghu. "Automatic verification of VHDL models." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/.

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Rao, Sanat R. "A hierarchical approach to effective test generation for VHDL behavioral models." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-08042009-040513/.

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Manek, Meenakshi. "Natural language interface to a VHDL modeling tool." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-06232009-063212/.

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Books on the topic "VHSIC Hardware Description Language (VHDL)"

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Computer Systems Laboratory (U.S.), ed. VHSIC hardware description language (VHDL). U.S. Dept. of Commerce, Technology Administration, National Institute of Standards and Technology, Computer Systems Laboratory, 1995.

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Center, Langley Research, ed. Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits. National Aeronautics and Space Administration, Langley Research Center, 1995.

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Center, Langley Research, ed. Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits. National Aeronautics and Space Administration, Langley Research Center, 1995.

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Pellerin, David. VHDL made easy! Prentice Hall, 1997.

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Coelho, David R. The VHDL handbook. Kluwer Academic Publishers, 1989.

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Jean-Michel, Bergé, ed. VHDL '92. Kluwer Academic Publishers, 1993.

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IEEE Computer Society. Design Automation Standards Subcommittee., IEEE Standards Coordinating Committee 20. Automatic Test Program Generation Subcommittee., Institute of Electrical and Electronics Engineers., IEEE Standards Board, and IEEE Standards Association, eds. IEEE standard VHDL language reference manual. Institute of Electrical and Electronics Engineers, 2000.

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IEEE Computer Society. Design Automation Standards Subcommittee., Institute of Electrical and Electronics Engineers., IEEE Standards Board, and IEEE Standards Association, eds. IEEE standard VHDL language reference manual. Institute of Electrical and Electronics Engineers, 2002.

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IEEE Computer Society. Design Automation Standards Subcommittee. IEEE standard VHDL language reference manual. Institute of Electrical and Electronics Engineers, 2009.

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10

Joseph, Pick. VHDL techniques, experiments, and caveats. McGraw-Hill, 1996.

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Book chapters on the topic "VHSIC Hardware Description Language (VHDL)"

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Pierre, Laurence. "VHDL: A Hardware Description Language and its Simulation Semantics." In Software Specification Methods. Springer London, 2001. http://dx.doi.org/10.1007/978-1-4471-0701-9_7.

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Navabi, Zainalabedin, and Naghmeh Karimi. "VHDL-AMS Hardware Description Language." In The VLSI Handbook, Second Edition. CRC Press, 2006. http://dx.doi.org/10.1201/9781420005967.ch91.

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Oczko, Andreas, and Christel Oczko. "Putting Different Simulation Models Together – The Simulation Configuration Language VHDL/S." In Computer Hardware Description Languages and their Applications. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-444-89208-9.50011-9.

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El Oualkadi, Ahmed. "S-? Fractional-N Phase-Locked Loop Design Using HDL and Transistor-Level Models for Wireless Communications." In Advances in Wireless Technologies and Telecommunication. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-4666-0083-6.ch005.

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This chapter presents a systematic design of a S-? fractional-N Phase-Locked Loop based on hardware description language behavioral modeling. The proposed design consists of describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The description language models of critical PLL blocks have been described in VHDL-AMS, which is an IEEE standard, to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the overall system performances. The obtained results are compared w

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Yahya, Abid, Farid Ghani, R. Badlishah Ahmad, et al. "Development of an Efficient and Secure Mobile Communication System with New Future Directions." In Handbook of Research on Computational Science and Engineering. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-61350-116-0.ch010.

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This chapter presents performance of a new technique for constructing Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) encrypted codes based on a row division method. The new QC-LDPC encrypted codes are flexible in terms of large girth, multiple code rates, and large block lengths. In the proposed algorithm, the restructuring of the interconnections is developed by splitting the rows into subrows. This row division reduces the load on the processing node and ultimately reduces the hardware complexity. In this method of encrypted code construction, rows are used to form a distance graph. They ar

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Schmid Moritz, Hannig Frank, Tanase Alexandru, and Teich Jürgen. "High-Level Synthesis Revised." In Advances in Parallel Computing. IOS Press, 2014. https://doi.org/10.3233/978-1-61499-381-0-497.

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The continuous progress in semiconductor technology allows for more and more complex processor architectures. The downside of these technological advances is that computing has already hit a power wall and clock frequencies can barely be increased. In order to scale computing performance in the future, systems' energy efficiency and the degree of parallelism have to be significantly improved. The design of heterogeneous hardware with different specialized resources seems to be a promising solution. When highest performance (throughput, short latencies) and energy efficiency are important, as a

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Jain, Dr Arpit. "CONCLUSION & FUTURESCOPE." In Network on Chip (NoC) Implementation for 3-D Network Topological Structure in HDL Environment. Pink Petals Publication Pvt Ltd, 2023. http://dx.doi.org/10.70034/ppp/bk/noc.7.

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The solution for the multiprocessor system architecture is Application specific Network on Chip (NoC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NoC can be beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. Network on chip (NoC) architecture is an approach to develop large and complex systems on a single chip. NoC is the network version of the MPSoC. A NoC can be structu

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Jain, Dr Arpit. "Bibliography." In Network on Chip (NoC) Implementation for 3-D Network Topological Structure in HDL Environment. Pink Petals Publication Pvt Ltd, 2023. http://dx.doi.org/10.70034/ppp/bk/noc.8.

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The solution for the multiprocessor system architecture is Application specific Network on Chip (NoC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NoC can be beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. Network on chip (NoC) architecture is an approach to develop large and complex systems on a single chip. NoC is the network version of the MPSoC. A NoC can be structu

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Jain, Dr Arpit. "Methodology and Implementation." In Network on Chip (NoC) Implementation for 3-D Network Topological Structure in HDL Environment. Pink Petals Publication Pvt Ltd, 2023. http://dx.doi.org/10.70034/ppp/bk/noc.5.

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The solution for the multiprocessor system architecture is Application specific Network on Chip (NoC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NoC can be beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. Network on chip (NoC) architecture is an approach to develop large and complex systems on a single chip. NoC is the network version of the MPSoC. A NoC can be structu

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Jain, Dr Arpit. "INTRODUCTION." In Network on Chip (NoC) Implementation for 3-D Network Topological Structure in HDL Environment. Pink Petals Publication Pvt Ltd, 2023. http://dx.doi.org/10.70034/ppp/bk/noc.1.

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The solution for the multiprocessor system architecture is Application specific Network on Chip (NoC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NoC can be beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. Network on chip (NoC) architecture is an approach to develop large and complex systems on a single chip. NoC is the network version of the MPSoC. A NoC can be structu

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Conference papers on the topic "VHSIC Hardware Description Language (VHDL)"

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Kiamilev, F., Dau-Tsuong Lu, J. Fan, S. Esener, and S. H. Lee. "VHDL for simulation of optoelectronic computers." In OSA Annual Meeting. Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.fj7.

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VHSIC Hardware Description Language (VHDL) is a standard language for modelling electronic hardware. To evaluate the application of VHDL to optoelectronic computers, we simulate the programmable optoelectronic multiprocessor (POEM) architecture in VHDL. POEM is an architecture in which processing elements are interconnected with reconfigurable free-space optical interconnections. We use VHDL to simulate the POEM prototype, develop the next-generation POEM system, and design and test new parallel algorithms that exploit unique features of optoelectronic technology. We discuss our experience in

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Gray, F., and James Armstrong. "Reutilization of VHDL testbench and library components (VHSIC Hardware Description Language)." In 10th Computing in Aerospace Conference. American Institute of Aeronautics and Astronautics, 1995. http://dx.doi.org/10.2514/6.1995-1035.

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Yuguo, Sun, and Chen Jin. "Embedded Fault Tree Logic Implementation Based on Complex Programmable Logic Device." In ASME 2005 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/detc2005-84886.

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To meet the requirements of an embedded mechanical fault diagnosis system development, a fault tree implementation and dynamic modification method based on CPLD (Complex Programmable Logic Device) is investigated experimentally. The mechanism of fault tree logic calculation in the CPLD chip is presented. The fault logic tree is modeled by VHDL (VHSIC Hardware Description Language) and logic graphic, respectively. The effects of the bottom events on the logic result are simulated in Max + plus II platform. The fault tree logic is downloaded into the EPM7064SLC44-10 chip by ISP (In System Progra

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Waxman, R., J. H. Aylor, and E. Marschner. "The VHSIC hardware description language (IEEE standard 1076): language features revisited." In COMPCON Spring 88. IEEE, 1988. http://dx.doi.org/10.1109/cmpcon.1988.4880.

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Binns, R. J. "High-level design of analogue circuitry using an analogue hardware description language." In IEE Colloquium on Mixed-Signal AHDL/VHDL Modelling and Synthesis. IEE, 1997. http://dx.doi.org/10.1049/ic:19971118.

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Peixoto, Daniela C., Diógenes Silva Jr., José M. Mata, Claudionor N. Coelho Jr., and Antônio O. Fernandes. "Translation of hardware description languages to structured representation: a tool for digital system analysis." In Simpósio de Arquitetura de Computadores e Processamento de Alto Desempenho. Sociedade Brasileira de Computação, 2001. http://dx.doi.org/10.5753/sbac-pad.2001.22196.

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SDS (System Data Structure), part of a digital synthesis system, is an internal representation that captures data/operation and communication/synchronization aspects from the behavioral specification of a digital system. SDS divides design information into two graphs that describe the data flow behavior and control timing behavior. This representation is useful for synthesis and validation/verification. This paper presents the translation process from the hardware description language VHDL to SDS, basically the transformation of a behavioral specification to a structured representation.

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Hayashi, Victor T., Wilson V. Ruggiero, and Felipe V. de Almeida. "LabEAD AutoTest: Online Tests of Hardware Designs." In Simpósio Brasileiro de Segurança da Informação e de Sistemas Computacionais. Sociedade Brasileira de Computação - SBC, 2022. http://dx.doi.org/10.5753/sbseg_estendido.2022.227007.

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The outsourcing of hardware production to third-party foundries (often overseas) for cost reduction presents additional challenges to the security of hardware devices. If Hardware Trojans are added to hardware devices during the fabrication phase, design-time approaches are not enough. LabEAD AutoTest is an open-source tool useful to perform automated tests in a hardware design in runtime. It is based on the MQTT protocol, the remote lab LabEAD and Python Notebook. An example of a glitch in an adder described in the VHDL Hardware Description Language was used to show the soundness of the propo

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Ristić, Petar. "Enigma Machine on an FPGA Board." In 17th Student Project Conference. University of Nis, Faculty of Electronic Engineering, 2024. https://doi.org/10.46793/ieeestec17.283r.

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This paper details the functional realisation of the Enigma machine, based on the model Enigma I, first introduced in 1930 on an FPGA(Field-Programmable Gate Array) using VHDL as the hardware description language of choice. The hardware of choice for this paper was Altera Cyclone V. The paper demonstrates ability of digital technology to emulate old encryption techniques.

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Wenzl, Matthias, Peter Roessler, and Andreas Puhm. "Checking Application Level Properties Using Assertion Synthesis." In ASME 2019 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/detc2019-97950.

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Abstract This work presents a proof-of-concept of a new approach on automatic generation of digital hardware that is able to check application-level properties of an embedded system such as a faulty system behavior at runtime. The approach makes use of assertion-based verification setups that today are very common in the area of digital hardware design with, however, the sole focus on logic simulation. Thus, a PSL-to-VHDL compiler is introduced that generates VHDL (Very High Speed Integrated Circuit Description Language) code out of PSL (Property Specification Language) assertions which can be

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Reports on the topic "VHSIC Hardware Description Language (VHDL)"

1

Aylor, James, Robert Klenke, Ron Waxman, Paul Menchini, Jack Stinson, and Bill Anderson. VHSIC Hardware Description Language (VHDL) 200X Requirements Report/Survey. Defense Technical Information Center, 1999. http://dx.doi.org/10.21236/ada406178.

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Chung, Moon Jung. Parallel Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) Simulation for Performance Modeling. Defense Technical Information Center, 1999. http://dx.doi.org/10.21236/ada372678.

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Mills, Michael T. Proposed Object Oriented Programming (OOP) Enhancements to the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada274004.

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Mills, Michael T. A Key Element Toward Concurrent Engineering of Hardware and Software: Binding Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) with Ada 95. Defense Technical Information Center, 1994. http://dx.doi.org/10.21236/ada294469.

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Federal Information Processing Standards Publication: VHSIC hardware description language (VHDL). National Institute of Standards and Technology, 1995. http://dx.doi.org/10.6028/nist.fips.172-1-1995.

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