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Journal articles on the topic 'VHSIC Hardware Description Language (VHDL)'

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Published: 3 June 2025

Last updated: 31 July 2025

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1

Sciuto, D. "VHDL( VHSIC Hardware Description Language)." Journal of Systems Architecture 42, no. 2 (1996): 95–96. http://dx.doi.org/10.1016/1383-7621(96)00015-x.

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Mahmudi, Ali, Sentot Achmadi, and Michael. "Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes." MATEC Web of Conferences 164 (2018): 01003. http://dx.doi.org/10.1051/matecconf/201816401003.

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In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained.

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Patil, Archana. "Design and Simulation of Clock Divider using VHDL." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 05 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem33837.

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This paper presents the diesign and simulation of clock divider circuit using VHDL(VHSIC Hardware Description Language) on an FPGA(Field Programmable Gate Array). The clock divider circuit is a fundamental component in digital system for generating lower frequency clocks from a higher frequency reference clock. The paper starts up with simple divider where the clock is divided by even numbers, odd numbers and then later expands it into non- integer dividers. Keywords:- clock divider, D flipflop, FPGA

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Shetty, Mamtha. "Design of BPSK Modulator Using VHDL." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, no. 12 (2014): 5247–52. http://dx.doi.org/10.24297/ijct.v13i12.5276.

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Binary Phase Shift Keying represents the simulation results of binary digital modulation schemes. Here for BASK and BPSK modulation techniques use FPGA algorithm. If multiplier block is used for multiplication bit stream with carrier signal, used time will rises. In addition using multiplier block obtained simulation results were analyzed and compared to other simulation results. Source consumptions of FPGA-based BASK modulation technique and BPSK modulation technique were compared. Also, for different modulation algorithm, source consumptions of BASK and BPSK modulation technique were analyze

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NUHA, MUHAMMAD ULIN, HARI ARIEF DHARMAWAN, and SETYAWAN PURNOMO SAKTI. "Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10." ELKOMIKA: Jurnal Teknik Energi Elektrik, Teknik Telekomunikasi, & Teknik Elektronika 10, no. 1 (2022): 16. http://dx.doi.org/10.26760/elkomika.v10i1.16.

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ABSTRAKDesain arsitektur ADC (Analog to Digital Converter) multi kanal simultan pada perangkat kontroller dapat mengurangi jumlah intruksi (task) program yang harus dijalankan oleh mikroprosessor dan dapat digunakan untuk membentuk pengukuran simultan. Paper ini memaparkan desain ADC SAR (Successive Approximation Register) 10-bit dua kanal simultan menggunakan Board FPGA (Field Programmable Gate Array) Altera DE10. FPGA dikonfigurasi untuk difungsikan sebagai sirkuit logika SAR dua kanal menggunakan bahasa VHDL (VHSIC-Very High Speed Integrated Circuit Hardware Description Language). Hasil pen

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Ameur, Noura Ben, Nouri Masmoudi та Mourad Loulou. "FPGA-Based Design Δ–Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit". Journal of Circuits, Systems and Computers 24, № 03 (2015): 1550037. http://dx.doi.org/10.1142/s0218126615500371.

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This paper, focus on synthesis design of a Δ–Σ digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio D

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Pavani, Ms K. "Fault Diagnosis and Redundant Technique for 24 Hours Clock Design Using VHDL." International Journal for Research in Applied Science and Engineering Technology 13, no. 7 (2025): 17–21. https://doi.org/10.22214/ijraset.2025.72917.

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In digital systems, precise timekeeping and fault tolerance are essential, especially in mission-critical applications. This project presents the design and implementation of a 24-hour digital clock using VHDL (VHSIC Hardware Description Language) with integrated fault diagnosis and redundancy techniques. The primary objective is to ensure the accurate display of time and the continuous operation of the clock even in the presence of faults. A redundant architecture is employed to provide backup operations in case of component failure, and diagnostic logic is incorporated to detect and isolate

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Montiel-Ross, Oscar, Jorge Quiñones, and Roberto Sepúlveda. "Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors." Advances in Fuzzy Systems 2012 (2012): 1–11. http://dx.doi.org/10.1155/2012/475894.

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This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy P

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Chou, Hsin-Hung, Ying-Shieh Kung, Tai-Wei Tsui, and Stone Cheng. "FPGA-BASED MOTION CONTROLLER FOR WAFER-HANDLING ROBOT." Transactions of the Canadian Society for Mechanical Engineering 37, no. 3 (2013): 427–37. http://dx.doi.org/10.1139/tcsme-2013-0032.

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This study applies FPGA (Field Programmable Gate Arrays) technology to implement a motion controller for wafer-handling robot which has three-DOF (Degree of Freedom) motion. The proposed FPGA-based motion controller has two modules. The first module is Nios II processor which is used to realize the motion trajectory computation and the three-axis position/speed controllers. The second module is demonstrated to implement the three-axis current vector controllers by using FPGA hardware, and VHDL (VHSIC Hardware Description Language) is adopted to describe the controller behavior. Therefore, a fu

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Cesar, da Costa, and Oliveira Santin Christian. "Design and simulation of direct torque control of induction motors using VHSIC Hardware Description Language (VHDL)." Scientific Research and Essays 12, no. 11 (2017): 103–12. http://dx.doi.org/10.5897/sre2017.6501.

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Vidya, Sagar Potharaju. "FPGA IMPLEMENTATION OF DIRECT DIGITAL SYNTHESIZERUSING VHDL." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 4, no. 11 (2017): 140–50. https://doi.org/10.5281/zenodo.1067984.

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Signal generators are heavy and large in size and are limited to particular set of analog wave forms,creation of arbitrary wave forms are not possible. The available Digital signal generators nowadays are incapable of creating all type of waveforms and more ever they are not reconfigurable. In this paper I am proposing an efficient method called Direct Digital Synthesis (DDS) to realize all the hardware parts of signal generator called Direct Digital Synthesizer in FPGA using VHSIC Hardware Description Language (VHDL). DDS has many advantages over its analog counterpart and improved phase nois

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Fathli, Mohammad Naqiuddin Fahmi, and Zulkifli Md Yusof. "Implementation Study Of Field Programmable Gate Array (FPGA) And Complex Programmable Logic Device (CPLD) In Collision Avoidance System Using Vhsic Hardware Description Language (VHDL)." MEKATRONIKA 3, no. 1 (2021): 52–60. http://dx.doi.org/10.15282/mekatronika.v3i1.7152.

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A collision avoidance system, also known as a pre-crash system, forward collision warning system, or collision mitigation system, is a sophisticated driver-assistance system that aims to avoid or mitigate the severity of a collision. For this research, collision avoidance system will be fabricating to show that this system can detect avoidance range before apply the braking action to prevent collision. The ultrasonic sensor will be used in this system to detect the avoidance range. In this collision avoidance system, there will be uses of Field Programmable Gate Array (FPGA) and Complex Progra

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SHARMA, SUBHASH KUMAR, SHRI PRAKASH DUBEY, and ANIL KUMAR MISHRA. "Development of Library Components for Floating Point Processor." Journal of Ultra Scientist of Physical Sciences Section A 33, no. 4 (2021): 42–50. http://dx.doi.org/10.22147/jusps-a/330402.

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This paper deals with development of an n-bit binary to decimal conversion, decimal to n bit binary conversion and decimal to IEEE-754 conversion for floating point arithmetic logic unit (FPALU) using VHDL. Normally most of the industries now a days are using either 4-bit conversion of ALU or 8-bit conversions of ALU, so we have generalized this, thus we need not to worry about the bit size of conversion of ALU. It has solved all the problems of 4-bit, 8-bit, 16-bit conversions of ALU’s and so on. Hence, we have utilized VHSIC Hardware Description Language and Xilinx in accomplishing this task

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Rampa, Vittorio. "Design and Implementation of a Low Complexity Multiuser Detector for Hybrid CDMA Systems." Journal of Communications Software and Systems 1, no. 1 (2017): 42. http://dx.doi.org/10.24138/jcomss.v1i1.316.

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In hybrid CDMA systems, multiuser detection (MUD) algorithms are adopted at the base station to reduce both multiple access and inter-symbol interference by exploitingspace-time (ST) signal processing techniques. Linear ST-MUD algorithms solve a linear problem where the system matrix has a block-Toeplitz shape. While exact inversion techniques impose an intolerable computational load, reduced complexity algorithms may be efficiently employed even if they show suboptimal behavior introducing performance degradation and nearfar effects. The block-Fourier MUD algorithm is generally considered the

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Schlaak, Christof, Tzung-Han Juang, and Christophe Dubach. "Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators." ACM Transactions on Architecture and Code Optimization 19, no. 2 (2022): 1–26. http://dx.doi.org/10.1145/3501768.

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Specialized accelerators deliver orders of a magnitude of higher performance than general-purpose processors. The ever-changing nature of modern workloads is pushing the adoption of Field Programmable Gate Arrays (FPGAs) as the substrate of choice. However, FPGAs are hard to program directly using Hardware Description Languages (HDLs). Even modern high-level HDLs, e.g., Spatial and Chisel, still require hardware expertise. This article adopts functional programming concepts to provide a hardware-agnostic higher-level programming abstraction. During synthesis, these abstractions are mechanicall

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Kung, Ying-Shieh, Jin-Mu Lin, Yu-Jen Chen, and Hsin-Hung Chou. "ModelSim/Simulink Cosimulation and FPGA Realization of a Multiaxis Motion Controller." Mathematical Problems in Engineering 2015 (2015): 1–17. http://dx.doi.org/10.1155/2015/202474.

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This paper is to implement a multiaxis servo controller and a motion trajectory planning within one chip. At first, SoPC (system on a programmable chip) technology which is composed of an Altera FPGA (field programmable gate arrays) chip and an embedded soft-core Nios II processor is taken as the development of a multiaxis motion control IC. The multiaxis motion control IC has two modules. The first module is Nios II processor which realizes the motion trajectory planning by software. It includes the step, circular, window, star, and helical motion trajectory. The second module presents a func

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Kharchenko, Vyacheslav, Oleg Illiashenko, and Vladimir Sklyar. "Invariant-Based Safety Assessment of FPGA Projects: Conception and Technique." Computers 10, no. 10 (2021): 125. http://dx.doi.org/10.3390/computers10100125.

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This paper describes a proposed method and technology of safety assessment of projects based on field programmable gate arrays (FPGA). Safety assessment is based on special invariants, e.g., properties which remain unchanged when a specified transformation is applied. A classification and examples of FPGA project invariants are provided. In the paper, two types of invariants are described. The first type of invariants used for such assessment are those which are versatile since they reflect the unchanged properties of FPGA projects, hardware description languages, etc. These invariants can be

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Kharchenko, Vyacheslav, Oleg Illiashenko, and Vladimir Sklyr. "Invariant-Based Safety Assessment of FPGA Projects: Conception and Technique." Computers 10, no. 125 (2021): 19. https://doi.org/10.3390/computers10100125.

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This paper describes a proposed method and technology of safety assessment of projects based on field programmable gate arrays (FPGA). Safety assessment is based on special invariants, e.g., properties which remain unchanged when a specified transformation is applied. A classification and examples of FPGA project invariants are provided. In the paper, two types of invariants are described. The first type of invariants used for such assessment are those which are versatile since they reflect the unchanged properties of FPGA projects, hardware description languages, etc. These invariants can be

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19

Ferreira, Diogo, Filipe Moutinho, João P. Matos-Carvalho, Magno Guedes, and Pedro Deusdado. "Generic FPGA Pre-Processing Image Library for Industrial Vision Systems." Sensors 24, no. 18 (2024): 6101. http://dx.doi.org/10.3390/s24186101.

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Currently, there is a demand for an increase in the diversity and quality of new products reaching the consumer market. This fact imposes new challenges for different industrial sectors, including processes that integrate machine vision. Hardware acceleration and improvements in processing efficiency are becoming crucial for vision-based algorithms to follow the complexity growth of future industrial systems. This article presents a generic library of pre-processing filters for execution in field-programmable gate arrays (FPGAs) to reduce the overall image processing time in vision systems. An

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Saleh, Adham Hadi, Hayder Khaleel AL-Qaysi, Khalid Awaad Humood, and Tahreer Mahmood. "Design of CRC circuit for 5G system using VHDL." Bulletin of Electrical Engineering and Informatics 12, no. 4 (2023): 2125–35. http://dx.doi.org/10.11591/beei.v12i4.4598.

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In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low d

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Saleh, Adham Hadi, Hayder Khaleel AL-Qaysi, Khalid Awaad Humood, and Tahreer Mahmood. "Design of CRC circuit for 5G system using VHDL." Bulletin of Electrical Engineering and Informatics 12, no. 4 (2023): 2125–35. http://dx.doi.org/10.11591/eei.v12i4.4598.

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In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low d

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22

Chou, Hsin Hung, Ying Shieh Kung, Tai Wei Tsui, and Stone Cheng. "Realization of a Motion Control System for Wafer-Handling Robot Using SoPC Technology." Applied Mechanics and Materials 284-287 (January 2013): 1909–13. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.1909.

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The novel FPGA (Field Programmable Gate Arrays) can embed a processor to be an SoPC (System-on-a-Programmable-Chip) environment which allows user to design the applications by mixing hardware and software. Therefore, a motion control system of wafer-handling robot based on the SoPC technology is presented in this paper. In FPGA, it is consists of two modules. The first module is Nios II processor which is used to realize the motion trajectory planning and three-axis position/speed controllers by software. The program developed in Nios II processor uses C language. The second module is presente

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23

Zemmouri, Abdelkarim, Anass Barodi, Hamad Dahou, et al. "A microsystem design for controlling a DC motor by pulse width modulation using MicroBlaze soft-core." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1437. http://dx.doi.org/10.11591/ijece.v13i2.pp1437-1448.

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This paper proposes a microsystem based on the field programmable gate arrays (FPGA) electronic board. The preliminary objective is to manipulate a programming language to achieve a control part capable of controlling the speed of electric actuators, such as direct current (DC) motors. The method proposed in this work is to control the speed of the DC motor by a purely embedded architecture within the FPGA in order to reduce the space occupied by the circuit to a minimum and to ensure the reliability of the system. The implementation of this system allows the embedded MicroBlaze processor to b

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Abdelkarim, Zemmouri, Barodi Anass, Dahou Hamad, et al. "A microsystem design for controlling a DC motor by pulse width modulation using MicroBlaze soft-core." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1437–48. https://doi.org/10.11591/ijece.v13i2.pp1437-1448.

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This paper proposes a microsystem based on the field programmable gate arrays (FPGA) electronic board. The preliminary objective is to manipulate a programming language to achieve a control part capable of controlling the speed of electric actuators, such as direct current (DC) motors. The method proposed in this work is to control the speed of the DC motor by a purely embedded architecture within the FPGA in order to reduce the space occupied by the circuit to a minimum and to ensure the reliability of the system. The implementation of this system allows the embedded MicroBlaze processor to b

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25

Zamiri, Elyas, Alberto Sanchez, Marina Yushkova, Maria Sofia Martínez-García, and Angel de Castro. "Comparison of Different Design Alternatives for Hardware-in-the-Loop of Power Converters." Electronics 10, no. 8 (2021): 926. http://dx.doi.org/10.3390/electronics10080926.

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This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods

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Ameur, Noura Ben. "A Low-Phase Noise ADPLL Based on a PRBS-Dithered DDS Enhancement Circuit." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750076. http://dx.doi.org/10.1142/s0218126617500761.

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This paper aims to design an all-digital phase-locked loop (ADPLL) intended for professional digital audio data conversion applications. The method used for designing is based on an analogy between analog PLL and ADPLL. Managing a low-jitter effect, a comparative study between discrete voltage-controlled oscillator (DVCO) and direct digital synthesis (DDS) based on a pseudorandom binary sequence (PRBS) generator is performed. The features of the design in this work are high-precision and low harmonic distortion DDS which is combined with ADPLL. For model-based design validation, a rapid regist

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27

El-Medany, Wael, Alauddin Al-Omary, Riyadh Al-Hakim, and Taher Homeed. "Reconfigurable SRTM System for Road Traffic in Kingdom of Bahrain." Transport and Telecommunication Journal 17, no. 4 (2016): 298–306. http://dx.doi.org/10.1515/ttj-2016-0026.

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Abstract This paper presents reconfigurable hardware architecture for smart road traffic system based on Field Programmable Gate Array (FPGA). The design can be reconfigured for different timing of the traffic signals according to the received and collected data read by the different sensors on the road; the design has been described using VHDL (VHSIC Hardware Description Language). The SRTM (Smart Road Traffic Management) System has some more features that help passenger to avoid traffic jamming by sending the collected information through web/mobile applications to find the best road between

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28

Motupalle, Haritha, and Syed Jahangir Badashah. "A Novel VLSI Architecture for SPHIT Encoder." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 10, no. 4 (2013): 1522–30. http://dx.doi.org/10.24297/ijct.v10i4.3252.

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In this Paper we propose a highly scalable image compression scheme based on the set partitioning in hierarchical trees (SPIHT) algorithm. Our algorithm called highly scalable SPIHT (HS-SPIHT), supports spatial and SNR scalability and provides a bit stream that can be easily adapted (reordered) to given bandwidth and resolution requirements by a simple transcoder (parser). The HS-SPIHT algorithm adds the spatial scalability feature without sacrificing the SNR embeddedness property as found in the original SPIHT bit stream. HS-SPIHT finds applications in progressive Web browsing, flexible image

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29

Assaad, El Makhloufi, Chekroun Nisrine, Tagmouti Noha, El Adib Samir, and Raissouni Naoufal. "Improvements in space radiation-tolerant FPGA implementation of land surface temperature-split window algorithm." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 5 (2021): 3844–54. https://doi.org/10.11591/ijece.v11i5.pp3844-3854.

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The trend in satellite remote sensing assignments has continuously been concerning using hardware devices with more flexibility, smaller size, and higher computational power. Therefore, field programmable gate arrays (FPGA) technology is often used by the developers of the scientific community and equipment for carrying out different satellite remote sensing algorithms. This article explains hardware implementation of land surface temperature split window (LST-SW) algorithm based on the FPGA. To get a high-speed process and real-time application, VHSIC hardware description language (VHDL) was

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30

Mylonas, Eleftherios, Nikolaos Tzanis, Michael Birbas, and Alexios Birbas. "An Automatic Design Framework for Real-Time Power System Simulators Supporting Smart Grid Applications." Electronics 9, no. 2 (2020): 299. http://dx.doi.org/10.3390/electronics9020299.

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Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for r

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31

Shinde, Vinayak Vikram, Sheetal Umesh Bhandari, Deepti Snehal Khurge, Satyashil Dasharath Nagarale, and Ujwal Ramesh Shirode. "A custom reduced instruction set computer-V based architecture for real-time electrocardiogram feature extraction." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 2 (2025): 412. https://doi.org/10.11591/ijres.v14.i2.pp412-427.

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<p>The growing demand for energy-efficient and real-time biomedical signal processing in wearable devices has necessitated the development of application-specific and reconfigurable embedded hardware architectures. This paper presents the register transfer level (RTL) design and simulation of a custom reduced instruction set computer-V (RISC-V) based hardware architecture tailored for real-time electrocardiogram (ECG) feature extraction, focusing on R-peak detection and heart rate (HR) calculation. The proposed system combines ECG-specific functional blocks including a specialized ECG ar

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32

Batista, Edson A., Moacyr A. G. de Brito, João C. Siqueira, et al. "A Multifunctional Smart Meter Using ANN-PSO Flux Estimation and Harmonic Active Compensation with Fuzzy Voltage Regulation." Sensors 21, no. 12 (2021): 4154. http://dx.doi.org/10.3390/s21124154.

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This paper aims to present the analysis and development of a complete electronic smart meter that is able to perform four-quadrant measurements, act as a three-phase shunt active power filter (APF), and control three-phase induction motors by stator flux estimation. A transmission control protocol together with Internet protocol (TCP/IP) communication protocol for the remote access of measurement data is embedded into the application to securely transmit reliable information. An artificial neural network trained with particle swarm optimization is used for stator flux estimation, and a fuzzy l

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33

El Makhloufi, Assaad, Nisrine Chekroun, Noha Tagmouti, Samir El Adib, and Naoufal Raissouni. "Improvements in space radiation-tolerant FPGA implementation of land surface temperature-split window algorithm." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 5 (2021): 3844. http://dx.doi.org/10.11591/ijece.v11i5.pp3844-3854.

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The trend in satellite remote sensing assignments has continuously been concerning using hardware devices with more flexibility, smaller size, and higher computational power. Therefore, field programmable gate arrays (FPGA) technology is often used by the developers of the scientific community and equipment for carrying out different satellite remote sensing algorithms. This article explains hardware implementation of land surface temperature split window (LST-SW) algorithm based on the FPGA. To get a high-speed process and real-time application, VHSIC hardware description language (VHDL) was

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34

Zenkouar, Fatima Zahrae, Mustapha El Alaoui, and Said Najah. "GF(q) LDPC encoder and decoder FPGA implementation using group shuffled belief propagation algorithm." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 3 (2022): 2184. http://dx.doi.org/10.11591/ijece.v12i3.pp2184-2193.

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This paper presents field programmable gate array (FPGA) exercises of the GF(q) low-density parity-check (LDPC) encoder and interpreter utilizing the group shuffled belief propagation (GSBP) algorithm are presented in this study. For small blocks, non-dual LDPC codes have been shown to have a greater error correction rate than dual codes. The reduction behavior of non-binary LDPC codes over GF (16) (also known as GF(q)-LDPC codes) over the additive white Gaussian noise (AWGN) channel has been demonstrated to be close to the Shannon limit and employs a short block length (N=600 bits). At the sa

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Assad, Fatimazahraa, Mohamed Fettach, Fadwa El Otmani, and Abderrahim Tragha. "High-performance FPGA implementation of the secure hash algorithm 3 for single and multi-message processing." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 2 (2022): 1324. http://dx.doi.org/10.11591/ijece.v12i2.pp1324-1333.

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<span>The secure hash function has become the default choice for information security, especially in applications that require data storing or manipulation. Consequently, optimized implementations of these functions in terms of Throughput or Area are in high demand. In this work we propose a new conception of the secure hash algorithm 3 (SHA-3), which aim to increase the performance of this function by using pipelining, four types of pipelining are proposed two, three, four, and six pipelining stages. This approach allows us to design data paths of SHA-3 with higher Throughput and higher

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Fatima, Zahrae Zenkouar, El Alaou Mustapha, and Najah Said. "GF(q) LDPC encoder and decoder FPGA implementation using group shuffled belief propagation algorithm." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 3 (2022): 2184–93. https://doi.org/10.11591/ijece.v12i3.pp2184-2193.

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This paper presents field programmable gate array (FPGA) exercises of the GF(q) low-density parity-check (LDPC) encoder and interpreter utilizing the group shuffled belief propagation (GSBP) algorithm are presented in this study. For small blocks, non-dual LDPC codes have been shown to have a greater error correction rate than dual codes. The reduction behavior of non-binary LDPC codes over GF (16) (also known as GF(q)-LDPC codes) over the additive white Gaussian noise (AWGN) channel has been demonstrated to be close to the Shannon limit and employs a short block length (N=600 bits). At the sa

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Fatimazahraa, Assad, Fettach Mohamed, El Otmani Fadwa, and Tragha Abderrahim. "High-performance FPGA implementation of the secure hash algorithm 3 for single and multi-message processing." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 2 (2022): 1324–33. https://doi.org/10.11591/ijece.v12i2.pp1324-1333.

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The secure hash function has become the default choice for information security, especially in applications that require data storing or manipulation. Consequently, optimized implementations of these functions in terms of Throughput or Area are in high demand. In this work we propose a new conception of the secure hash algorithm 3 (SHA-3), which aim to increase the performance of this function by using pipelining, four types of pipelining are proposed two, three, four, and six pipelining stages. This approach allows us to design data paths of SHA-3 with higher Throughput and higher clock frequ

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Mayer, Kayol Soares, Candice Müller, Fernando Cesar Comparsi de Castro, and Maria Cristina Felippetto de Castro. "A New CPFSK Demodulation Approach for Software Defined Radio." Journal of Circuits, Systems and Computers 28, no. 14 (2019): 1950243. http://dx.doi.org/10.1142/s0218126619502438.

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This paper proposes a new coherent Frequency-Shift Keying (FSK) demodulation technique for software defined radio platform, based on a new Digital Phase Locked Loop (DPLL) architecture. The proposed DPLL addresses the frequency dependence on classic DPLL architectures found in the literature. In classical approaches, the loop filter constants are dependent on the frequency level of the FSK transmitted symbols. The proposed approach applies a simpler feedback loop, with a single integrator and a phase detector architecture based on the small-angle approximation [Formula: see text], which result

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Naji, Baligh, Chokri Abdelmoula, and Mohamed Masmoudi. "A Real Time Algorithm for Versatile Mode Parking System and Its Implementation on FPGA Board." Applied Sciences 12, no. 2 (2022): 655. http://dx.doi.org/10.3390/app12020655.

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This paper presents the design and development of a technique for an Autonomous and Versatile mode Parking System (AVPS) that combines a various number of parking modes. The proposed approach is different from that of many developed parking systems. Previous research has focused on choosing only a parking lot starting from two parking modes (which are parallel and perpendicular). This research aims at developing a parking system that automatically chooses a parking lot starting from four parking modes. The automatic AVPS was proposed for the car-parking control problem, and could be potentiall

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García-Grimaldo, Claudio, Ciro Fabián Bermudez-Marquez, Esteban Tlelo-Cuautle, and Eric Campos-Cantón. "FPGA Implementation of a Chaotic Map with No Fixed Point." Electronics 12, no. 2 (2023): 444. http://dx.doi.org/10.3390/electronics12020444.

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The employment of chaotic maps in a variety of applications such as cryptosecurity, image encryption schemes, communication schemes, and secure communication has been made possible thanks to their properties of high levels of complexity, ergodicity, and high sensitivity to the initial conditions, mainly. Of considerable interest is the implementation of these dynamical systems in electronic devices such as field programmable gate arrays (FPGAs) with the intention of experimentally reproducing their dynamics, leading to exploiting their chaotic properties in real phenomena. In this work, the im

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Ismail, Negabi, Ait El Asri Smail, El Adib Samir, and Raissouni Naoufal. "Convolutional neural network based key generation for security of data through encryption with advanced encryption standard." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 3 (2023): 2589–99. https://doi.org/10.11591/ijece.v13i3.pp2589-2599.

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Machine learning techniques, especially deep learning, are playing an increasingly important role in our lives. Deep learning uses different models to extract information from the data. They have already had a huge impact in areas such as health (i.e., cancer diagnosis), self-driving cars, speech recognition, and data encryption. Recently, deep learning models, including convolutional neural networks (CNN), have been proven to be more effective in the security field. Moreover, the National Institute of Standards and Technology (NIST) recommends the advanced encryption standard (AES) algorithm

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Negabi, Ismail, Smail Ait El Asri, Samir El Adib, and Naoufal Raissouni. "Convolutional neural network based key generation for security of data through encryption with advanced encryption standard." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 3 (2023): 2589. http://dx.doi.org/10.11591/ijece.v13i3.pp2589-2599.

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Machine learning techniques, especially deep learning, are playing an increasingly important role in our lives. Deep learning uses different models to extract information from the data. They have already had a huge impact in areas such as health (i.e., cancer diagnosis), self-driving cars, speech recognition, and data encryption. Recently, deep learning models, including convolutional neural networks (CNN), have been proven to be more effective in the security field. Moreover, the National Institute of Standards and Technology (NIST) recommends the advanced encryption standard (AES) algorithm

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Hong, Eonpyo, Kang-A. Choi, and Jhihoon Joo. "Efficient Two-Stage Max-Pooling Engines for an FPGA-Based Convolutional Neural Network." Electronics 12, no. 19 (2023): 4043. http://dx.doi.org/10.3390/electronics12194043.

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This paper proposes two max-pooling engines, named the RTB-MAXP engine and the CMB-MAXP engine, with a scalable window size parameter for FPGA-based convolutional neural network (CNN) implementation. The max-pooling operation for the CNN can be decomposed into two stages, i.e., a horizontal axis max-pooling operation and a vertical axis max-pooling operation. These two one-dimensional max-pooling operations are performed by tracking the rank of the values within the window in the RTB-MAXP engine and cascading the maximum operations of the values in the CMB-MAXP engine. Both the RTB-MAXP engine

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Shahdad, Lipsett, Marschner, Sheehan, and Cohen. "VHSIC Hardware Description Language." Computer 18, no. 2 (1985): 94–103. http://dx.doi.org/10.1109/mc.1985.1662802.

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Tezak, Nikolas, Armand Niederberger, Dmitri S. Pavlichin, Gopal Sarma, and Hideo Mabuchi. "Specification of photonic circuits using quantum hardware description language." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1979 (2012): 5270–90. http://dx.doi.org/10.1098/rsta.2011.0526.

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Following the simple observation that the interconnection of a set of quantum optical input–output devices can be specified using structural mode VHSIC hardware description language, we demonstrate a computer-aided schematic capture workflow for modelling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations of motion, illustrate our approach using simple examples based on linear and cavity-nonlinear optical components, and demonstrate a computational approach to hierarchical model reduction.

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Dickinson, Brian. "VHDL '92: The new features of the VHDL hardware description language." Microprocessors and Microsystems 19, no. 2 (1995): 106–7. http://dx.doi.org/10.1016/0141-9331(95)90002-0.

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Doligalski, Michał, and Marian Adamski. "Hierarchical Configurable Petri Net Modeling in VHDL." International Journal of Electronics and Telecommunications 58, no. 4 (2012): 397–402. http://dx.doi.org/10.2478/v10177-012-0054-y.

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Abstract The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dual model is an alternative way for behavioral description of the discrete control process. Dual model consists of two correlated models: UML state machine diagram and hierarchical configurable Petri net (HCfgPN). HCfgPN are Petri nets variant with direct support of exceptions handling mechanism. Logical synthesis of dual model is realized by the description of HCfgPN model by means of hardware description language. The paper presents placesoriented method for HCfgPN description in VHDL l

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Marcus, Lloyde George, and Joseph Brandon. "Development of a control path VHDL code generator for hardware development." i-manager’s Journal on Software Engineering 16, no. 3 (2022): 16. http://dx.doi.org/10.26634/jse.16.3.18660.

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The Very High-Speed Integration Circuit HDL (VHDL) is widely used to implement digital electronic systems. The VHDL language can be difficult to learn, so it is necessary to simplify and speed up the process of implementing digital electronic components through a hardware description with a minimal understanding of the VHDL language. This paper entails the design and development of a Graphical User Interface (GUI) capable of generating VHDL code for ControlPaths using specified state transition tables and state diagrams. This application was created using the Matrix Laboratory (MATLAB). Applic

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Yi, Zhao Xiang, Xiong Mei Zhang, Ning Li, and Xiao Dong Mu. "A Visual Dependency Analysis Method Based on VHDL." Applied Mechanics and Materials 738-739 (March 2015): 582–85. http://dx.doi.org/10.4028/www.scientific.net/amm.738-739.582.

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Modern complex circuits are described in very high speed integrated circuit hardware description language (VHDL) and difficult to verify. This paper proposes a systematic and visual dependency analysis method based on VHDL. The dependency relationships including control dependency, data dependency, signal control dependency and signal data dependency are defined. The entity dependency graph is presented and its generation algorithm, which searches the dependency relationships in hardware processes and between hardware processes, are developed. The experiment of a typical keyboard demonstrates

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Soe, Ei Phyu, Myint Myint Soe, and Htet Htet Yi. "Analysis and Synthesis of Elevator Controller Based On VHSIC Hardware Description Language." International Journal of Scientific and Research Publications (IJSRP) 9, no. 4 (2019): p8806. http://dx.doi.org/10.29322/ijsrp.9.04.2019.p8806.

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