Relevant bibliographies by topics / Virtex-II

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Virtex-II'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Virtex-II"

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Schuck, Christian, Bastian Haetzer, and Jürgen Becker. "Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs." International Journal of Reconfigurable Computing 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/671546.

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Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to support high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in place to generate the desired frequency and to drive the clock networks with different sources, respectively. Currently, almost all designs run at a fixed clock frequency determined statically during design time. Such systems cannot take the full advantage of partial and dynamic self-reconfiguration. Therefore, we introduce a new methodology that allows the implemented hardware to dynamically self-adopt the clock frequency during runtime by reconfiguring the Digital Clock Managers. We also present a method for online speed monitoring which is based on a two-dimensional online routing. The created speed maps of the FPGA area can be used as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given. Further, the tradeoffs for reconfiguration effort using this method are evaluated. Results show the high potential and importance of the distributed dynamic frequency scaling method with little additional overhead.
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Ranganadh, Narayanam, Muni Guravaiah P, and Bindu Tushara D. "Implementation Of Grigoryan FFT For its Performance Case Study Over Cooley-Tukey FFT Using Xilinx Virtex-II Pro, Virtex-5 And Virtex-4 FPGAs." International journal of Multimedia & Its Applications 5, no. 4 (August 31, 2013): 85–94. http://dx.doi.org/10.5121/ijma.2013.5407.

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Hashmi, Imran, Habibullah Jamal, and Tahir Muhammad. "Evaluating FPGA Virtex-II Board using Dynamic Partial Reconfiguration." International Journal of Computer Applications 71, no. 1 (June 26, 2013): 40–45. http://dx.doi.org/10.5120/12326-8559.

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Vasicek, Zdenek, and Lukas Sekanina. "An evolvable hardware system in Xilinx Virtex II Pro FPGA." International Journal of Innovative Computing and Applications 1, no. 1 (2007): 63. http://dx.doi.org/10.1504/ijica.2007.013402.

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Becker, Tobias, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, and Tero Rissa. "Power Characterisation for Fine-Grain Reconfigurable Fabrics." International Journal of Reconfigurable Computing 2010 (2010): 1–9. http://dx.doi.org/10.1155/2010/787405.

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This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009 power benchmarking suite. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using five field-programmable gate arrays (FPGAs) that span a range of process technologies: Xilinx Virtex-II Pro, Spartan-3E, Spartan-3AN, Virtex-5, and Silicon Blue iCE65. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications. The Silicon Blue device demonstrates that performance can be traded off to achieve lower leakage.
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Koga, R., J. George, G. Swift, C. Yui, L. Edmonds, C. Carmichael, T. Langley, P. Murray, K. Lanes, and M. Napier. "Comparison of Xilinx Virtex-II FPGA SEE sensitivities to protons and heavy ions." IEEE Transactions on Nuclear Science 51, no. 5 (October 2004): 2825–33. http://dx.doi.org/10.1109/tns.2004.835057.

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Bernardi, P., L. Sterpone, M. Violante, and M. Portela-Garcia. "Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro's PowerPC 405." IEEE Transactions on Nuclear Science 53, no. 6 (December 2006): 3550–57. http://dx.doi.org/10.1109/tns.2006.886221.

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Tatas, Konstantinos, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, and Stephan Wong. "Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D2-CMP) using FPGAs." Parallel Processing Letters 18, no. 02 (June 2008): 291–306. http://dx.doi.org/10.1142/s0129626408003399.

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This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the non-blocking Data-Driven Multithreading (DDM) model of execution. The DDM model has been evaluated using an execution driven simulator. To validate the simulation results, a 2-node DDM chip multiprocessor has been implemented on a Xilinx Virtex-II Pro FPGA with two PowerPC processors hardwired on the FPGA. Measurements on the hardware prototype show that the TSU can be implemented with a moderate hardware budget. The 2-node multiprocessor has been implemented with less than half of the reconfigurable hardware available on the Xilinx Virtex-II Pro FPGA (45% slices), which corresponds to an ASIC equivalent gate count of 1.9 million gates. Measurements on the prototype showed that the delays incurred by the operation of the TSU can be tolerated.
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Cintra, Renato J., Fábio M. Bayer, Arjuna Madanayake, Uma S. Potluri, and Amila Edirisuriya. "Fast Algorithms and Architectures for 8-Point DST-II/DST-VII Approximations." Journal of Circuits, Systems and Computers 26, no. 03 (November 21, 2016): 1750045. http://dx.doi.org/10.1142/s0218126617500451.

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Multiplier-free fast algorithms are derived and analyzed for realizing the 8-point discrete sine transform of type II and type VII (DST-II and DST-VII) transforms with applications in image and video compression. A new fast algorithm is identified using numerical search methods for approximating DST-VII without employing multipliers. In addition, recently proposed fast algorithms for approximating the 8-point DCT-II are now extended to approximate DST-II. All proposed approximations for DST-II and DST-VII are compared with ideal transforms, and circuit complexity is measured using FPGA-based rapid prototypes on a 90[Formula: see text]nm Xilinx Virtex-4 device. The proposed architectures find applications in emerging video processing standards such as H.265/HEVC.
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Brack, T., U. Wasenmüller, D. Schmidt, and N. Wehn. "Design Space Exploration for Frequency Synchronization of BPSK/QPSK Bursts." Advances in Radio Science 3 (May 13, 2005): 337–41. http://dx.doi.org/10.5194/ars-3-337-2005.

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Abstract. Frequency synchronisation is a vital part of every inner receiver for wireless communication. In this paper we present different implementation alternatives for non data aided frequency estimation of BPSK/QPSK bursts with respect to implementation complexity and communications performance. Results with regard to different quantization levels, varying burstlengths, frequency offsets and modulation indices for different signal to noise ratios are presented. Implementation results are based on XILINX Virtex II Pro FPGA devices.
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Dissertations / Theses on the topic "Virtex-II"

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Steiner, Neil Joseph. "A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/35014.

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Modern FPGAs contain routing resources easily exceeding millions of wires. While mainstream design flows and place-and-route tools make very good use of these routing resources, they do so at the cost of very significant processing time. A well established alternative scheme is to modify or generate configuration bitstreams directly, resulting in more dynamic designs and shorter processing times. This thesis introduces a complete set of alternate wire databases for Xilinx Virtex, Virtex-E, and Virtex-II FPGAs, suitable for standalone use or as an addition to the JBits API. The databases can be used to route or trace through any device in these families, and can generate the necessary bitstream configurations with the help of JBits or an independent bitstream interface.
Master of Science
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Kolář, Jan. "Metody částečné rekonfigurace programovatelných struktur." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217848.

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This master's thesis dissertates of partial reconfiguration methods based on programmable structures. In theoretical part it deals with difference and modular-based method of Xilinx's FPGAs Partial reconfiguration. Options of both reconfiguration techniques were written for Spartan 3, Virtex II, Virtex 4 and Virtex 5 processors. Diference-based method was in practical part tested on Spartan 3E Starter Kit and modular-based on ML501 board. All configuration bitstreams are included on CD. Xilinx Inc. provided all needed software tools such as ISE9.2i and PlanAHEAD.
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Morford, Casey Justin. "BitMaT - Bitstream Manipulation Tool for Xilinx FPGAs." Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/36198.

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With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform different tasks and swap them in and out of designated dynamic regions on an FPGA. However, the current mainstream partial reconfiguration flow provides a limited and inefficient approach that requires a strict set of guidelines to be met. This thesis introduces BitMaT, a tool that provides the low-level bitstream manipulation as a member tool of an alternative, automated, modular partial reconfiguration flow.
Master of Science
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Iqbal, Rashid. "Hardware bidirectional real time motion estimator on a Xilinx Virtex II Pro FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6355.

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This thesis describes the implementation of a real-time, full search, 16x16 bidirectional motion estimation at 24 frames per second with the record performance of 155 Gop/s (1538 ops/pixel) at a high clock rate of 125 MHz. The core of bidirectional motion estimation uses close to 100% FPGA resources with 7 Gbit/s bandwidth to external memory. The architecture allows extremely controlled, macro level floor-planning with parameterized block size, image size, placement coordinates and data words length. The FPGA chip is part of the board that was developed at the Institute of Computer & Communication Networking Engineering, Technical University Braunschweig Germany, in collaboration with Grass Valley Germany in the FlexFilm research project. The goal of the project was to develop hardware and programming methodologies for real-time digital film image processing. Motion estimation core uses FlexWAFE reconfigurable architecture where FPGAs are configured using macro components that consist of weakly programmable address generation units and data stream processing units. Bidirectional motion estimation uses two cores of motion estimation engine (MeEngine) forming main data processing unit for backward and forward motion vectors. The building block of the core of motion estimation is an RPM-macro which represents one processing element and performs 10-bit difference, a comparison, and 19-bit accumulation on the input pixel streams. In order to maximize the throughput between elements, the processing element is replicated and precisely placed side-by-side by using four hierarchal levels, where each level is a very compact entity with its own local control and placement methodology. The achieved speed was further improved by regularly inserting pipeline stages in the processing chain.

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Bernspång, Johan. "Interfacing an external Ethernet MAC/PHY to a MicroBlaze system on a Virtex-II FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2412.

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Due to the development towards more dense programmable devices (FPGAs) it is today possible to fit a complete embedded system including microprocessor, bus architecture, memory, and custom peripherals onto one single reprogrammable chip, it is called a System-on-Chip (SoC). The custom peripherals can be of literally any nature from I/O interfaces to Ethernet Media Access Controllers. The latter core, however, usually consumes a big part of a good sized FPGA. The purpose of this thesis is to explore the possibilities of interfacing an FPGA based Microblaze system to an off-chip Ethernet MAC/PHY. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price. This work includes evaluation of different available Ethernet devices, decision of interface technology, implementation of the interface, testing and verification. Since the ISA interface still is a common interface to Ethernet MAC devices a bus bridge is implemented linking the internal On-Chip Peripheral Bus (OPB) with the ISA bus. Due to delivery delays of the selected Ethernet chip a small on-chip ISA peripheral was constructed to provide a tool for the testing and verification of the bus bridge. The main result of this work is an OPB to ISA bus bridge core. The bridge was determined to work according to specification, and with this report at hand the connection of the Ethernet chip to the system should be quite straightforward.

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Lin, Hsiang-Ling Jamie. "Evaluating hardware/software partitioning and an embedded Linux port of the Virtex-II pro development system." Online access for everyone, 2006. http://www.dissertations.wsu.edu/Thesis/Spring2006/h%5Flin%5F050106.pdf.

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Lee, Barry Roland. "Comparison of logarithmic and floating-point number systems implemented on Xilinx Virtex-II field-programmable gate arrays." Thesis, Cardiff University, 2004. http://orca.cf.ac.uk/55943/.

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The aim of this thesis is to compare the implementation of parameterisable LNS (logarithmic number system) and floating-point high dynamic range number systems on FPGA. The Virtex/Virtex-II range of FPGAs from Xilinx, which are the most popular FPGA technology, are used to implement the designs. The study focuses on using the low level primitives of the technology in an efficient way and so initially the design issues in implementing fixed-point operators are considered. The four basic operations of addition, multiplication, division and square root are considered. Carry- free adders, ripple-carry adders, parallel multipliers and digit recurrence division and square root are discussed. The floating-point operators use the word format and exceptions as described by the IEEE std-754. A dual-path adder implementation is described in detail, as are floating-point multiplier, divider and square root components. Results and comparisons with other works are given. The efficient implementation of function evaluation methods is considered next. An overview of current FPGA methods is given and a new piecewise polynomial implementation using the Taylor series is presented and compared with other designs in the literature. In the next section the LNS word format, accuracy and exceptions are described and two new LNS addition/subtraction function approximations are described. The algorithms for performing multiplication, division and powering in the LNS domain are also described and are compared with other designs in the open literature. Parameterisable conversion algorithms to convert to/from the fixed-point domain from/to the LNS and floating-point domain are described and implementation results given. In the next chapter MATLAB bit-true software models are given that have the exact functionality as the hardware models. The interfaces of the models are given and a serial communication system to perform low speed system tests is described. A comparison of the LNS and floating-point number systems in terms of area and delay is given. Different functions implemented in LNS and floating-point arithmetic are also compared and conclusions are drawn. The results show that when the LNS is implemented with a 6-bit or less characteristic it is superior to floating-point. However, for larger characteristic lengths the floating-point system is more efficient due to the delay and exponential area increase of the LNS addition operator. The LNS is beneficial for larger characteristics than 6-bits only for specialist applications that require a high portion of division, multiplication, square root, powering operations and few additions.
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Fong, Ryan Joseph Lim. "Improving Field-Programmable Gate Array Scaling Through Wire Emulation." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/35086.

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Field-programmable gate arrays (FPGAs) are excellent devices for high-performance computing, system-on-chip realization, and rapid system prototyping. While FPGAs offer flexibility and performance, they continue to lag behind application specific integrated circuit (ASIC) performance and power consumption. As manufacturing technology improves and IC feature size decreases, FPGAs may further lag behind ASICs due to interconnection scalability issues. To improve FPGA scalability, this thesis proposes an architectural enhancement to improve global communications in large FPGAs, where chip-length programmable interconnects are slow. It is expected that this architectural enhancement, based on wire emulation techniques, can reduce chip-length communication latency and routing congestion. A prototype wire emulation system that uses FPGA self-reconfiguration as a non-traditional means of intra-FPGA communication is implemented and verified on a Xilinx Virtex-II XC2V1000 FPGA. Wire emulation benefits and impact to FPGA architecture are examined with quantitative and qualitative analysis.
Master of Science
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Hunter, Jesse Everett III. "A Device-Level FPGA Simulator." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/10041.

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In the realm of FPGAs, many tool vendors offer behaviorally-based simulators aimed at easing the complexity of large FPGA designs. At times, a behaviorally-modeled design does not work in hardware as expected or intended. VTsim, a Virtex-II device simulator, was designed to resolve this and many other design problems by providing a window into the FPGA fabric via a virtual device. VTsim is an event-driven device simulator modeled at the CLB level with multiple clock domain support. Utilizing JBits3 and ADB, VTsim enables simulation and examination of all resources within an FPGA via a virtual device. The only input required by VTsim is a bitstream, which can be generated from any tool suite. The simulator is part of the JHDLBits open-source project, and was designed for rapid response, low memory usage, and ease of interaction.
Master of Science
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Botella, Pedro. "Implementation and Design of a Bit-Error Generator and Logger for Multi-Gigabit Serial Links." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7268.

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Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher

speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer,

this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need

to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors

in a controlled way.

A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been

developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the

hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is

handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links,

independently. This report describes the implementation and the necessary theoretical background for this.

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Book chapters on the topic "Virtex-II"

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Kuzmanov, Georgi, Georgi Gaydadjiev, and Stamatis Vassiliadis. "The Virtex II ProTM MOLEN Processor." In Lecture Notes in Computer Science, 192–202. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-27776-7_21.

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Blodget, B., C. Bobda, M. Huebner, and A. Niyonkuru. "Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs." In Field Programmable Logic and Application, 801–10. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_81.

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Beuchat, Jean-Luc, and Arnaud Tisserand. "Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices." In Lecture Notes in Computer Science, 513–22. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-46117-5_54.

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Plaza, Antonio. "Towards Real-Time Compression of Hyperspectral Images Using Virtex-II FPGAs." In Euro-Par 2007 Parallel Processing, 248–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-74466-5_28.

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Glette, Kyrre, and Jim Torresen. "A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device." In Evolvable Systems: From Biology to Hardware, 66–75. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11549703_7.

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Arul Murugan C. and Banuselvasaraswathy B. "Challenges in FPGA Technology Paradigm for the Implementation of IoT Applications." In Advances in Systems Analysis, Software Engineering, and High Performance Computing, 1–21. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-5225-9806-0.ch001.

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Internet of things (IoT) is a recent technology, and it will become the next generation of internet that connects several physical objects to interact amongst themselves without the assistance of human beings. It plays a significant role in our day-to-day lives and is used in several applications. IoT is a boon to this modern world, but it lacks in security. It cannot protect the user data from assailants, hackers, and vulnerabilities. Field programmable gate arrays (FPGA) helps to achieve all these objectives by incorporating secured end-to-end layer into its architecture. In this chapter, ultralow power and reduced area AES architecture with energy efficient DSE-S box techniques and clock gating for IoT applications are introduced. The proposed AES architecture is implemented over different FPGA families such as Cyclone I, Cyclone II, Virtex 5, and Kintex 7, respectively. From the experimental results, it is observed that the Kintex 7 FPGA kit consumes less power than other FPGA families.
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Conference papers on the topic "Virtex-II"

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Donchev, Blagomir, Georgi Kuzmanov, and Georgi Gaydadjiev. "External Memory Controller for Virtex II Pro." In 2006 International Symposium on System-on-Chip. IEEE, 2006. http://dx.doi.org/10.1109/issoc.2006.322009.

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Rexha, Hergys, and Betim Cico. "Implementing Codesign in Xilinx Virtex II Pro." In 2009 Fourth Balkan Conference in Informatics. IEEE, 2009. http://dx.doi.org/10.1109/bci.2009.28.

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Shang, Li, Alireza S. Kaviani, and Kusuma Bathala. "Dynamic power consumption in Virtex™-II FPGA family." In the 2002 ACM/SIGDA tenth international symposium. New York, New York, USA: ACM Press, 2002. http://dx.doi.org/10.1145/503048.503072.

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Hubner, Michael, Lars Braun, Jurgen Becker, Christopher Claus, and Walter Stechele. "Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs." In IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07). Emerging VLSI Technologies and Architectures. IEEE, 2007. http://dx.doi.org/10.1109/isvlsi.2007.83.

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Zhou, Qingguo, Qi Yao, Chanjuan Li, and Bin Hu. "Port embedded Linux to XUP Virtex-II Pro development board." In 2009 IEEE International Symposium on IT in Medicine & Education (ITME2009). IEEE, 2009. http://dx.doi.org/10.1109/itime.2009.5236439.

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Krasteva, Y., E. La Torre, T. Riesgo, and Didier Joly. "Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems." In 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. http://dx.doi.org/10.1109/fpl.2006.311298.

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Jammoussi, Ameni Yengui, Sameh Fakhfakh Ghribi, and Dorra Sallami Masmoudi. "Implementation of face recognition system in virtex II Pro platform." In 2009 3rd International Conference on Signals, Circuits and Systems (SCS 2009). IEEE, 2009. http://dx.doi.org/10.1109/icscs.2009.5412313.

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Duarte, F., and S. Wong. "Profiling Bluetooth and Linux on the Xilinx Virtex II Pro." In 9th EUROMICRO Conference on Digital System Design (DSD'06). IEEE, 2006. http://dx.doi.org/10.1109/dsd.2006.100.

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Choi, Seonil, Viktor K. Prasanna, and Ju-wook Jang. "Minimizing energy dissipation of matrix multiplication kernel on Virtex-II." In ITCom 2002: The Convergence of Information Technologies and Communications, edited by John Schewel, Philip B. James-Roxby, Herman H. Schmit, and John T. McHenry. SPIE, 2002. http://dx.doi.org/10.1117/12.455487.

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Ranganadh, Narayanam, and Bindu Tushara D. "Performance Evaluations of GRIORYAN FFT and COOLEY-TUKEY FFT onto XILINX VIRTEX-II PRO and VIRTEX-5 FPGAS." In Third International Conference on Computer Science & Information Technology. Academy & Industry Research Collaboration Center (AIRCC), 2013. http://dx.doi.org/10.5121/csit.2013.3637.

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