Journal articles: 'Virtex-II'

1

Schuck, Christian, Bastian Haetzer, and Jürgen Becker. "Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs." International Journal of Reconfigurable Computing 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/671546.

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Xilinx Virtex-II family FPGAs support an advanced low-skew clock distribution network with numerous global clock nets to support high-speed mixed frequency designs. Digital Clock Managers in combination with Global Clock Buffers are already in place to generate the desired frequency and to drive the clock networks with different sources, respectively. Currently, almost all designs run at a fixed clock frequency determined statically during design time. Such systems cannot take the full advantage of partial and dynamic self-reconfiguration. Therefore, we introduce a new methodology that allows the implemented hardware to dynamically self-adopt the clock frequency during runtime by reconfiguring the Digital Clock Managers. We also present a method for online speed monitoring which is based on a two-dimensional online routing. The created speed maps of the FPGA area can be used as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given. Further, the tradeoffs for reconfiguration effort using this method are evaluated. Results show the high potential and importance of the distributed dynamic frequency scaling method with little additional overhead.

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Ranganadh, Narayanam, Muni Guravaiah P, and Bindu Tushara D. "Implementation Of Grigoryan FFT For its Performance Case Study Over Cooley-Tukey FFT Using Xilinx Virtex-II Pro, Virtex-5 And Virtex-4 FPGAs." International journal of Multimedia & Its Applications 5, no. 4 (August 31, 2013): 85–94. http://dx.doi.org/10.5121/ijma.2013.5407.

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Hashmi, Imran, Habibullah Jamal, and Tahir Muhammad. "Evaluating FPGA Virtex-II Board using Dynamic Partial Reconfiguration." International Journal of Computer Applications 71, no. 1 (June 26, 2013): 40–45. http://dx.doi.org/10.5120/12326-8559.

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Vasicek, Zdenek, and Lukas Sekanina. "An evolvable hardware system in Xilinx Virtex II Pro FPGA." International Journal of Innovative Computing and Applications 1, no. 1 (2007): 63. http://dx.doi.org/10.1504/ijica.2007.013402.

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Becker, Tobias, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, and Tero Rissa. "Power Characterisation for Fine-Grain Reconfigurable Fabrics." International Journal of Reconfigurable Computing 2010 (2010): 1–9. http://dx.doi.org/10.1155/2010/787405.

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This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009 power benchmarking suite. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using five field-programmable gate arrays (FPGAs) that span a range of process technologies: Xilinx Virtex-II Pro, Spartan-3E, Spartan-3AN, Virtex-5, and Silicon Blue iCE65. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications. The Silicon Blue device demonstrates that performance can be traded off to achieve lower leakage.

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Koga, R., J. George, G. Swift, C. Yui, L. Edmonds, C. Carmichael, T. Langley, P. Murray, K. Lanes, and M. Napier. "Comparison of Xilinx Virtex-II FPGA SEE sensitivities to protons and heavy ions." IEEE Transactions on Nuclear Science 51, no. 5 (October 2004): 2825–33. http://dx.doi.org/10.1109/tns.2004.835057.

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7

Bernardi, P., L. Sterpone, M. Violante, and M. Portela-Garcia. "Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro's PowerPC 405." IEEE Transactions on Nuclear Science 53, no. 6 (December 2006): 3550–57. http://dx.doi.org/10.1109/tns.2006.886221.

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Tatas, Konstantinos, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, and Stephan Wong. "Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D2-CMP) using FPGAs." Parallel Processing Letters 18, no. 02 (June 2008): 291–306. http://dx.doi.org/10.1142/s0129626408003399.

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This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the non-blocking Data-Driven Multithreading (DDM) model of execution. The DDM model has been evaluated using an execution driven simulator. To validate the simulation results, a 2-node DDM chip multiprocessor has been implemented on a Xilinx Virtex-II Pro FPGA with two PowerPC processors hardwired on the FPGA. Measurements on the hardware prototype show that the TSU can be implemented with a moderate hardware budget. The 2-node multiprocessor has been implemented with less than half of the reconfigurable hardware available on the Xilinx Virtex-II Pro FPGA (45% slices), which corresponds to an ASIC equivalent gate count of 1.9 million gates. Measurements on the prototype showed that the delays incurred by the operation of the TSU can be tolerated.

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Cintra, Renato J., Fábio M. Bayer, Arjuna Madanayake, Uma S. Potluri, and Amila Edirisuriya. "Fast Algorithms and Architectures for 8-Point DST-II/DST-VII Approximations." Journal of Circuits, Systems and Computers 26, no. 03 (November 21, 2016): 1750045. http://dx.doi.org/10.1142/s0218126617500451.

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Multiplier-free fast algorithms are derived and analyzed for realizing the 8-point discrete sine transform of type II and type VII (DST-II and DST-VII) transforms with applications in image and video compression. A new fast algorithm is identified using numerical search methods for approximating DST-VII without employing multipliers. In addition, recently proposed fast algorithms for approximating the 8-point DCT-II are now extended to approximate DST-II. All proposed approximations for DST-II and DST-VII are compared with ideal transforms, and circuit complexity is measured using FPGA-based rapid prototypes on a 90[Formula: see text]nm Xilinx Virtex-4 device. The proposed architectures find applications in emerging video processing standards such as H.265/HEVC.

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10

Brack, T., U. Wasenmüller, D. Schmidt, and N. Wehn. "Design Space Exploration for Frequency Synchronization of BPSK/QPSK Bursts." Advances in Radio Science 3 (May 13, 2005): 337–41. http://dx.doi.org/10.5194/ars-3-337-2005.

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Abstract. Frequency synchronisation is a vital part of every inner receiver for wireless communication. In this paper we present different implementation alternatives for non data aided frequency estimation of BPSK/QPSK bursts with respect to implementation complexity and communications performance. Results with regard to different quantization levels, varying burstlengths, frequency offsets and modulation indices for different signal to noise ratios are presented. Implementation results are based on XILINX Virtex II Pro FPGA devices.

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11

Swift, G. M., S. Rezgui, J. George, C. Carmichael, M. Napier, J. Maksymowicz, J. Moore, A. Lesea, R. Koga, and T. F. Wrobel. "Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)." IEEE Transactions on Nuclear Science 51, no. 6 (December 2004): 3469–74. http://dx.doi.org/10.1109/tns.2004.839190.

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Wang, Lie, and Yi Jie Wang. "Implementation of CRC by Using FPGA in Data Communication." Applied Mechanics and Materials 325-326 (June 2013): 1805–8. http://dx.doi.org/10.4028/www.scientific.net/amm.325-326.1805.

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By introducing the basic principle of ordinary CRC algorithm, the paper develops an algorithm which can be used to analyze data communication structure and construct design process. At the same time, it can be quickly implemented in the data communication process. The algorithm uses Verilog HDL hardware description language to complete all the design on ISE development platform. And it uses Xilinxs development board Virtex-II Pro to achieve the final realization. Compared with traditional methods, the algorithm is simple and intuitive, which reduces computational the delays and saves space. It also benefits hardware implementation.

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13

Bibilo, P. N., Yu Yu Lankevich, and V. I. Romanov. "Logical minimization for combinatorial structure in FPGA." Informatics 18, no. 1 (March 29, 2021): 7–24. http://dx.doi.org/10.37661/1816-0301-2021-18-1-7-24.

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The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA. Programs are designed for shared and separated function minimization in a disjunctive normal form (DNF) class and minimization of multilevel representations of fully defined Boolean functions based on Shannon expansion with finding equal and inverse cofactors. The graphical form of such representations is widely known as binary decision diagrams (BDD). For technological mapping the program of "enlargement" of obtained Shannon expansion formulas was applied in a way that each of them depends on a limited number of k input variables and can be implemented on one LUT-k – a programmable unit of FPGA with k input variables. It is shown that a preliminary logic minimization, which is performed on the domestic programs, allows improving design results of foreign CAD systems such as Leonardo Spectrum (Mentor Graphics), ISE (Integrated System Environment) Design Suite and Vivado (Xilinx). The experiments were performed for FPGA families’ Virtex-II PRO, Virtex-5 and Artix-7 (Xilinx) on standard threads of industrial examples, which define both DNF systems of Boolean functions and systems represented as interconnected logical equations.

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14

Zhang, Lei, Ren Ping Dong, and Ya Ping Yu. "Realization of SMS4 Algorithm Based on Share Memory of the Heterogeneous Multi-Core Password Chip System." Applied Mechanics and Materials 668-669 (October 2014): 1368–73. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.1368.

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In order to meet the rapid demand of the modern cryptographic communication, heterogeneous multi-core password system architecture is set up based on shared memory in Xilinx XUP Virtex-II Pro chip in this paper. Under this architecture, the encryption and decryption of the SMS4 algorithm is realized fastly. Make a contrast with the homogeneous multi-core password system and the heterogeneous one-core password system’s performance in the execution time, throughput and resource utilization of the SMS4 algorithm.The experimental results show that the heterogeneous multi-core password system which based on shared memory has better performance.

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15

Ren, Y. J., J. G. Zhu, X. Y. Yang, and S. H. Ye. "The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor." Journal of Physics: Conference Series 48 (October 1, 2006): 373–78. http://dx.doi.org/10.1088/1742-6596/48/1/070.

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16

Singh, Sanjay, Srinivasa Murali Dunga, AS Mandal, Chandra Shekhar, and Santanu Chaudhury. "FPGA Based Embedded Implementation of Video Summary Generation Scheme in Smart Camera." Advanced Materials Research 403-408 (November 2011): 516–21. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.516.

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In any remote surveillance scenario, smart cameras have to take intelligent decisions to generate summary frames to minimize communication and processing overhead. Video summary generation, in the context of smart camera, is the process of merging the information from multiple frames. A summary generation scheme based on clustering based change detection algorithm has been implemented in our smart camera system for generating frames to deliver requisite information. In this paper we propose an embedded platform based framework for implementing summary generation scheme using HW-SW Co-Design based methodology. The complete system is implemented on Xilinx XUP Virtex-II Pro FPGA board. The overall algorithm is running on PowerPC405 and some of the blocks which are computationally intensive and more frequently called are implemented in hardware using VHDL. The system is designed using Xilinx Embedded Design Kit (EDK).

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17

Schmidt, D., T. Brack, U. Wasenmüller, and N. Wehn. "From algorithm to implementation: a case study on blind carrier synchronization." Advances in Radio Science 4 (September 6, 2006): 313–18. http://dx.doi.org/10.5194/ars-4-313-2006.

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Abstract. Increasing chip complexities demand a higher design productivity. IP cores, which implement commonly needed operations, can help to dramatically shorten development and verification times for new designs. They often allow for a efficient mapping of algorithmic tasks to a hardware architecture. In this paper we present a novel configurable building block for blind carrier synchronization that features combined frequency and phase offset estimation and an alternative modulation removal that improves communication performance compared to state-of-the-art designs. The used design flow exploits the benefits of IP cores for rapid development times while still offering the designer the full range of optimization possibilities for a specific design. It allowed us to do an almost complete design space exploration, assuring a near-optimal solution to the given problem. The implementation platform is a XILINX Virtex II Pro FPGA.

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18

Divakara, S. S., Sudarshan Patilkulkarni, and Cyril Prasanna Raj. "High speed modular systolic array-based DTCWT with parallel processing architecture for 2D image transformation on FPGA." International Journal of Wavelets, Multiresolution and Information Processing 15, no. 05 (August 28, 2017): 1750047. http://dx.doi.org/10.1142/s0219691317500473.

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In this paper, systolic array-based novel architecture for dual-tree complex wavelet transform (DTCWT) computation is designed and implemented on FPGA. The wavelet filter coefficients of DTCWT are quantized and rounded to nearest integer and the loss in rounding and quantization is limited to 0.5[Formula: see text]dB as compared with software implementation. The parallel architecture designed computes row elements simultaneously and pipelined architecture is designed to compute column elements. The proposed architecture is modeled using Verilog and implemented on Xilinx Virtex II FPGA. For 2D implementation, the design operates at a maximum frequency of 156[Formula: see text]MHz and consumes power less than 3[Formula: see text]W. This is the first design with systolic array architecture on FPGA for DTCWT computation operating at frequencies greater than 100[Formula: see text]MHz.

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Foster, Charles C., Patrick M. O'Neill, and Coy K. Kouba. "Monte Carlo Simulation of Proton Upsets in Xilinx Virtex-II FPGA Using a Position Dependent ${\rm Q}_{\rm crit}$ With PROPSET." IEEE Transactions on Nuclear Science 53, no. 6 (December 2006): 3494–501. http://dx.doi.org/10.1109/tns.2006.886233.

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20

Zheng, Hanzhong, Simin Yu, and Xiangqian Xu. "A Systematic Methodology for Multi-Images Encryption and Decryption Based on Single Chaotic System and FPGA Embedded Implementation." Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/698608.

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A systematic methodology is developed for multi-images encryption and decryption and field programmable gate array (FPGA) embedded implementation by using single discrete time chaotic system. To overcome the traditional limitations that a chaotic system can only encrypt or decrypt one image, this paper initiates a new approach to designn-dimensional (n-D) discrete time chaotic controlled systems via some variables anticontrol, which can achieve multipath drive-response synchronization. To that end, the designedn-dimensional discrete time chaotic controlled systems are used for multi-images encryption and decryption. A generalized design principle and the corresponding implementation steps are also given. Based on the FPGA embedded hardware system working platform with XUP Virtex-II type, a chaotic secure communication system for three digital color images encryption and decryption by using a 7D discrete time chaotic system is designed, and the related system design and hardware implementation results are demonstrated, with the related mathematical problems analyzed.

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21

Ammendola, Roberto, Andrea Biagioni, Andrea Ciardiello, Paolo Cretaro, Ottorino Frezza, Gianluca Lamanna, Francesca Lo Cicero, et al. "L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor." EPJ Web of Conferences 245 (2020): 01017. http://dx.doi.org/10.1051/epjconf/202024501017.

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The L0TP+ initiative is aimed at the upgrade of the FPGA-based Level-0 Trigger Processor (L0TP) of the NA62 experiment at CERN for the post-LS2 data taking, which is expected to happen at 100% of design beam intensity, corresponding to about 3.3 × 1012 protons per pulse on the beryllium target used to produce the kaons beam. Although tests performed at the end of 2018 showed a substantial robustness of the L0TP system also at full beam intensity, there are several reasons to motivate such an upgrade: i) avoid FPGA platform obsolescence, ii) make room for improvements in the firmware design leveraging a more capable FPGA device, iii) add new functionalities, iv) support the 4 beam intensity increase foreseen in future experiment upgrades. We singled out the Xilinx Virtex UltraScale+ VCU118 development board as the ideal platform for the project. L0TP+ seamless integration into the current NA62 TDAQ system and exact matching of L0TP functionalities represent the main requirements and focus of the project; nevertheless, the final design will include additional features, such as a PCIe RDMA engine to enable processing on CPU and GPU accelerators, and the partial reconfiguration of trigger firmware starting from a high level language description (C/C++). The latter capability is enabled by modern High Level Synthesis (HLS) tools, but to what extent this methodology can be applied to perform complex tasks in the L0 trigger, with its stringent latency requirements and the limits imposed by single FPGA resources, is currently being investigated. As a test case for this scenario we considered the online reconstruction of the RICH detector rings on an HLS generated module, using a dedicated primitives data stream with PM hits IDs. Besides, the chosen platform supports the Virtex Ultrascale+ FPGA wide I/O capabilities, allowing for straightforward integration of primitive streams from additional sub-detectors in order to improve the performance of the trigger.

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Rashid, Muhammad, Sajjad Shaukat Jamal, Sikandar Zulqarnain Khan, Adel R. Alharbi, Amer Aljaedi, and Malik Imran. "Elliptic-Curve Crypto Processor for RFID Applications." Applied Sciences 11, no. 15 (July 31, 2021): 7079. http://dx.doi.org/10.3390/app11157079.

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This work presents an Elliptic-curve Point Multiplication (ECP) architecture with a focus on low latency and low area for radio-frequency-identification (RFID) applications over GF(2163). To achieve low latency, we have reduced the clock cycles by using: (i) three-shift buffers in the datapath to load Elliptic-curve parameters as well as an initial point, (ii) the identical size of input/output interfaces in all building blocks of the architecture. The low area is preserved by using the same hardware resources of squaring and multiplication for inversion computation. Finally, an efficient controller is used to control the inferred logic. The proposed ECP architecture is modeled in Verilog and the synthesis results are given on three different 7-series FPGA (Field Programmable Gate Array) devices, i.e., Kintex-7, Artix-7, and Virtex-7. The performance of the architecture is provided with the integration of a schoolbook multiplier (implemented with two different logic styles, i.e., combinational and sequential). On Kintex-7, the combinational implementation style of a schoolbook multiplier results in power-optimized, i.e., 161 μW, values with an expense of (i) hardware resources, i.e., 3561 look-up-tables and 1527 flip-flops, (ii) clock frequency, i.e., 227 MHz, and (iii) latency, i.e., 11.57 μs. On the same Kintex-7 device, the sequential implementation style of a schoolbook multiplier provides, (i) 2.88 μs latency, (ii) 1786 look-up-tables and 1855 flip-flops, (iii) 647 μW power, and (iv) 909 MHz clock frequency. Therefore, the reported area, latency and power results make the proposed ECP architecture well-suited for RFID applications.

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23

Kirischian, L., V. Dumitriu, P. W. Chun, and G. Okouneva. "Mechanism of Resource Virtualization in RCS for Multitask Stream Applications." International Journal of Reconfigurable Computing 2010 (2010): 1–13. http://dx.doi.org/10.1155/2010/159367.

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Virtualization of logic, routing, and communication resources in recent FPGA devices can provide a dramatic improvement in cost-efficiency for reconfigurable computing systems (RCSs). The presented work is “proof-of-concept” research for the virtualization of the above resources in partially reconfigurable FPGA devices with a tile-based architecture. The following aspects have been investigated, prototyped, tested, and analyzed: (i) platform architecture for hardware support of the dynamic allocation of Application Specific Virtual Processors (ASVPs), (ii) mechanisms for run-time on-chip ASVP assembling using virtual hardware Components (VHCs) as building blocks, and (iii) mechanisms for dynamic on-chip relocation of VHCs to predetermined slots in the target FPGA. All the above mechanisms and procedures have been implemented and tested on a prototype platform—MARS (multitask adaptive reconfigurable system) using a Xilinx Virtex-4 FPGA. The on-chip communication infrastructure has been developed and investigated in detail, and its timing and hardware overhead were analyzed. It was determined that component relocation can be done without affecting the ASVP pipeline cycle time and throughput. The hardware overhead was estimated as relatively small compared to the gain of other performance parameters. Finally, industrial applications associated with next generation space-borne platforms are discussed, where the proposed approach can be beneficial.

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"Investigation of SEU sensitivity of Xilinx Virtex II FPGA by pulsed laser fault injections." Microelectronics Reliability 44, no. 9-11 (September 2004): 1709–14. http://dx.doi.org/10.1016/j.microrel.2004.07.060.

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25

Lisovik, Ulyana, and Oleksandr Lipchanskiy. "THE IMPLEMENTATION OF THE NEURAL NETWORK FOR THE CLASSIFICATION PROBLEM." International Journal of Computing, August 1, 2014, 119–26. http://dx.doi.org/10.47839/ijc.3.2.295.

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The example of NN realization is considered. Also description of all its design stages from NN function model description to its timing and hardware characteristics estimation is considered. NN structural model is presented in VHDL code. Through SynplifyPro 7.0 package from Synplicity® the system synthesis with the orientation on Virtex- II XC2V6000 family is made out. The estimation of the optimality of the synthesized NN model utilization is accomplished. NN structures are shown; hardware costs are taken to the table.

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"Efficient Comparator Design for Motion Estimation on FPGA." International Journal of Recent Technology and Engineering 8, no. 2 (July 30, 2019): 1118–23. http://dx.doi.org/10.35940/ijrte.b1656.078219.

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Motion Estimation(ME) operationinvolves predicting the frames and identifying motion vectors sothat redundancy can be exploited by eliminating the transfer ofsimilar information between successive frames.The most efficientand simple technique to estimate the motion vectors is Summation ofAbsolute Difference(SAD) where comparator forms one of an elemental component in SAD computation.This paper proposes two different comparator designs where propoundcircuit I is based on efficient look ahead comparator andpropound circuit II uses alteredone’s complement and conditional sum adder method. Results shows that propound circuit I reduces delay by 23%but with 16% increase in number of slice LUTs whereas the propoundcircuit II reduces delay by 11% and gives 33% reduction in number of slice LUTsas compared to traditional circuit. The propound hardwarecircuits are implemented on Virtex 7 FPGA and synthesized using Verilog as HDL language on Xilinx ISE 14.2.

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"Real Time Implementation of SIGN LMS Adaptive Filters using Xilinx System Generator." International Journal of Mathematics and Computers in Simulation 14 (May 4, 2020). http://dx.doi.org/10.46300/9102.2020.14.2.

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Sign Least Mean Square (SLMS) adaptive filter can adapt dynamically based on corresponding filter output. One of the major applications of adaptive filter is Noise cancellation. In real time applications like medical computing, speed of the process developing hardware is essential hence the hardware realization of SLMS adaptive filter using Xilinx System generator is proposed in this work. The propose architecture aims to reduce convergence rate, path delay and increasing speed. In this work (i) Modified architecture is designed for a 8-tap SLMS adaptive filter and (ii) multiplier less structure for Modified DLMS Filter. The designed architecture tested for ECG signal. The functionality of the algorithm is verified in MATLAB with various ECG data from the MIT-BIH database as input. Both LMS and SLMS are designed, simulated, synthesized and implemented in Virtex-5 FPGA using Xilnix ISE 14.3 . The result shows 5% decrease in total real time router completion and also decrease in the number of adders and subtractors, the maximum combinational path delay has been reduced by 48.84% in Systolic Sign LMS Filter when compared to LMS Filter.

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"Design SSTL Based Energy Efficient Solar Charge Sensor on FPGA." International Journal of Innovative Technology and Exploring Engineering 8, no. 12 (October 10, 2019): 3114–17. http://dx.doi.org/10.35940/ijitee.k1728.1081219.

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In this paper we have designed solar charge sensor which is used to make our battery efficient. Component is designed on Virtex 6 FPGA family and applied frequency scaling techniques. During the experiment, we have used different SSTL IO families and calculated total power consumption. In our work we have selected class I and class II from SSTL IO family. For the analysis we have used following range of frequency (20GHz, 40GHz, 60GHz and 80GHz). Firstly, we have worked with SSTL2_I and reduced total power consumption by 51.53%, in second experiment we have worked with SSTL2_I_DCI and reduced consumption of power by 47.18%. In third experiment we choose to work with SSTL2_II and reduced 51.58% in total power consumption. In fourth experiment we opted SSTL15 Io standard and downscale the total power consumption by 51.57%. In fifth we have selected SSTL15_DCI and downscale the power consumption by 49.93%. In sixth experiment we set SSTL18_I_DCI IO standard and consumption minimize by 49.20% in total power. At the end we have mark to be worked with SSTL18_II_DCI which is DCI circuit and found 48.78% reduction in total power consumption.

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Rao, R. V. Ch Sekhar, and Mr M. Srinivasa Rao. "Feat Of Submerged Scheme Relevance In Power Pc Processor Based Fpga Using Fpga Ip Cores." International Journal of Computer Science and Informatics, July 2011, 28–33. http://dx.doi.org/10.47893/ijcsi.2011.1006.

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Under water systems use processor based rooted systems to provide control and guidance to the under water vehicles. They obtain target and vehicle dynamics data from sensors and gyros, and process this data as per control and guidance algorithms to generate control and guidance parameters to the actuation system. Traditionally x86 families are being used in these systems in amassing to memory, I/Os and other peripherals being on the card. The recent developments in FPGA (Field Programmable Gate Array) technology has made pavement to use superior FPGAs with IP cores to develop under water systems. The modern FPGA devices include 32-bit Power PC processor, memory blocks and programmable area to comprise peripheral blocks. Under water systems developed out of the FPGA cores are definitely have several advantages like, saving the card size (FPGA accommodates several of the components in addition to the processor), flexibility to adopt changes in design (as FPGA can be programmed by the end user), preventing obsolescence of components. Building an under water systems based on FPGA IP cores is an innovative and hottest technological demonstration with several advantages to prophesy. The present work describes the dwindling in power consumption and size of the Under Water System. This work will also be productive to CSS Division of NSTL in designing and miniaturizing embedded systems such as MCS, MDAC etc. used in marine systems. The present work describes the mellowness of under water system relevance in Power PC Based FPGA using FPGA IP Cores. This work includes understanding the design flow of EDK and learns about various IP Cores Provided by Xilinx EDK 10.1. The underwater system application has been implemented in ‘C’ language by using Xilinx Device Drivers. A custom logic in VHDL has been developed for truncating extra bits of ADC. In Xilinx ISE10.1 project navigator the developed VHDL Code has been integrated with C. The combined bit file generated has been downloaded into Xilinx Virtex-II Pro FPGA Proto Board.

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Journal articles on the topic 'Virtex-II'

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