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Academic literature on the topic 'Viterbi decoding algorithm'

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Published: 4 June 2025

Last updated: 8 July 2025

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Journal articles on the topic "Viterbi decoding algorithm"

1

Muhammad, Shamsuddeen Hassan, and Abdulrasheed Mustapha. "A Form of List Viterbi Algorithm for Decoding Convolutional Codes." U.Porto Journal of Engineering 4, no. 2 (2018): 42–48. http://dx.doi.org/10.24840/2183-6493_004.002_0004.

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Viterbi algorithm is a maximum likelihood decoding algorithm. It is used to decode convolutional code in several wireless communication systems, including Wi-Fi. The standard Viterbi algorithm gives just one decoded output, which may be correct or incorrect. Incorrect packets are normally discarded thereby necessitating retransmission and hence resulting in considerable energy loss and delay. Some real-time applications such as Voice over Internet Protocol (VoIP) telephony do not tolerate excessive delay. This makes the conventional Viterbi decoding strategy sub-optimal. In this regard, a modified approach, which involves a form of List Viterbi for decoding the convolutional code is investigated. The technique employed combines the bit-error correction capabilities of both the Viterbi algorithm and the Cyclic Redundancy Check (CRC) procedures. It first uses a form of ‘List Viterbi Algorithm’ (LVA), which generates a list of possible decoded output candidates after the trellis search. The CRC check is then used to determine the presence of correct outcome. Results of experiments conducted using simulation shows considerable improvement in bit-error performance when compared to classical approach.

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2

Reeve, J. S. "A parallel Viterbi decoding algorithm." Concurrency and Computation: Practice and Experience 13, no. 2 (2001): 95–102. http://dx.doi.org/10.1002/cpe.539.

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3

Sosnenko, Kateryna. "Improved Decoding Algorithms for Convolutional Codes." Cybernetics and Computer Technologies, no. 2 (June 9, 2024): 39–46. http://dx.doi.org/10.34229/2707-451x.24.2.4.

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Introduction. The considered implementation of the Viterbi algorithm provides a reduction in hardware and time costs for decoding convoluted code sequences, and can be used for semi-realistic modeling of existing means of data transmission (for example, in satellite communication). The purpose of the article. Show how when modeling the processes of encoding and decoding convolutional codes according to the improved Viterbi algorithm, as well as its implementation based on programmable logic devices of the FPGA type, it was possible to reduce the number of clocks of reading metrics and tracks from RAM by 2 times. The results. A two-fold decrease in the number of reading cycles of metrics and tracks (input sequences or reverse pointers) from RAM is achieved by joint processing of two receiver nodes that share two source nodes. Relatively small costs for a hardware calculator of edge metrics allow you to organize parallel calculation, comparison and multiplexing of metrics and tracks of two sources at the inputs of block RAM. Two-port block memory makes it possible to significantly (up to two times) speed up the decoding process, to abandon metric and track buffer registers. Conclusions: The Viterbi decoder is widely used in communication systems and is a practical method of error correction at high signal transmission speed in modern telecommunication systems. The Viterbi decoder is designed for decoding convolutional codes and is optimal in the sense of minimizing the probability of an error. The advantage of the Viterbi decoder is that its complexity is a linear function of the number of symbols in the codeword sequence. In addition, the Viterbi algorithm is widely used in pattern recognition systems using hidden Markov models. Keywords: Convolutional codes, Viterbi algorithm, FPGA basis, metrics.

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4

Suman, Chandel, and Mathur Manju. "Viterbi Decoder Plain Sailing Design for TCM Decoders." International Journal of Trend in Scientific Research and Development 3, no. 5 (2019): 1794–97. https://doi.org/10.5281/zenodo.3591497.

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Convolutional codes are error correction technique used in noisy channels. Viterbi Algorithm is the most widely used decoding Algorithm, which decodes the sequence in a maximum likelihood sense. But the complexity of the Viterbi decoder increases with the coding rate of the system. Viterbi decoder is the most power hungry module in the Trellis coded modulation system. Viterbi decoding is the best technique for decoding the convolutional codes but it is limited to smaller constraint lengths. The basic building blocks of Viterbi decoder are branch metric unit, add compare and select unit and survivor memory management unit. From the simulation results it is observed that the proposed Viterbi decoder architecture with modified Branch metric calculation can reduce significant amount of computations in order to decrease the hardware usage and to simplify the proceedings. Suman Chandel | Manju Mathur "Viterbi Decoder Plain Sailing Design for TCM Decoders" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-5 , August 2019, URL: https://www.ijtsrd.com/papers/ijtsrd26710.pdf

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5

Monfared, Saleh Khalaj, Omid Hajihassani, Vahid Mohsseni, Dara Rahmati, and Saeid Gorgin. "A High-throughput Parallel Viterbi Algorithm via Bitslicing." ACM Transactions on Parallel Computing 8, no. 4 (2021): 1–25. http://dx.doi.org/10.1145/3470642.

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In this work, we present a novel bitsliced high-performance Viterbi algorithm suitable for high-throughput and data-intensive communication. A new column-major data representation scheme coupled with the bitsliced architecture is employed in our proposed Viterbi decoder that enables the maximum utilization of the parallel processing units in modern parallel accelerators. With the help of the proposed alteration of the data scheme, instead of the conventional bit-by-bit operations, 32-bit chunks of data are processed by each processing unit. This means that a single bitsliced parallel Viterbi decoder is capable of decoding 32 different chunks of data simultaneously. Here, the Viterbi’s Add-Compare-Select procedure is implemented with our proposed bitslicing technique, where it is shown that the bitsliced operations for the Viterbi internal functionalities are efficient in terms of their performance and complexity. We have achieved this level of high parallelism while keeping an acceptable bit error rate performance for our proposed methodology. Our suggested hard and soft-decision Viterbi decoder implementations on GPU platforms outperform the fastest previously proposed works by and , achieving 21.41 and 8.24 Gbps on Tesla V100, respectively.

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6

Wang, Haocheng, Yafeng Wang, and Yue Hu. "Bidirectional Viterbi decoding algorithm for OvTDM." China Communications 17, no. 7 (2020): 183–92. http://dx.doi.org/10.23919/j.cc.2020.07.013.

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7

Han, Ke, Zhong Liang Deng, and Lian Ming Xu. "The Viterbi Decoding Scheme for FPGA." Applied Mechanics and Materials 63-64 (June 2011): 835–40. http://dx.doi.org/10.4028/www.scientific.net/amm.63-64.835.

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This paper analyzes the principle of Viterbi algorithm which can be used in the norm of the mobile communication system. Then a new Viterbi decoding scheme of (2, 1, 7) convolutional code is presented for FPGA implementation. To take advantage of the FPGA, a new branch weight algorithm and uniform state weight memories is used. At last, a new decoding circuit which can work on 35MHz and can achieve 120 kbs in decoding speed was designed. To use the design of survival path exchange register module, it can decrease the power consumption and the RAM size.

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8

Kahina, Rekkal, and Abdesselam Bassou. "Improving the Performance of Viterbi Decoder using Window System." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (2018): 611. http://dx.doi.org/10.11591/ijece.v8i1.pp611-621.

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An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.

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9

Rekkal, Kahina, and Bassou Abdesselam. "Improving The Performance of Viterbi Decoder using Window System." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (2018): 611–21. https://doi.org/10.11591/ijece.v8i1.pp611-621.

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An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.

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10

Al-Rabadi, Anas. "Closed-system quantum logic network implementation of the Viterbi algorithm." Facta universitatis - series: Electronics and Energetics 22, no. 1 (2009): 1–33. http://dx.doi.org/10.2298/fuee0901001a.

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New convolution-based multiple-stream error-control coding and decoding schemes are introduced. The new coding method applies the reversibility property in the convolution-based encoder for multiple-stream error-control encoding and implements the reversibility property in the new reversible Viterbi decoding algorithm for multiple-stream error-correction decoding. The complete design of quantum circuits for the quantum realization of the new quantum Viterbi cell in the quantum domain is also introduced. In quantum mechanics, a closed system is an isolated system that can't exchange energy or matter with its surroundings and doesn't interact with other quantum systems. In contrast to open quantum systems, closed quantum systems obey the unitary evolution and thus they are reversible. Reversibility property in error-control coding can be important for the following main reasons: (1) reversibility is a basic requirement for low-power circuit design in future technologies such as in quantum computing (QC), (2) reversibility leads to super-speedy encoding/decoding operations because of the superposition and entanglement properties that emerge in the quantum computing systems that are naturally reversible and therefore very high performance is obtained, and (3) it is shown in this paper that the reversibility relationship between multiple-streams of data can be used for further correction of errors that are uncorrectable using the implemented decoding algorithm such as in the case of triple-errors that are uncorrectable using the classical irreversible Viterbi algorithm. .

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Dissertations / Theses on the topic "Viterbi decoding algorithm"

1

Cui, Xiaoxiao. "MODIFIED VITERBI DECODING ALGORITHM FOR CIRCULAR TRELLIS-CODED MODULATION." Ohio University / OhioLINK, 2000. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171649965.

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2

Beale, Martin Warwick. "Reduced state decoding of convolutional codes." Thesis, University of Cambridge, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.320013.

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3

Yamazato, Takaya, Iwao Sasase, and Shinsaku Mori. "A New Viterbi Algorithm with Adaptive Path Reduction Method." IEICE, 1993. http://hdl.handle.net/2237/7839.

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4

Fang, Juing. "Décodage pondère des codes en blocs et quelques sujets sur la complexité du décodage." Paris, ENST, 1987. http://www.theses.fr/1987ENST0005.

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Etude de la compléxité théorique du décodage des codes en blocs à travers une famille d'algorithmes basée sur le principe d'optimisation combinatoire. Puis on aborde un algorithme parallèle de décodage algébrique dont la complexitré est liée au niveau de bruit du canal. Enfin on introduit un algorithme de Viterbi pour les applications de traitement en chaînes.

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5

Huang, Zhiyong. "Modified Viterbi decoding algorithms for high dimensional trellis coded modulation." Ohio : Ohio University, 2003. http://www.ohiolink.edu/etd/view.cgi?ohiou1175094385.

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6

Segkos, Michail. "Advanced techniques to improve the performance of OFDM Wireless LAN." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2004. http://library.nps.navy.mil/uhtbin/hyperion/04Jun%5FSegkos.pdf.

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Thesis (M.S. in Electrical Engineering and M.S. in Applied Physics)--Naval Postgraduate School, June 2004.<br>Thesis advisor(s): Tri T. Ha, Brett H. Borden. Includes bibliographical references (p. 107-109). Also available online.

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7

Chen, Chun-Hao, and 陳俊豪. "Decoding Metric based on Viterbi Algorithm over Markov-Gaussian Channel." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/6snff5.

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碩士<br>國立臺灣科技大學<br>電機工程系<br>102<br>It is well known that communication systems are prone to impulse noise; it becomes more and more common to have coexistent systems overlap partial or full bandwidth, inevitably introducing interference to each other if no sophisticated coordinating mechanism is enabled. Nevertheless, the cost arising from the refined coordinating algorithm can be mounting, especially when the number of devices increases to a certain extent, plaguing the coordinator to, if not impossible, maintain a stable network. In this thesis, a self-arbitrating mechanism is introduced to a low-cost communication device in the presence of impulse noise, which can either instantly occur in each time instant or take place based on whether or not the occurrence of impulse was true in the previous time instant. The study aims at blunting the effect of occurrence of impulses while the statistics of impulse noise is not assumed at the decoder. In the scenario regarding the memory channel noise model, a first-order Markov chain, characterized by the transition probabilities and the probability of impulse occurrence, is used. Without assuming the aforementioned probabilities as well as the power strength of impulse noise, the decoder, additionally taking into account the noise (or channel) state, implements a two-dimensional trellis search owing to virtual state’s help, in a manner similar to the Viterbi algorithm. When compared with other existing methods forgoing the statistics of impulse under the same simulation setups, the proposed decoding algorithm enjoys several decibel gain in terms of signal-to-noise ratio at a bit error probability of 1.0E-5 . Furthermore, the proposed decoder is attested to be robust in numerous scenarios and even performs fairly close to the maximum likelihood decoder, which nevertheless assumes the statistics of impulse are available.

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8

Chang, Chihhao, and 張智皓. "Design of Differential Frequency Hopping Systems Using Soft Decision Viterbi Decoding Algorithm." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/34453059289581050156.

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碩士<br>國立聯合大學<br>電機工程學系碩士班<br>100<br>Differential frequency-hopping (DFH) systems have been widely studied and applied in the military communications because of their reli-able high data rate transmission characteristics and anti-jamming abilities. Since DFH systems are mainly used in the military areas, the information security during the transmission of data is another important issue in ad-dition to the system performance. In DFH systems, the frequency transi-tion function (FTF), so-called G-function, which determines how the transmitted frequency is depended on both the current data symbol and the previous transmitted frequency, is the key technique. However, DFH systems with the conventional G-function have the worse performance in the information security, so that the transmitted data was easily intercepted by the eavesdroppers. Therefore, in order to improve the information security of the conventional DFH system, a novel DFH system with the G-function controlled by the well-known maximal length sequences, is proposed in the thesis. Moreover, the pro-posed DFH system also utilizes the BCH codes and soft decision Viterbi algorithm in the transmitter and receiver, respectively, to further improve the system performance. In the thesis, the computer simulation of the proposed DFH system under the additive white Gaussian noise (AWGN) channel and Rayleigh fading channel, respectively, are also provided to identify the feasibility and validity of proposed scheme by using Matlab program. The simula-tion results show that not only both randomness and continuity of the proposed scheme can be effectively improved by utilizing the maximum length sequences, but also the system performance will further get better due to the use of BCH codes.

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9

Garga, Ganesh. "Flexible Constraint Length Viterbi Decoders On Large Wire-area Interconnection Topologies." Thesis, 2009. https://etd.iisc.ac.in/handle/2005/975.

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To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without having to recall previously deployed devices. This is achievable if as much functionality of the mobile device as possible is provided through software. A mobile device which fits this description is called a Software Defined Radio (SDR). Reconfigurable hardware-based solutions are an attractive option for realizing SDRs as they can potentially provide a favourable combination of the flexibility of a DSP or a GPP and the efficiency of an ASIC. The work presented in this thesis discusses the development of efficient reconfigurable hardware for one of the most energy-intensive functionalities in the mobile device, namely, Forward Error Correction (FEC). FEC is required in order to achieve reliable transfer of information at minimal transmit power levels. FEC is achieved by encoding the information in a process called channel coding. Previous studies have shown that the FEC unit accounts for around 40% of the total energy consumption of the mobile unit. In addition, modern wireless standards also place the additional requirement of flexibility on the FEC unit. Thus, the FEC unit of the mobile device represents a considerable amount of computing ability that needs to be accommodated into a very small power, area and energy budget. Two channel coding techniques have found widespread use in most modern wireless standards -namely convolutional coding and turbo coding. The Viterbi algorithm is most widely used for decoding convolutionally encoded sequences. It is possible to use this algorithm iteratively in order to decode turbo codes. Hence, this thesis specifically focusses on developing architectures for ﬂexible Viterbi decoders. Chapter 2 provides a description of the Viterbi and turbo decoding techniques. The flexibility requirements placed on the Viterbi decoder by modern standards can be divided into two types -code rate flexibility and constraint length flexibility. The code rate dictates the number of received bits which are handled together as a symbol at the receiver. Hence, code rate flexibility needs to be built into the basic computing units which are used to implement the Viterbi algorithm. The constraint length dictates the number of computations required per received symbol as well as the manner of transfer of results between these computations. Hence, assuming that multiple processing units are used to perform the required computations, supporting constraint length flexibility necessitates changes in the interconnection network connecting the computing units. A constraint length K Viterbi decoder needs 2K−1computations to be performed per received symbol. The results of the computations are exchanged among the computing units in order to prepare for the next received symbol. The communication pattern according to which these results are exchanged forms a graph called a de Bruijn graph, with 2K−1nodes. This implies that providing constraint length flexibility requires being able to realize de Bruijn graphs of various sizes on the interconnection network connecting the processing units. This thesis focusses on providing constraint length flexibility in an efficient manner. Quite clearly, the topology employed for interconnecting the processing units has a huge effect on the efficiency with which multiple constraint lengths can be supported. This thesis aims to explore the usefulness of interconnection topologies similar to the de Bruijn graph, for building constraint length flexible Viterbi decoders. Five different topologies have been considered in this thesis, which can be discussed under two different headings, as done below: De Bruijn network-based architectures The interconnection network that is of chief interest in this thesis is the de Bruijn interconnection network itself, as it is identical to the communication pattern for a Viterbi decoder of a given constraint length. The problem of realizing flexible constraint length Viterbi decoders using a de Bruijn network has been approached in two different ways. The first is an embedding-theoretic approach where the problem of supporting multiple constraint lengths on a de Bruijn network is seen as a problem of embedding smaller sized de Bruijn graphs on a larger de Bruijn graph. Mathematical manipulations are presented to show that this embedding can generally be accomplished with a maximum dilation of, where N is the number of computing nodes in the physical network, while simultaneously avoiding any congestion of the physical links. In this case, however, the mapping of the decoder states onto the processing nodes is assumed fixed. Another scheme is derived based on a variable assignment of decoder states onto computing nodes, which turns out to be more efficient than the embedding-based approach. For this scheme, the maximum number of cycles per stage is found to be limited to 2 irrespective of the maximum contraint length to be supported. In addition, it is also found to be possible to execute multiple smaller decoders in parallel on the physical network, for smaller constraint lengths. Consequently, post logic-synthesis, this architecture is found to be more area-efficient than the architecture based on the embedding theoretic approach. It is also a more efficiently scalable architecture. Alternative architectures There are several interconnection topologies which are closely connected to the de Bruijn graph, and hence could form attractive alternatives for realizing flexbile constraint length Viterbi decoders. We consider two more topologies from this class -namely, the shuffle-exchange network and the flattened butterfly network. The variable state assignment scheme developed for the de Bruijn network is found to be directly applicable to the shuffle-exchange network. The average number of clock cycles per stage is found to be limited to 4 in this case. This is again independent of the constraint length to be supported. On the flattened butterfly (which is actually identical to the hypercube), a state scheduling scheme similar to that of bitonic sorting is used. This architecture is found to offer the ideal throughput of one decoded bit every clock cycle, for any constraint length. For comparison with a more general purpose topology, we consider a flexible constraint length Viterbi decoder architecture based on a 2D-mesh, which is a popular choice for general purpose applications, as well as many signal processing applications. The state scheduling scheme used here is also similar to that used for bitonic sorting on a mesh. All the alternative architectures are capable of executing multiple smaller decoders in parallel on the larger interconnection network. Inferences Following logic synthesis and power estimation, it is found that the de Bruijn network-based architecture with the variable state assignment scheme yields the lowest (area)−(time) product, while the flattened butterfly network-based architecture yields the lowest (area) - (time)2product. This means, that the de Bruijn network-based architecture is the best choice for moderate throughput applications, while the flattened butterfly network-based architecture is the best choice for high throughput applications. However, as the flattened butterfly network is less scalable in terms of size compared to the de Bruijn network, it can be concluded that among the architectures considered in this thesis, the de Bruijn network-based architecture with the variable state assignment scheme is overall an attractive choice for realizing flexible constraint length Viterbi decoders.

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10

Garga, Ganesh. "Flexible Constraint Length Viterbi Decoders On Large Wire-area Interconnection Topologies." Thesis, 2009. http://hdl.handle.net/2005/975.

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To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without having to recall previously deployed devices. This is achievable if as much functionality of the mobile device as possible is provided through software. A mobile device which fits this description is called a Software Defined Radio (SDR). Reconfigurable hardware-based solutions are an attractive option for realizing SDRs as they can potentially provide a favourable combination of the flexibility of a DSP or a GPP and the efficiency of an ASIC. The work presented in this thesis discusses the development of efficient reconfigurable hardware for one of the most energy-intensive functionalities in the mobile device, namely, Forward Error Correction (FEC). FEC is required in order to achieve reliable transfer of information at minimal transmit power levels. FEC is achieved by encoding the information in a process called channel coding. Previous studies have shown that the FEC unit accounts for around 40% of the total energy consumption of the mobile unit. In addition, modern wireless standards also place the additional requirement of flexibility on the FEC unit. Thus, the FEC unit of the mobile device represents a considerable amount of computing ability that needs to be accommodated into a very small power, area and energy budget. Two channel coding techniques have found widespread use in most modern wireless standards -namely convolutional coding and turbo coding. The Viterbi algorithm is most widely used for decoding convolutionally encoded sequences. It is possible to use this algorithm iteratively in order to decode turbo codes. Hence, this thesis specifically focusses on developing architectures for ﬂexible Viterbi decoders. Chapter 2 provides a description of the Viterbi and turbo decoding techniques. The flexibility requirements placed on the Viterbi decoder by modern standards can be divided into two types -code rate flexibility and constraint length flexibility. The code rate dictates the number of received bits which are handled together as a symbol at the receiver. Hence, code rate flexibility needs to be built into the basic computing units which are used to implement the Viterbi algorithm. The constraint length dictates the number of computations required per received symbol as well as the manner of transfer of results between these computations. Hence, assuming that multiple processing units are used to perform the required computations, supporting constraint length flexibility necessitates changes in the interconnection network connecting the computing units. A constraint length K Viterbi decoder needs 2K−1computations to be performed per received symbol. The results of the computations are exchanged among the computing units in order to prepare for the next received symbol. The communication pattern according to which these results are exchanged forms a graph called a de Bruijn graph, with 2K−1nodes. This implies that providing constraint length flexibility requires being able to realize de Bruijn graphs of various sizes on the interconnection network connecting the processing units. This thesis focusses on providing constraint length flexibility in an efficient manner. Quite clearly, the topology employed for interconnecting the processing units has a huge effect on the efficiency with which multiple constraint lengths can be supported. This thesis aims to explore the usefulness of interconnection topologies similar to the de Bruijn graph, for building constraint length flexible Viterbi decoders. Five different topologies have been considered in this thesis, which can be discussed under two different headings, as done below: De Bruijn network-based architectures The interconnection network that is of chief interest in this thesis is the de Bruijn interconnection network itself, as it is identical to the communication pattern for a Viterbi decoder of a given constraint length. The problem of realizing flexible constraint length Viterbi decoders using a de Bruijn network has been approached in two different ways. The first is an embedding-theoretic approach where the problem of supporting multiple constraint lengths on a de Bruijn network is seen as a problem of embedding smaller sized de Bruijn graphs on a larger de Bruijn graph. Mathematical manipulations are presented to show that this embedding can generally be accomplished with a maximum dilation of, where N is the number of computing nodes in the physical network, while simultaneously avoiding any congestion of the physical links. In this case, however, the mapping of the decoder states onto the processing nodes is assumed fixed. Another scheme is derived based on a variable assignment of decoder states onto computing nodes, which turns out to be more efficient than the embedding-based approach. For this scheme, the maximum number of cycles per stage is found to be limited to 2 irrespective of the maximum contraint length to be supported. In addition, it is also found to be possible to execute multiple smaller decoders in parallel on the physical network, for smaller constraint lengths. Consequently, post logic-synthesis, this architecture is found to be more area-efficient than the architecture based on the embedding theoretic approach. It is also a more efficiently scalable architecture. Alternative architectures There are several interconnection topologies which are closely connected to the de Bruijn graph, and hence could form attractive alternatives for realizing flexbile constraint length Viterbi decoders. We consider two more topologies from this class -namely, the shuffle-exchange network and the flattened butterfly network. The variable state assignment scheme developed for the de Bruijn network is found to be directly applicable to the shuffle-exchange network. The average number of clock cycles per stage is found to be limited to 4 in this case. This is again independent of the constraint length to be supported. On the flattened butterfly (which is actually identical to the hypercube), a state scheduling scheme similar to that of bitonic sorting is used. This architecture is found to offer the ideal throughput of one decoded bit every clock cycle, for any constraint length. For comparison with a more general purpose topology, we consider a flexible constraint length Viterbi decoder architecture based on a 2D-mesh, which is a popular choice for general purpose applications, as well as many signal processing applications. The state scheduling scheme used here is also similar to that used for bitonic sorting on a mesh. All the alternative architectures are capable of executing multiple smaller decoders in parallel on the larger interconnection network. Inferences Following logic synthesis and power estimation, it is found that the de Bruijn network-based architecture with the variable state assignment scheme yields the lowest (area)−(time) product, while the flattened butterfly network-based architecture yields the lowest (area) - (time)2product. This means, that the de Bruijn network-based architecture is the best choice for moderate throughput applications, while the flattened butterfly network-based architecture is the best choice for high throughput applications. However, as the flattened butterfly network is less scalable in terms of size compared to the de Bruijn network, it can be concluded that among the architectures considered in this thesis, the de Bruijn network-based architecture with the variable state assignment scheme is overall an attractive choice for realizing flexible constraint length Viterbi decoders.

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Books on the topic "Viterbi decoding algorithm"

1

Lin, Shu. On decoding of multi-level MPSK modulation codes. Dept. of Electrical Engineering, University of Hawaii at Manoa, 1990.

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University of Hawaii at Manoa. Dept. of Electrical Engineering. and Goddard Space Flight Center, eds. On decoding of multi-level MPSK modulation codes. Dept. of Electrical Engineering, University of Hawaii at Manoa, 1990.

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Shu, Lin. On decoding of multi-level MPSK modulation codes. Dept. of Electrical Engineering, University of Hawaii at Manoa, 1990.

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Book chapters on the topic "Viterbi decoding algorithm"

1

Minango, Juan, Marcelo Zambrano, and Jorge Caraguay. "Co-channel Interference Mitigation Using Convolutional Enconder via Joint Decoding Viterbi Algorithm." In Innovation and Research - A Driving Force for Socio-Econo-Technological Development. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-11438-0_2.

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Walrand, Jean. "Speech Recognition: A." In Probability in Electrical Engineering and Computer Science. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-49995-2_11.

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AbstractSpeech recognition can be formulated as the problem of guessing a sequence of words that produces a sequence of sounds. The human brain is remarkably good at solving this problem, even though the same words correspond to many different sounds, because of accents or characteristics of the voice. Moreover, the environment is always noisy, to that the listeners hear a corrupted version of the speech.Computers are getting much better at speech recognition and voice command systems are now common for smartphones (Siri), automobiles (GPS, music, and climate control), call centers, and dictation systems. In this chapter, we explain the main ideas behind the algorithms for speech recognition and for related applications.The starting point is a model of the random sequence (e.g., words) to be recognized and of how this sequence is related to the observation (e.g., voice). The main model is called a hidden Markov chain. The idea is that the successive parts of speech form a Markov chain and that each word maps randomly to some sounds. The same model is used to decode strings of symbols in communication systems.Section 11.1 is a general discussion of learning. The hidden Markov chain model used in speech recognition and in error decoding is introduced in Sect. 11.2. That section explains the Viterbi algorithm. Section 11.3 discusses expectation maximization and clustering algorithms. Section 11.4 covers learning for hidden Markov chains.

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Lin, Shu, Tadao Kasami, Toru Fujiwara, and Marc Fossorier. "The Viterbi and Differential Trellis Decoding Algorithms." In Trellises and Trellis-Based Decoding Algorithms for Linear Block Codes. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5745-6_10.

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Véstias, Mário Pereira. "High-Speed Viterbi Decoder." In Encyclopedia of Information Science and Technology, Fifth Edition. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-3479-3.ch019.

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The Viterbi algorithm is the most well-known trellis-based maximum likelihood decoding algorithm. Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is implemented with a Viterbi decoder. High-speed applications require high-speed Viterbi decoders. Therefore, many hardware solutions have been proposed to improve the performance of Viterbi decoders. These hardware solutions explore the properties of the Viterbi algorithm to simplify and improve the architecture of the decoder. In particular, statistical properties of the algorithm are used to design parallel Viterbi decoders with very high data decoding rates. The article focuses on the implementation of high-speed Viterbi decoders.

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Véstias, Mário Pereira. "Viterbi Decoder in Hardware." In Advances in Computer and Electrical Engineering. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-7598-6.ch084.

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Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is the most well-known trellis-based maximum likelihood decoding algorithm. The Viterbi algorithm is executed by a Viterbi decoder. Different hardware solutions may be considered to implement a Viterbi decoder with different design requirements in terms of area, performance, power consumption, among others. The most appropriate solution depends on the metric requirements of the application as well as on the target technology. Properties of the Viterbi algorithm are used to simplify and improve the architecture of the Viterbi decoder. In particular, statistical properties of the Viterbi algorithm are used to design parallel Viterbi decoders with very high data decoding rates. The chapter focuses on the implementation of a Viterbi decoder in hardware, including optimizations to improve the area and performance.

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Véstias, Mário Pereira. "Viterbi Decoder in Hardware." In Encyclopedia of Information Science and Technology, Fourth Edition. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-2255-3.ch549.

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Abstract:

Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is the most well known trellis-based maximum likelihood decoding algorithm. The Viterbi algorithm is executed by a Viterbi decoder. Different hardware solutions may be considered to implement a Viterbi decoder with different design requirements in terms of area, performance, power consumption, among others. The most appropriate solution depends on the metric requirements of the application as well as on the target technology. Properties of the Viterbi algorithm are used to simplify and improve the architecture of the Viterbi decoder. In particular, statistical properties of the Viterbi algorithm are used to design parallel Viterbi decoders with very high data decoding rates. The article focuses on the implementation of a Viterbi decoder in hardware, including optimizations to improve the area and performance.

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Conference papers on the topic "Viterbi decoding algorithm"

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Kerner, M., and O. Amrani. "Viterbi algorithm motives in turbo decoding." In IEEE Information Theory Workshop, 2005. IEEE, 2005. http://dx.doi.org/10.1109/itw.2005.1531865.

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Nair, Nishanth Ulhas, and T. V. Sreenivas. "Viterbi Algorithm for multi-pattern joint decoding." In TENCON 2009 - 2009 IEEE Region 10 Conference. IEEE, 2009. http://dx.doi.org/10.1109/tencon.2009.5396092.

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Hulyalkar, Vidisha Niteen, Priyatamkumar, and Ramakrishna Joshi. "Hard and Soft Decision Decoding Using Viterbi Algorithm." In 2018 3rd International Conference on Inventive Computation Technologies (ICICT). IEEE, 2018. http://dx.doi.org/10.1109/icict43934.2018.9034450.

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Mahran, Ashraf, and Ramy Samy. "Modified adaptive Viterbi algorithm for convolutional codes decoding." In 2017 IEEE Aerospace Conference. IEEE, 2017. http://dx.doi.org/10.1109/aero.2017.7943748.

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Ciaperoni, Martino, Aristides Gionis, Athanasios Katsamanis, and Panagiotis Karras. "SIEVE: A Space-Efficient Algorithm for Viterbi Decoding." In SIGMOD/PODS '22: International Conference on Management of Data. ACM, 2022. http://dx.doi.org/10.1145/3514221.3526170.

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Zolotarev, V. V., N. N. Grinchenko, G. V. Ovechkin, and P. V. Ovechkin. "Modified Viterbi algorithm for decoding of block codes." In 2017 6th Mediterranean Conference on Embedded Computing (MECO). IEEE, 2017. http://dx.doi.org/10.1109/meco.2017.7977250.

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Kairouz, Peter, Aolin Xu, Naresh Shanbhag, and Andrew Singer. "A sphere decoding approach for the vector Viterbi algorithm." In 2012 46th Asilomar Conference on Signals, Systems and Computers. IEEE, 2012. http://dx.doi.org/10.1109/acssc.2012.6488970.

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Sparso, J., H. N. Jorgensen, E. Paaske, S. Pedersen, and T. Rubner-Petersen. "A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm." In ESSCIRC '89: 15th European Solid-State Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/esscirc.1989.5468082.

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Mishra, Shivshankar, and Ram Racksha Tripathi. "VDHL Implementation of Viterbi Algorithm for Decoding of Convolutional Code." In 2015 International Conference on Computational Intelligence and Communication Networks (CICN). IEEE, 2015. http://dx.doi.org/10.1109/cicn.2015.265.

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Arsadjaja, Alfonsus Raditya, and Achmad Imam Kistijantoro. "Online Speech Decoding Optimization Strategy with Viterbi Algorithm on GPU." In 2018 5th International Conference on Advanced Informatics: Concept Theory and Applications (ICAICTA). IEEE, 2018. http://dx.doi.org/10.1109/icaicta.2018.8541343.

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