Relevant bibliographies by topics / Viterbi encoder

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Viterbi encoder'

Author: Grafiati
Published: 4 June 2025
Last updated: 6 July 2025

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Journal articles on the topic "Viterbi encoder"

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Md., Abdul Rawoof, Ch Umasankar., Naresh Kumar D., Khalandar Basha D., and Madhu N. "Verilog based efficient convolution encoder and viterbi decoder." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 1 (2019): 75–80. https://doi.org/10.11591/ijres.v8.i1.pp75-80.

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In thetoday"sdigital communication Systems,transmission of data with more reliability and efficiency is the most challenging issue for data communication through channels. In communication systems, error correction technique plays a vital role. In error correction techniques, The capacity of data can be enhanced by adding the redundant information for the source data while transmitting the data through channel. It mainly focuses on the awareness of convolution encoder and Viterbi decoder. For decoding convolution codes Viterbi algorithm is preferred.
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Kahina, Rekkal, and Abdesselam Bassou. "Improving the Performance of Viterbi Decoder using Window System." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (2018): 611. http://dx.doi.org/10.11591/ijece.v8i1.pp611-621.

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An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.
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Rekkal, Kahina, and Bassou Abdesselam. "Improving The Performance of Viterbi Decoder using Window System." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (2018): 611–21. https://doi.org/10.11591/ijece.v8i1.pp611-621.

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An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.
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kumar, G. Madhu, and A. Swetha A.Swetha. "Design and implementation of convolution encoder and viterbi decoder." International Journal of Scientific Research 1, no. 6 (2012): 65–66. http://dx.doi.org/10.15373/22778179/nov2012/23.

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S Sreekanth, V., Y. Rama Krishna, and A. V V Prasad. "Simulation and Implementation of Convolution Encoder and Viterbi Decoder." International Journal of Scientific Engineering and Research 4, no. 10 (2016): 132–37. https://doi.org/10.70729/ijser151051.

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Al-Aboosi, Yasin Yousif, Ammar Ali Sahrab, Amal Ibrahim Nasser, and Hussein A. Abdulnabi. "Error performance analysis of forward error correction using convolutional encoding in the presence of (1/f) noise." Bulletin of Electrical Engineering and Informatics 12, no. 5 (2023): 2903–12. http://dx.doi.org/10.11591/eei.v12i5.4771.

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Any communication scheme's principal goal is providing error-free data transmission. By increasing the rate at which data could be transmitted through a channel and maintaining a given error rate, this coding is advantageous. The message bits to be transmitted will gradually receive more bits thanks to the convolution (channel) encoder. At the receiver end of the channel, a Viterbi decoder is utilized in order to extract original message sequence from the received data. Widely utilized error correction approaches in communication systems for the enhancement of bit error rate (BER) performance are Viterbi decoding and convolutional encoding. The Viterbi decoder and convolution encoder rate for constraints with lengths of 2 and 6 and bit rates of 1⁄2 and 1⁄3 are shown in this study in the presence of (1/f) noise. The performance regarding the convolutional encoding/hard decision Viterbi decoding forward error correction (FEC) method affects the simulation outcomes. The findings demonstrate that the BER as function of signal to noise ratio (SNR) acquired for uncoded binary phase shift keying (BPSK) with the existence of additive white Gaussian noise (AWGN) is inferior to that acquired with the use of a hard decision Viterbi decoder.
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Rawoof, Md Abdul, Umasankar Ch., D. Naresh Kumar, D. Khalandar Basha, and N. Madhur. "Verilog based efficient convolution encoder and viterbi decoder." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 1 (2019): 75. http://dx.doi.org/10.11591/ijres.v8.i1.pp75-80.

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In the<strong><em> </em></strong>today’s<strong><em> </em></strong>digital communication Systems,<strong><em> </em></strong>transmission of data with more reliability and efficiency is the most challenging issue for data communication through channels. In communication systems, error correction technique plays a vital role. In error correction techniques, The capacity of data can be enhanced by adding the redundant information for the source data while transmitting the data through channel. It mainly focuses on the awareness of convolution encoder and Viterbi decoder. For decoding convolution codes Viterbi algorithm is preferred.
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Nayak, Manashree, Praveen Kumar Y.G, and Dr M. Z. Kurian. "Implementation of Encoder and Adaptive Viterbi Decoder." International Journal of Computer & Organization Trends 5, no. 1 (2014): 40–42. http://dx.doi.org/10.14445/22492593/ijcot-v5p309.

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Suman, Chandel, and Mathur Manju. "Viterbi Decoder Plain Sailing Design for TCM Decoders." International Journal of Trend in Scientific Research and Development 3, no. 5 (2019): 1794–97. https://doi.org/10.5281/zenodo.3591497.

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Convolutional codes are error correction technique used in noisy channels. Viterbi Algorithm is the most widely used decoding Algorithm, which decodes the sequence in a maximum likelihood sense. But the complexity of the Viterbi decoder increases with the coding rate of the system. Viterbi decoder is the most power hungry module in the Trellis coded modulation system. Viterbi decoding is the best technique for decoding the convolutional codes but it is limited to smaller constraint lengths. The basic building blocks of Viterbi decoder are branch metric unit, add compare and select unit and survivor memory management unit. From the simulation results it is observed that the proposed Viterbi decoder architecture with modified Branch metric calculation can reduce significant amount of computations in order to decrease the hardware usage and to simplify the proceedings. Suman Chandel | Manju Mathur "Viterbi Decoder Plain Sailing Design for TCM Decoders" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-5 , August 2019, URL: https://www.ijtsrd.com/papers/ijtsrd26710.pdf
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N., Glory Priscilla, and M. Ramesh Patnaik Dr. "Reconfigurable Adaptive Viterbi Algorithm for Conventional Decoding." Journal of VLSI Design and its Advancement 2, no. 3 (2019): 1–4. https://doi.org/10.5281/zenodo.3561938.

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<strong><em>ABSTRACT</em></strong> <em>Conventional encoder is widely applied to lots of wireless communications including 3G/4G communication and digital video Broad casting (DVB), IOT (Internet of things) transmission and so on. A reconfigurable Viterbi decoder design is proposed for LTE-A, WiMAX, LTECDMA, GSM and TD-SCDMA. The proposed flexible architecture supports a polynomial reconfiguration. More over both tail biting and zero trellis terminating modes are supported. The transmitter encoder and receiver decoder are designed for verifying functionality .The purpose is to determine the feasible to design data error correcting to reduce the decoding latency and complexity it employs forward trace back method and sliding window technology.</em>
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Dissertations / Theses on the topic "Viterbi encoder"

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Sozen, Serkan. "A Viterbi Decoder Using System C For Area Efficient Vlsi Implementation." Master's thesis, METU, 2006. http://etd.lib.metu.edu.tr/upload/12607567/index.pdf.

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In this thesis, the VLSI implementation of Viterbi decoder using a design and simulation platform called SystemC is studied. For this purpose, the architecture of Viterbi decoder is tried to be optimized for VLSI implementations. Consequently, two novel area efficient structures for reconfigurable Viterbi decoders have been suggested. The traditional and SystemC design cycles are compared to show the advantages of SystemC, and the C++ platforms supporting SystemC are listed, installation issues and examples are discussed. The Viterbi decoder is widely used to estimate the message encoded by Convolutional encoder. For the implementations in the literature, it can be found that special structures called trellis have been formed to decrease the complexity and the area. In this thesis, two new area efficient reconfigurable Viterbi decoder approaches are suggested depending on the rearrangement of the states of the trellis structures to eliminate the switching and memory addressing complexity. The first suggested architecture based on reconfigurable Viterbi decoder reduces switching and memory addressing complexity. In the architectures, the states are reorganized and the trellis structures are realized by the usage of the same structures in subsequent instances. As the result, the area is minimized and power consumption is reduced. Since the addressing complexity is reduced, the speed is expected to increase. The second area efficient Viterbi decoder is an improved version of the first one and has the ability to configure the parameters of constraint length, code rate, transition probabilities, trace-back depth and generator polynomials.
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Ferreira, Nathan. "An Assessment of Available Software Defined Radio Platforms Utilizing Iterative Algorithms." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-theses/728.

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As the demands of communication systems have become more complex and varied, software defined radios (SDR) have become increasingly popular. With behavior that can be modified in software, SDR's provide a highly flexible and configurable development environment. Despite its programmable behavior, the maximum performance of an SDR is still rooted in its hardware. This limitation and the desire for the use of SDRs in different applications have led to the rise of various pieces of hardware to serve as SDR platforms. These platforms vary in aspects such as their performance limitations, implementation details, and cost. In this way the choice of SDR platform is not solely based on the cost of the hardware and should be closely examined before making a final decision. This thesis examines the various SDR platform families available on the market today and compares the advantages and disadvantages present for each during development. As many different types of hardware can be considered an option to successfully implement an SDR, this thesis specifically focuses on general purpose processors, system on chip, and field-programmable gate array implementations. When examining these SDR families, the Freescale BSC9131 is chosen to represent the system on chip implementation, while the Nutaq PicoSDR 2x2 Embedded with Virtex6 SX315 is used for the remaining two options. In order to test each of these platforms, a Viterbi algorithm is implemented on each and the performance measured. This performance measurement considers both how quickly the platform is able to perform the decoding, as well as its bit error rate performance in order to ascertain the implementations' accuracy. Other factors considered when comparing each platform are its flexibility and the amount of options available for development. After testing, the details of each implementation are discussed and guidelines for choosing a platform are suggested.
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Peh, Lin Kiat. "Performance comparison of two implementations of TCM for QAM." Thesis, Monterey, California. Naval Postgraduate School, 2007. http://hdl.handle.net/10945/55202.

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Approved for public release; distribution is unlimited.<br>Trellis-Coded Modulation (TCM) is employed with quadrature amplitude modulation (QAM) to provide error correction coding with no expense in bandwidth. There are two common implementations of TCM, namely pragmatic TCM and Ungerboeck TCM. Both schemes employ Viterbi algorithms for decoding but have different code construction. This thesis investigates and compares the performance of pragmatic TCM and Ungerboeck TCM by implementing the Viterbi decoding algorithm for both schemes with 16-QAM and 64-QAM. Both pragmatic and Ungerboeck TCM with six memory elements are considered. Simulations were carried out for both pragmatic and Ungerboeck TCM to evaluate their respective performance. The simulations were done using Matlab software, and an additive white Gaussian noise channel was assumed. The objective was to ascertain that pragmatic TCM, with its reduced-complexity decoding, is more suitable to adaptive modulation than Ungerboeck TCM.<br>Civilian
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Καζίλης, Φάνης. "Επεξεργαστές VLSI για διόρθωση λαθών με συνελικτικούς κώδικες". Thesis, 2010. http://hdl.handle.net/10889/5150.

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Σκοπός της παρούσας διπλωματικής εργασίας είναι η μελέτη και ο σχεδιασμός VLSI επεξεργαστών για τη διόρθωση λαθών. Η κατηγορία των VLSI επεξεργαστών στην οποία εστιάζει η έρευνά μου είναι ο αποκωδικοποιητής Viterbi. Αρχικά, παρουσιάζεται η δομή του ψηφιακού τηλεπικοινωνιακού συστήματος και κάποιες βασικές έννοιες των κωδικών διόρθωσης λαθών. Έπειτα, αναλύονται οι Συνελικτικοί κωδικοποιητές, ανάμεσα στους οποίους περιλαμβάνεται ο Συνελικτικός κωδικοποιητής που χρησιμοποιείται στην εργασία μου και ο οποίος χρησιμοποιείται ευρέως στο πρότυπο Wifi 802.11a. Ακολούθως, γίνεται αναφορά στο κανάλι AWGN και στη διαμόρφωση BPSK. Ακόμα, παρουσιάζονται οι βασικές έννοιες του αλγόριθμου Viterbi, η λειτουργία του, η δομή του καθώς και οι εφαρμογές του. Στη συνέχεια, μελετώνται διάφορες αρχιτεκτονικές του αποκωδικοποιητή Viterbi σε VLSI. Με βάση τον τρόπο υλοποίησης αριθμητικών πράξεων, οι αρχιτεκτονικές που αναπτύσσονται είναι ο Radix-2 και ο Radix-4 Viterbi, ενώ με βάση τον τρόπο αποκωδικοποίησης αναπτύσσονται οι αρχιτεκτονικές του Viterbi για συνεχή αποκωδικοποίηση-εφαρμογές streaming και του Viterbi για αποκωδικοποίηση πακέτων των 20 bits. Επίσης, μελετάται η απόδοση των αρχιτεκτονικών αυτών με κριτήριο τη συχνότητα λαθών που πραγματοποιούνται (Bit Error Rate – BER) και αναλύεται η υλοποίηση των αρχιτεκτονικών αυτών στο αναπτυξιακό σύστημα Xilinx. Τέλος, προκύπτουν τα κατάλληλα συμπεράσματα.<br>The purpose of this diploma thesis is to study and implement VLSI processors for correcting errors. The category of VLSI processor which will focus in this work is the Viterbi decoder. Initially, the structure of the digital telecommunications system is presented along with some basic concepts of error correcting codes. Then we explain the theory behind convolutional encoders and we describe the convolutional encoder that is used in my work and is consistent in the Wifi 802.11a standard. Next we analyze briefly the AWGN channel and the BPSJ modulation. Also the basic concepts of the Viterbi algorithm, how it works, its structure and the different applications are given. For the practical part which is the main part of this project, is to study the different architectures of the Viterbi decoder in VLSI approach. The main architectures that were developed for the implementation arithmetic operations is Radix-2 and Radix-4 Viterbi, but in terms of decoding two more architectures were developed, Viterbi continuous decoding-streaming applications and Viterbi decoding for packets of 20 bits. Then, the performance of these architectures in terms of frequency of errors made (BER) was investigated and also the implementation of these architectures in the development system Xilinx was analyzed. At the end we give our conclusion regarding the results of the different simulations that we’ve done.
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Book chapters on the topic "Viterbi encoder"

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Sowmya, K. B., D. N. Rahul Raj, and Sandesh Krishna Shetty. "Error Correction Technique Using Convolution Encoder with Viterbi Decoder." In Sustainable Communication Networks and Application. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-8677-4_20.

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Minango, Juan, Marcelo Zambrano, and Jorge Caraguay. "Co-channel Interference Mitigation Using Convolutional Enconder via Joint Decoding Viterbi Algorithm." In Innovation and Research - A Driving Force for Socio-Econo-Technological Development. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-11438-0_2.

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Halder, Archit, Saurabh Gajanan Bhokare, and Basanta Bhowmik. "Design of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog." In A Collection of Contemporary Research Articles in Electronics, Communication and Computation. Mantech Publications, 2021. http://dx.doi.org/10.47531/mantech/ecc.2021.21.

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Véstias, Mário Pereira. "High-Speed Viterbi Decoder." In Encyclopedia of Information Science and Technology, Fifth Edition. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-3479-3.ch019.

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The Viterbi algorithm is the most well-known trellis-based maximum likelihood decoding algorithm. Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is implemented with a Viterbi decoder. High-speed applications require high-speed Viterbi decoders. Therefore, many hardware solutions have been proposed to improve the performance of Viterbi decoders. These hardware solutions explore the properties of the Viterbi algorithm to simplify and improve the architecture of the decoder. In particular, statistical properties of the algorithm are used to design parallel Viterbi decoders with very high data decoding rates. The article focuses on the implementation of high-speed Viterbi decoders.
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Véstias, Mário Pereira. "Viterbi Decoder in Hardware." In Advances in Computer and Electrical Engineering. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-7598-6.ch084.

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Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is the most well-known trellis-based maximum likelihood decoding algorithm. The Viterbi algorithm is executed by a Viterbi decoder. Different hardware solutions may be considered to implement a Viterbi decoder with different design requirements in terms of area, performance, power consumption, among others. The most appropriate solution depends on the metric requirements of the application as well as on the target technology. Properties of the Viterbi algorithm are used to simplify and improve the architecture of the Viterbi decoder. In particular, statistical properties of the Viterbi algorithm are used to design parallel Viterbi decoders with very high data decoding rates. The chapter focuses on the implementation of a Viterbi decoder in hardware, including optimizations to improve the area and performance.
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Véstias, Mário Pereira. "Viterbi Decoder in Hardware." In Encyclopedia of Information Science and Technology, Fourth Edition. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-2255-3.ch549.

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Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is the most well known trellis-based maximum likelihood decoding algorithm. The Viterbi algorithm is executed by a Viterbi decoder. Different hardware solutions may be considered to implement a Viterbi decoder with different design requirements in terms of area, performance, power consumption, among others. The most appropriate solution depends on the metric requirements of the application as well as on the target technology. Properties of the Viterbi algorithm are used to simplify and improve the architecture of the Viterbi decoder. In particular, statistical properties of the Viterbi algorithm are used to design parallel Viterbi decoders with very high data decoding rates. The article focuses on the implementation of a Viterbi decoder in hardware, including optimizations to improve the area and performance.
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Conference papers on the topic "Viterbi encoder"

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Soreng, Bineeta, and Saurabh Kumar. "Efficient implementation of Convolution Encoder and Viterbi Decoder." In 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT). IEEE, 2013. http://dx.doi.org/10.1109/iccpct.2013.6529035.

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Wong, Yin Sweet, Wen Jian Ong, Jin Hui Chong, Chee Kyun Ng, and Nor Kamariah Noordin. "Implementation of convolutional encoder and Viterbi decoder using VHDL." In 2009 IEEE Student Conference on Research and Development (SCOReD). IEEE, 2009. http://dx.doi.org/10.1109/scored.2009.5443417.

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Khichar, Sunita, and Pawan Kumar Inaniya. "Is-OWC System Using Convolution Encoder and Viterbi Decoder." In 2018 International Conference on Inventive Research in Computing Applications (ICIRCA). IEEE, 2018. http://dx.doi.org/10.1109/icirca.2018.8597336.

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Kavinilavu, V., S. Salivahanan, V. S. Kanchana Bhaaskaran, Samiappa Sakthikumaran, B. Brindha, and C. Vinoth. "Implementation of Convolutional encoder and Viterbi decoder using Verilog HDL." In 2011 3rd International Conference on Electronics Computer Technology (ICECT). IEEE, 2011. http://dx.doi.org/10.1109/icectech.2011.5941609.

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Kulkarni, Anuradha, Dnyaneshwar Mantri, Neeli R. Prasad, and Ramjee Prasad. "Convolutional encoder and Viterbi decoder using SOPC for variable constraint length." In 2013 3rd IEEE International Advanced Computing Conference (IACC 2013). IEEE, 2013. http://dx.doi.org/10.1109/iadcc.2013.6514476.

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Suganya, G. S., and G. Kavya. "RTL design and VLSI implementation of an efficient convolutional encoder and adaptive Viterbi decoder." In 2013 International Conference on Communications and Signal Processing (ICCSP). IEEE, 2013. http://dx.doi.org/10.1109/iccsp.2013.6577103.

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Basavaraj, Hanchinal Punit, and Pappa M. "FPGA Implementation of High Speed Convolutional Encoder and Viterbi Decoder for Software Defined Radio." In 2023 Fifth International Conference on Electrical, Computer and Communication Technologies (ICECCT). IEEE, 2023. http://dx.doi.org/10.1109/icecct56650.2023.10179840.

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Koka Hemant, Hamsavahini, Pawan Upadhyay, and Shamim Akhter. "Design and implementation of crypto-based interleaver for viterbi encoder and decoder using turbo codes." In 2007 7th International Conference on ASIC. IEEE, 2007. http://dx.doi.org/10.1109/icasic.2007.4415778.

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Febrianti Irfat, Dwi Evita, I. Gede Puja Astawa, and Aries Pratiarso. "Analyze of Single RF Front End Performance on MIMO System using V-BLAST Detection for Convolutional Code Encoder and Viterbi Decoder." In 2020 International Electronics Symposium (IES). IEEE, 2020. http://dx.doi.org/10.1109/ies50839.2020.9231572.

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Borodzhieva, Adriana, and Plamen Manoilov. "Simulating the operation of feed-forward convolutional encoders and Viterbi decoders applied in additive white Gaussian noise communication channels." In the 9th International Conference. ACM Press, 2008. http://dx.doi.org/10.1145/1500879.1500932.

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