Journal articles: 'Viterbi encoder'

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Md., Abdul Rawoof, Ch Umasankar., Naresh Kumar D., Khalandar Basha D., and Madhu N. "Verilog based efficient convolution encoder and viterbi decoder." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 1 (2019): 75–80. https://doi.org/10.11591/ijres.v8.i1.pp75-80.

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In thetoday"sdigital communication Systems,transmission of data with more reliability and efficiency is the most challenging issue for data communication through channels. In communication systems, error correction technique plays a vital role. In error correction techniques, The capacity of data can be enhanced by adding the redundant information for the source data while transmitting the data through channel. It mainly focuses on the awareness of convolution encoder and Viterbi decoder. For decoding convolution codes Viterbi algorithm is preferred.

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Kahina, Rekkal, and Abdesselam Bassou. "Improving the Performance of Viterbi Decoder using Window System." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (2018): 611. http://dx.doi.org/10.11591/ijece.v8i1.pp611-621.

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An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.

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Rekkal, Kahina, and Bassou Abdesselam. "Improving The Performance of Viterbi Decoder using Window System." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (2018): 611–21. https://doi.org/10.11591/ijece.v8i1.pp611-621.

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An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.

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kumar, G. Madhu, and A. Swetha A.Swetha. "Design and implementation of convolution encoder and viterbi decoder." International Journal of Scientific Research 1, no. 6 (2012): 65–66. http://dx.doi.org/10.15373/22778179/nov2012/23.

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S Sreekanth, V., Y. Rama Krishna, and A. V V Prasad. "Simulation and Implementation of Convolution Encoder and Viterbi Decoder." International Journal of Scientific Engineering and Research 4, no. 10 (2016): 132–37. https://doi.org/10.70729/ijser151051.

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Al-Aboosi, Yasin Yousif, Ammar Ali Sahrab, Amal Ibrahim Nasser, and Hussein A. Abdulnabi. "Error performance analysis of forward error correction using convolutional encoding in the presence of (1/f) noise." Bulletin of Electrical Engineering and Informatics 12, no. 5 (2023): 2903–12. http://dx.doi.org/10.11591/eei.v12i5.4771.

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Any communication scheme's principal goal is providing error-free data transmission. By increasing the rate at which data could be transmitted through a channel and maintaining a given error rate, this coding is advantageous. The message bits to be transmitted will gradually receive more bits thanks to the convolution (channel) encoder. At the receiver end of the channel, a Viterbi decoder is utilized in order to extract original message sequence from the received data. Widely utilized error correction approaches in communication systems for the enhancement of bit error rate (BER) performance are Viterbi decoding and convolutional encoding. The Viterbi decoder and convolution encoder rate for constraints with lengths of 2 and 6 and bit rates of 1⁄2 and 1⁄3 are shown in this study in the presence of (1/f) noise. The performance regarding the convolutional encoding/hard decision Viterbi decoding forward error correction (FEC) method affects the simulation outcomes. The findings demonstrate that the BER as function of signal to noise ratio (SNR) acquired for uncoded binary phase shift keying (BPSK) with the existence of additive white Gaussian noise (AWGN) is inferior to that acquired with the use of a hard decision Viterbi decoder.

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Rawoof, Md Abdul, Umasankar Ch., D. Naresh Kumar, D. Khalandar Basha, and N. Madhur. "Verilog based efficient convolution encoder and viterbi decoder." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 1 (2019): 75. http://dx.doi.org/10.11591/ijres.v8.i1.pp75-80.

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In the today’s digital communication Systems, transmission of data with more reliability and efficiency is the most challenging issue for data communication through channels. In communication systems, error correction technique plays a vital role. In error correction techniques, The capacity of data can be enhanced by adding the redundant information for the source data while transmitting the data through channel. It mainly focuses on the awareness of convolution encoder and Viterbi decoder. For decoding convolution codes Viterbi algorithm is preferred.

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Nayak, Manashree, Praveen Kumar Y.G, and Dr M. Z. Kurian. "Implementation of Encoder and Adaptive Viterbi Decoder." International Journal of Computer & Organization Trends 5, no. 1 (2014): 40–42. http://dx.doi.org/10.14445/22492593/ijcot-v5p309.

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Suman, Chandel, and Mathur Manju. "Viterbi Decoder Plain Sailing Design for TCM Decoders." International Journal of Trend in Scientific Research and Development 3, no. 5 (2019): 1794–97. https://doi.org/10.5281/zenodo.3591497.

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Convolutional codes are error correction technique used in noisy channels. Viterbi Algorithm is the most widely used decoding Algorithm, which decodes the sequence in a maximum likelihood sense. But the complexity of the Viterbi decoder increases with the coding rate of the system. Viterbi decoder is the most power hungry module in the Trellis coded modulation system. Viterbi decoding is the best technique for decoding the convolutional codes but it is limited to smaller constraint lengths. The basic building blocks of Viterbi decoder are branch metric unit, add compare and select unit and survivor memory management unit. From the simulation results it is observed that the proposed Viterbi decoder architecture with modified Branch metric calculation can reduce significant amount of computations in order to decrease the hardware usage and to simplify the proceedings. Suman Chandel | Manju Mathur "Viterbi Decoder Plain Sailing Design for TCM Decoders" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-5 , August 2019, URL: https://www.ijtsrd.com/papers/ijtsrd26710.pdf

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N., Glory Priscilla, and M. Ramesh Patnaik Dr. "Reconfigurable Adaptive Viterbi Algorithm for Conventional Decoding." Journal of VLSI Design and its Advancement 2, no. 3 (2019): 1–4. https://doi.org/10.5281/zenodo.3561938.

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ABSTRACT Conventional encoder is widely applied to lots of wireless communications including 3G/4G communication and digital video Broad casting (DVB), IOT (Internet of things) transmission and so on. A reconfigurable Viterbi decoder design is proposed for LTE-A, WiMAX, LTECDMA, GSM and TD-SCDMA. The proposed flexible architecture supports a polynomial reconfiguration. More over both tail biting and zero trellis terminating modes are supported. The transmitter encoder and receiver decoder are designed for verifying functionality .The purpose is to determine the feasible to design data error correcting to reduce the decoding latency and complexity it employs forward trace back method and sliding window technology.

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Mathur, Nehul, and Sunil Sharma. "Simulation of Convolutional Encoder and Viterbi Decoder using Verilog." International Journal of Computer Applications 102, no. 4 (2014): 31–34. http://dx.doi.org/10.5120/17805-8625.

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R. J., Reshmi, and Raji C. "Design and Implementation of High Speed Viterbi Decoder and Convolution Encoder for SDR." Indian Journal of Science and Technology 12, no. 36 (2019): 1–5. http://dx.doi.org/10.17485/ijst/2019/v12i36/147574.

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V, S. Sneha, and Joe Nithin. "Implementation of Turbo Coder Using Verilog HDL for LTE." International Journal of Innovative Science and Research Technology 7, no. 7 (2022): 380–83. https://doi.org/10.5281/zenodo.6930806.

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In many communication systems, turbo codesare employed to repair errors. Turbo codes demonstrate high error correction when compared to other error correction methods. A Very Large Scale Integration is suggested in this study. VLSI architecture for the Turbo encoder implementation, Interleaves and de interleaves, and soft-in-soft-out decoders are employed. This study employs a technique that for the encoder portion, includes two recursive systematic convolutional (RSC) encoders , a Block interleaver and the decoder part involve Soft Output Virtebi Algorithm(SOVA) decoder. Aconvolutional code is a sort of error-correcting code used incommunicationsthat creates parity signals by sliding a Boolean polynomial function across a data stream. The word "convolutional coding" comes from the sliding application, which depicts the encoder's "convolution" acrossthe data. Convolutional codes sliding properties make it easier to do trellis decoding with a time-invariant trellis. Convolutional codes can be maximum-likelihood soft-decision decoded with a manageable level of complexity thanks to time invariant trellis decoding. The Viterbi algorithm, also known as the Viterbi path, is a dynamic programming approach for determining the greatest probability estimate of the most probable series of hidden states that leads to a series of observed events. The quantity of times needed to decode the bits is been reduced in this methodology. A block interleaver accepts a set of symbols and rearranges them, without repeating or omitting any of the symbols in the set. The number of symbols in each set is fixed for a given interleaver. Turbo encoding, as well as decoding simulations are done using Modelsim software.

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Rahmah, Linza Mawadda. "Analisis Kinerja Enkoder Konvolusi Dengan Parameter BER dan SNR Menggunakan MATLAB." JREC (Journal of Electrical and Electronics) 11, no. 1 (2023): 15–20. http://dx.doi.org/10.33558/jrec.v11i1.7122.

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Abstrak Sistem komunikasi satelit menggunakan rentang frekuensi yang sangat tinggi untuk menerima dan mengirim sinyal sehingga terdapat beberapa kekhawatiran yg menjadi masalah yaitu masalah keamanan dan kesalahan data selama proses transmisi yang disebabkan oleh noise. Pada penelitian ini, dilakukan simulasi terhadap kemungkinan terjadinya kesalahan bit error dan Signal to Noise Ratio (Eb/No) untuk mengetahui kinerja pada convolutional encoder. Sedangkan pada sisi decoder menggunakan algoritma viterbi. Simulasi dilakukan menggunakan Simulink Matlab dengan parameter struktur rate kode konvolusi, BER, dan Eb/No. Hasil simulasi menunjukan bahwa besarnya Bit Error Rate (BER) sangat dipengaruhi oleh besarnya Eb/No. Semakin besar nilai Eb/No (dB), maka nilai BER akan semakin kecil. Begitu juga sebaliknya, semakin kecil nilai Eb/No (dB), nilai BER akan semakin besar. Selain itu, dengan penggunaan convolutional codes, hasil simulasi menunjukan bahwa konvolusi enkoder dengan rate 2/3 lebih baik dari rate 1/2 dan 1/3. Kata Kunci: encoder konvolusi, rate, BER, signal to noise ratio (Eb/No), simulink matlab. Abstract Satellite Communication Systems use a very high-frequency range to receive and send signals. Some concerns become a problem, namely security issues, and data errors during the transmission process caused by noise. In this research, a simulation of the possibility of bit errors and Signal to Noise Ratio (Eb/No) was performed to determine the performance of the convolutional encoder. Whereas the decoder side uses the Viterbi algorithm. Simulations were carried out using Simulink Matlab with parameters the rate of convolution codes, BER, and Eb/No. Simulation results show that the magnitude of the bit error rate (BER) is strongly influenced by the amount of Eb/No. The greater the value of Eb/No (dB), the smaller the value of BER. And otherwise, the smaller the value of Eb/No, the greater the value of BER. In addition, with the use of Convolutional codes, the simulation results show that the convolution of encoders with a rate of 2/3 is better than the rate of ½ and 1/3. Keywords: convolutional encoder, rate, BER, signal to noise ratio (Eb/No), simulink matlab.

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Vasumathi, J., and R. Parameshwaran. "High throughput based transceiver design using convolutional encoder and Viterbi decoder." Contemporary Engineering Sciences 7 (2014): 339–44. http://dx.doi.org/10.12988/ces.2014.4211.

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Joseph, Thobius, Herbert Peter Wanga, Frank Samson, and Shangweli Vyosena Kituma. "Prototype for Multimedia Content Delivery based on Non-Transmittable Codewords Enhanced Viterbi Algorithm." International Journal of Engineering and Applied Computer Science 04, no. 04 (2022): 41–46. http://dx.doi.org/10.24032/ijeacs/0404/010.

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The paper provides a prototype for multimedia content delivery with reduced channel code rate from conventional Non-Transmittable Codewords Enhanced Viterbi Algorithm. The code rate reduction was simulated using VB.NET Viterbi simulator available at College of Informatics and Virtual Education-University of Dodoma. The study approximates Uplink and downlink speeds limits of the prototype using High Speed Packet Access Evolved technology by assuming all other parameters remain constant. The uplink and downlink of the prototype is clearly presented. The code rate of 1/3 was obtained by simulating different 8-bits patterns. This code rate of 1/3 enabled reduction of encoder output bits from 48-bits to 24-bits, therefore, few bits would be sent to the network and bandwidth conservation is attained. This makes the prototype to be the good choice for low network bandwidth channel. In addition, the reduced code rate will reduce the expenses of user internet bundles, because number of MBs to be charged will be smaller. This prototype for multimedia delivery over network has three benefits, high data transmission reliability due to adopted NTC Enhanced Viterbi, minimum network bandwidth utilization and satisfied uplink and downlink access speed.

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Abu, Mohd Azlan, Harlisya Harun, Mohammad Yazdi Harmin, Noor Izzri Abdul Wahab, and Muhd Khairulzaman Abdul Kadir. "The design of Viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model." World Journal of Engineering 13, no. 6 (2016): 540–46. http://dx.doi.org/10.1108/wje-09-2016-0088.

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Purpose This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD). Design/methodology/approach The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. The decoding process has been carried out using maximum likelihood sequences estimation through the Viterbi algorithm. Findings The results showed that the STTC decoder can successfully decipher the encoded symbols from the STTC encoder and can fully recover the original data. The data rate of the decoder is 50 Mbps. Originality/value It has been shown that 96 per cent improvement of the total logic elements in Max V CPLD is used compared to the previous literature review.

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Taher Qassim, Yahya, and Dr Dhafir A. Alneema. "FPGA Based Implementation of Convolutional Encoder- Viterbi Decoder Using Multiple Booting Technique." AL-Rafdain Engineering Journal (AREJ) 18, no. 6 (2010): 70–80. http://dx.doi.org/10.33899/rengj.2010.34888.

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Soni, Vinita, and Sandip Nemade. "FPGA Design for Efficient Architecture for the Convolution Encoder and Viterbi Decoder." International Journal of Engineering Trends and Technology 9, no. 2 (2014): 74–77. http://dx.doi.org/10.14445/22315381/ijett-v9p215.

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Ramanna, Dasari. "Low Power VLSI Implementation of Convolution Encoder and Viterbi Decoder using Verilog HDL." Bioscience Biotechnology Research Communications 13, no. 13 (2020): 177–84. http://dx.doi.org/10.21786/bbrc/13.13/25.

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AL-RABADI, ANAS N. "REVERSIBLE VITERBI ALGORITHM AND ITS CLOSED-SYSTEM Q-DOMAIN CIRCUIT DESIGN AND COMPUTATION." Journal of Circuits, Systems and Computers 18, no. 08 (2009): 1627–49. http://dx.doi.org/10.1142/s0218126609005903.

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Novel convolution-based multiple-stream error-control coding and decoding methods and their corresponding circuits are introduced. The new coding method applies the reversibility property in (1) the convolution-based encoder for multiple-stream error-control encoding and (2) in the new reversible Viterbi decoding algorithm for multiple-stream error-correction decoding. The complete synthesis of quantum circuits for the quantum realization of the new quantum Viterbi cell in the quantum domain (Q-domain) is also introduced, and the associated quantum computing representations and operations are presented. In quantum mechanics, a closed system is an isolated system that cannot exchange energy or matter with its surroundings and does not interact with other quantum systems. Closed quantum systems obey the unitary evolution and thus they are reversible. Reversibility property in error-control coding can be important for the following main reasons: (1) reversibility is a basic requirement for low-power circuit design in future technologies such as in closed-system quantum computing (QC), (2) reversibility leads to super-speedy encoding/decoding operations because of the superposition and entanglement properties that exist in the reversible closed-system quantum computing circuits and systems, and (3) the reversibility relationship between multiple-streams of data can be used for the correction of errors that are usually uncorrectable using the implemented decoding algorithm such as in the case of triple-errors that are uncorrectable using the irreversible Viterbi algorithm.

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Al-Rabadi, Anas. "Closed-system quantum logic network implementation of the Viterbi algorithm." Facta universitatis - series: Electronics and Energetics 22, no. 1 (2009): 1–33. http://dx.doi.org/10.2298/fuee0901001a.

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New convolution-based multiple-stream error-control coding and decoding schemes are introduced. The new coding method applies the reversibility property in the convolution-based encoder for multiple-stream error-control encoding and implements the reversibility property in the new reversible Viterbi decoding algorithm for multiple-stream error-correction decoding. The complete design of quantum circuits for the quantum realization of the new quantum Viterbi cell in the quantum domain is also introduced. In quantum mechanics, a closed system is an isolated system that can't exchange energy or matter with its surroundings and doesn't interact with other quantum systems. In contrast to open quantum systems, closed quantum systems obey the unitary evolution and thus they are reversible. Reversibility property in error-control coding can be important for the following main reasons: (1) reversibility is a basic requirement for low-power circuit design in future technologies such as in quantum computing (QC), (2) reversibility leads to super-speedy encoding/decoding operations because of the superposition and entanglement properties that emerge in the quantum computing systems that are naturally reversible and therefore very high performance is obtained, and (3) it is shown in this paper that the reversibility relationship between multiple-streams of data can be used for further correction of errors that are uncorrectable using the implemented decoding algorithm such as in the case of triple-errors that are uncorrectable using the classical irreversible Viterbi algorithm. .

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Hussein, Dina M., Abdelhalim Zekry, Said Baioumy, and Fatma El-Newagy. "Implementation of a standard inner convolutional codec for DVB-T system using VHDL." International Journal of Engineering & Technology 6, no. 4 (2017): 131. http://dx.doi.org/10.14419/ijet.v6i4.8038.

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Forward error correction (FEC) plays a vital role in digital communication systems. DVB-T system uses FEC as a channel coding technique to restore any data lost through transmission to the receiver. DVB-T system uses two levels of error protection. The first level is applied in the data transmitted by using a Reed-Solomon RS (204, 188) code followed by a convolutional interleaver. The other level of error protection is a punctured convolutional inner coding followed by an inner interleave in which the data sequence is rearranged again to minimize the influence of burst errors.This paper describes the implementation of inner convolutional codec (Convolutional coder and Viterbi Decoder) and inner de/interleaving of a standard DVB-T system with a constrained length of 7 and a code rate of 2/3 using VHDL on virtex-6 FPGA xc6vlx240t. The designed channel convolutional encoder and Viterbi decoder follow European Standard ETSI EN 300 744 for digital terrestrial television. Verification of the design is accomplished by loop back and by comparison with the corresponding Xilinx core. Utilization and timing re-ports of the implemented device on Vertex 6 are included.

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Thune, Neeta Nitin, and Sanjay Haridas. "Low Power Trellis Coded Modulation (TCM) Decoder by Using Modified Resource Sharing Method for IoT Enabler." International Journal of Electronics, Communications, and Measurement Engineering 11, no. 1 (2022): 1–9. http://dx.doi.org/10.4018/ijecme.312260.

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This paper proposes a new pre-computation approach based on the auxiliary trellis of the TCM decoder's ACSU (add compare select unit). The suggested method is based on pre-computation of path metrics and resource sharing of the ACSU unit. The Viterbi decoder itself is a power-consuming module of the communication system that comprises the TMU (transition metric unit) and ACSU (add compare select unit). By applying the suggested method, the authors would be able to achieve low dynamic power. The TCM decoder designed accordingly shows better SER/ BER results in comparison to the existing techniques. The 4D 8 PSK TCM encoder and decoder were implemented as per the design specifications given by consultative committee for space data system (CCSDS) for satellite applications. The simulations results are observed on 100 Mbps data for 8PSK modulation and the ¾ code rate of the TCM encoder. The results based on the new method show improved power-speed ratio with improved SER and BER.

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Thune, Neeta N., Archana B. Kanwade, Mohini Sardey, Sarika A. Panwar, and G. S. Gawande. "KNN-Based ML Model for the Symbol Prediction in TCM Trellis Coded Modulation TCM Decoder." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 9s (2023): 623–27. http://dx.doi.org/10.17762/ijritcc.v11i9s.7475.

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Machine Learning is a booming technology today. In a machine learning set of training, data is to be provided to the model for training and that model predicts the output. Machine Learning models are trained using a computer program known as ML algorithms.The new machine learning-based Transition Metric Unit (TMU) of 4D- 8PSK Trellis coded Modulation TCM Decoder is presented in this work. The classic Viterbi decoder's branch metric unit, or TMU, takes on a complex structure. Trellis coded Modulation (TCM) is a combination of 8 PSK modulations and Error Correcting Code (ECC). TMU is one of the complex units of the TCM decoder, which is essentially a Viterbi decoder. Similar to how the first Branch metric is determined in the straightforward Viterbi decoder, the TCM decoder performs this BM computation via the TMU unit. The TMU becomes challenging and uses more dynamic power as a result of the enormous constraint length and the vast number of encoder states.In the proposed algorithm innovative KNN (K nearest neighbours) based ML model is developed. It is a supervised learning model in which input and output both are provided to the model, training data also called the labels, when a new set of data will come the model will give output based on its previous set experience and data.Here we are using this ML model for the symbol prediction at the receiver end of the TCM decoder based on the previous learning. Using the proposed innovation, the paper perceives the optimization of the TCM Decoder which will further reduce the H/W requirements and low latency which results in less power consumption.

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Singh, Dr Balkar. "TURBO CODE RE-ANALYSIS USING DIFFERENT ALGORITHMS." International Journal of Engineering Science and Humanities 14, Special Issue 1 (2024): 27–31. http://dx.doi.org/10.62904/k2aydz44.

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Turbo codes are a novel type of forward error correcting codes that have proved to give a perfor- mance close to the channel capacity as proposed by C. Shannon. The parallel concatenation of two identical recursive convolutional encoders that are spaced apart by an interleaver results in a turbo code encoder. The two cascaded decoding blocks used by the turbo code decoder pass along a priori knowledge generated by each block in turn. The decoding approach has the advantage of working iteratively, allowing for an increase in total performance. This study does a performance analysis of turbo codes. The performance study includes two decoding methods: the soft output Viterbi algo- rithm (SOVA), which uses the log-likelihood ratio to produce soft outputs, and the log maximum a posteriori probability (Log-MAP) algorithm. Both punctured and unpunctured codes are studied to determine the impact of utilizing various decoding algorithms. The performance of the two various decoding techniques is then contrasted in terms of bit error rate. MATLAB tools are utilized to per- form simulations.

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Ramesh, K., and S. Sudha. "FPGA Implementation of High Speed and Low Power Viterbi Decoder Using Reverse Algorithm of Convolution Encoder." Journal of Computational and Theoretical Nanoscience 14, no. 12 (2017): 5957–62. http://dx.doi.org/10.1166/jctn.2017.7042.

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Sun, Yan, and Zhizhong Ding. "FPGA Design and Implementation of a Convolutional Encoder and a Viterbi Decoder Based on 802.11a for OFDM." Wireless Engineering and Technology 03, no. 03 (2012): 125–31. http://dx.doi.org/10.4236/wet.2012.33019.

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Sidorenko, Alexander A. "Method for changing the redundancy of sequential concatenated code." Journal of Physics: Conference Series 2697, no. 1 (2024): 012038. http://dx.doi.org/10.1088/1742-6596/2697/1/012038.

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Abstract During the operation of information transmission systems errors occur in the transmitted data due to the influence of various negative factors. To correct errors the codes are currently used that can withstand both single and multiple errors. From the point of view of the ability to correct multiple errors, concatenated codes are highly efficient. When constructing a sequential concatenated code, coding is carried out first by the external, then by the internal code. A significant disadvantage of such coding is a significant increase in redundancy. It is proposed to regulate redundancy by encoding with the internal code only a certain part of the bits from the output of the external code encoder. The study showed the effectiveness of this method, which made it possible to change the parameters of the cascade code within a wide range. A method was proposed and tested to increase the corrective ability of selective coding by multiplying symbols decoded by an external code by coefficients that are different for symbols that have and have not been encoded by an internal code. Decoding of the external code was carried out according to the Viterbi algorithm. The performance of the proposed method has been confirmed experimentally.

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Kao, Johnny W. H., Stevan M. Berber, and Abbas Bigdeli. "A General Rate K/N Convolutional Decoder Based on Neural Networks with Stopping Criterion." Advances in Artificial Intelligence 2009 (June 18, 2009): 1–11. http://dx.doi.org/10.1155/2009/356120.

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A novel algorithm for decoding a general rate K/N convolutional code based on recurrent neural network (RNN) is described and analysed. The algorithm is introduced by outlining the mathematical models of the encoder and decoder. A number of strategies for optimising the iterative decoding process are proposed, and a simulator was also designed in order to compare the Bit Error Rate (BER) performance of the RNN decoder with the conventional decoder that is based on Viterbi Algorithm (VA). The simulation results show that this novel algorithm can achieve the same bit error rate and has a lower decoding complexity. Most importantly this algorithm allows parallel signal processing, which increases the decoding speed and accommodates higher data rate transmission. These characteristics are inherited from a neural network structure of the decoder and the iterative nature of the algorithm, that outperform the conventional VA algorithm.

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Archana, B., and P. Surekha T. "Integrated approach for efficient power consumption and resource allocation in MIMO-OFDMA." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 2069–76. https://doi.org/10.11591/ijece.v10i2.pp2069-2076.

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The growing interest towards wireless communication advancement with smart devices has provided the desired throughput of wireless communication mechanisms. But, attaining high-speed data packets amenities is the biggest issue in different multimedia applications. Recently, OFDM has come up with the useful features for wireless communication however it faces interference issues at carrier level (intercarrier interferences). To resolve these interference issues in OFDM, various existing mechanisms were utilized cyclic prefix, but it leads to redundancy in transmitted data. Also, the transmission of this redundant data can take some more power and bandwidth. All these limitations factors can be removed from a parallel cancellation mechanism. The integration of parallel cancellation and Convolution Viterbi encoding and decoding in MIMOOFDMA will be an effective solution to have high data rate which also associations with the benefits of both the architectures of MIMO and OFDMA modulation approaches. This paper deals with this integrated mechanism for efficient resource allocation and power consumption. For performance analysis, MIMO-OFDMA system is analyzed with three different approaches likeMIMO-OFDM system without parallel cancellation (MIMO-OFDMA-WPC), MIMO-OFDMA System with parallel cancellation (MIMO-OFDMA-PC) and proposed IMO-OFDMA system with parallel cancellation and Convolution Viterbi encoding/decoding (pMIMO-OFDMAPC &CVed) for 4x4 transmitter and receiver. Through performance analysis, it is found that the proposed system achieved better resource allocation (bandwidth) with high data rate by minimized BER rate and achieved least power consumption with least BER.

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Samy, Ahmed, Ashraf Y. Hassan, and Hatem M. Zakaria. "Improving bit error-rate based on adaptive Bose-Chaudhuri Hocquenghem concatenated with convolutional codes." Indonesian Journal of Electrical Engineering and Computer Science 23, no. 2 (2021): 890–901. https://doi.org/10.11591/ijeecs.v23.i2.pp890-901.

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Several algorithms have been proposed to avoid the error floor region, such as the concatenation codes that requires high computational demands in addition to high complexity. This paper proposes a technique based on using cascaded BCH and convolutional codes that leads to better error correction performance. Moreover, an adaptive method based on sensing the channel's noise to determine the number of the parity bits that will be added to the used BCH that reduces the consumed bandwidth and the transmitted parity bits is presented. A further enhancement is fulfilled by using parallel processing branches, resulting in reducing the consumed time and speed up the performance. The results show that the proposed code presents a better performance. A high reduction in the number of cycles that will be used in the encoding and decoding compared with the classical method and finally a flexible parity bits method based on the signal-to-noise ratio of the channel that reduced the parity bits which leads to reduce the consumed bandwidth. The MATLAB simulation and the field programmable gate array (FPGA) implementation will be provided in this paper to validate the proposed concept.

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Lu, Jiaheng, and Weirong Liu. "Automatic Information Extraction for Financial Events by Integrating BiGRU and Attention Mechanism." Journal of Physics: Conference Series 2171, no. 1 (2022): 012001. http://dx.doi.org/10.1088/1742-6596/2171/1/012001.

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Abstract In this paper, an information extraction method for financial events written in Chinese is proposed. The core entities of the causes and results, as well as the verbs and conditions are extracted from the financial events reported by websites. The method takes the original words and the part-of-speech of words as two inputs. BERT encoder is utilized to transform the original sentences to word-embedding vectors, which then are send to BiGRU to extract the sematic features. And a full-connected network is overlapped on BiGRU to reduce the impact of “covariate shift”. For the second input, the original sentences are cut by Chinese cut-word tool ‘jieba’ to get the part-of-speech of words, which are then transformed by self-attention mechanism to get global dependencies. The two outputs for word-embedding vectors and part-of-speech of words are combined and then decoded by CRF. Finally, the Viterbi algorithm is utilized to get the best sequences. The experiment results validate the effectiveness of the proposed method.

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Kharchenko, Volodymyr, Yuri Barabanov, and Andrii Grekhov. "MODELING OF ADS-B DATA TRANSMISSION VIA SATELLITE." Aviation 17, no. 3 (2013): 119–27. http://dx.doi.org/10.3846/16487788.2013.840057.

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For modelling transmission of ADS-B messages via low-orbit satellite constellation Iridium, the original model of a communication channel “Aircraft-to-Satellite-to-Ground Station” was built using MATLAB Simulink. The model comprises “Aircraft Uplink Transmitter” (Bernoulli Random Binary Generator, Convolutional Encoder, BPSK Baseband Modulator, High Power Amplifier with a memoryless nonlinearity, Transmitter Dish Antenna Gain), “Uplink Path” (Free Space Path Loss, Phase/Frequency Offset), “Satellite Transponder” (Receiver Dish Antenna Gain, Satellite Receiver System Temperature, Complex Baseband Amplifier, Phase Noise, Transmitter Dish Antenna Gain), “Downlink Path” (Free Space Path Loss, Phase/Frequency Offset), “Ground Station Downlink Receiver” (Receiver Dish Antenna Gain, Ground Receiver System Temperature, Viterbi Decoder), “Error Rate Calculation” block and “Display”. The modelling was realized without and with convolutional coding (r = 3/4, K = 7) at different noise temperatures and free space losses. Dependencies of a Bit Error Rate on free space path losses, antenna's diameter, phase/frequency off-sets, satellite transponder linear gain, aircraft and satellite transponder high power amplifier back-off level, and phase noise were received and analysed.

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Nataraju, Chaitra Soppinahally, Desai Karanam Sreekantha, and Kanduri V. S. S. S. S.Sairam. "Low-power body-coupled transceiver for miniaturized body area networks." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 3 (2024): 3522. http://dx.doi.org/10.11591/ijece.v14i3.pp3522-3532.

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As wearable devices continue to proliferate, seamlessly integrating them into wireless body-area networks (WBANs) becomes increasingly crucial. Body-coupled communication (BCC) emerges as a promising WBAN technology, utilizing the human body itself as a transmission channel. This paper presents a novel BCC transceiver designed for efficiency and miniaturization. The proposed transceiver prioritizes reliable data transmission with a convolutional encoder. It leverages a simple direct digital synthesizer (DDS) for frequency shift keying (FSK) modulation, minimizing chip area. At the receiver, a Viterbi decoder (VD) ensures accurate data recovery. This design shines in its resource efficiency. It occupies less than 1% of an Artix-7 FPGA, operates at 268.77 MHz with a mere 111 mW power consumption, and achieves a remarkable data rate of 13.78 Mbps. This translates to a hardware efficiency of 44.46 Kbps/slice, surpassing existing transceivers. Moreover, the BCC transceiver exhibits a stellar bit error rate (BER) of over 10⁻⁷ under realistic body channel conditions. Overall, this work presents a highly efficient BCC transceiver with significant improvements in chip area, power consumption, and data rate compared to existing designs. This paves the way for practical and miniaturized WBAN solutions for future wearable applications.

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Soppinahally, Nataraju Chaitra, Sreekantha Desai Karanam, and S. S. S. S. Sairam Kanduri V. "Low-power body-coupled transceiver for miniaturized body area networks." Low-power body-coupled transceiver for miniaturized body area networks 14, no. 3 (2024): 3522–32. https://doi.org/10.11591/ijece.v14i3.pp3522-3532.

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As wearable devices continue to proliferate, seamlessly integrating them into wireless body-area networks (WBANs) becomes increasingly crucial. Body-coupled communication (BCC) emerges as a promising WBAN technology, utilizing the human body itself as a transmission channel. This paper presents a novel BCC transceiver designed for efficiency and miniaturization. The proposed transceiver prioritizes reliable data transmission with a convolutional encoder. It leverages a simple direct digital synthesizer (DDS) for frequency shift keying (FSK) modulation, minimizing chip area. At the receiver, a Viterbi decoder (VD) ensures accurate data recovery. This design shines in its resource efficiency. It occupies less than 1% of an Artix-7 FPGA, operates at 268.77 MHz with a mere 111 mW power consumption, and achieves a remarkable data rate of 13.78 Mbps. This translates to a hardware efficiency of 44.46 Kbps/slice, surpassing existing transceivers. Moreover, the BCC transceiver exhibits a stellar bit error rate (BER) of over 10⁻⁷ under realistic body channel conditions. Overall, this work presents a highly efficient BCC transceiver with significant improvements in chip area, power consumption, and data rate compared to existing designs. This paves the way for practical and miniaturized WBAN solutions for future wearable applications.

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Koti, Jayasudha, and Braj Kishore Mishra. "BER Performance Comparison of DCO-OFDM and Convolutional Coded DCO-OFDM in IM/DD Systems." International Journal of Electronics, Communications, and Measurement Engineering 8, no. 2 (2019): 26–39. http://dx.doi.org/10.4018/ijecme.2019070102.

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Optical wireless communication (OWC) is an alternative technology to meet the demands of the exponentially-growing high data rate applications run by broadband users. The implementation of single carrier modulation techniques in OWC is an age old technology, but for the last few years research is focused towards the multicarrier modulation techniques in OWC. In OWC, information is carried using intensity modulation and retrieved using direct detection. To perform intensity modulation, the baseband signal should be a unipolar signal. To obtain a unipolar signal, various techniques such as DC-biased orthogonal frequency division multiplexing (DCO-OFDM), Asymmetrically clipped orthogonal frequency division multiplexing (ACO-OFDM), Flip orthogonal frequency division multiplexing (Flip-OFDM) and Unipolar orthogonal frequency division multiplexing (U-OFDM) techniques are reported in the literature. Though the DCO-OFDM is spectrally efficient compared to other techniques it requires more power to achieve the targeted BER. In this article, a convolutional Coded DCO-OFDM (CDCO-OFDM) has been introduced by applying channel coding. A convolutional encoder and a hard-decision Viterbi decoder are considered in CDCO-OFDM. It has been observed that CDCO-OFDM requires less transmitted power than DCO-OFDM to attain the targeted BER. The performance of DCO-OFDM and CDCO-OFDM is evaluated for 4, 16, 64 QAM- 7dB and 13dB bias, in the presence of the additive white Gaussian noise (AWGN) channel. It is observed that CDCO requires less power to transmit than DCO-OFDM for the BER 10-4.

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Mallikarjuna, Gowda C. P., and Hajare Raju. "Space-time trellis codes: Field programmable gate array approach." International Journal of Reconfigurable and Embedded Systems 9, no. 3 (2020): 213–23. https://doi.org/10.11591/ijres.v9.i3.pp213-223.

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In this paper, an effective method of implementation of Space-Time Trellis Codes (STTC) for 4-state on Field Programmable Gate Array is presented. To reach the very high data rates provided in STTC, a lot of expensive highspeed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.

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Thorpe, J., and P. McLane. "A Hybrid Phase/Data Viterbi Demodulator for Encoded CPFSK Modulation." IEEE Transactions on Communications 33, no. 6 (1985): 535–42. http://dx.doi.org/10.1109/tcom.1985.1096344.

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Gulak, P., and E. Shwedyk. "VLSI Structures for Viterbi Receivers: Part II--Encoded MSK Modulation." IEEE Journal on Selected Areas in Communications 4, no. 1 (1986): 155–59. http://dx.doi.org/10.1109/jsac.1986.1146300.

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ANGARITA, FABIAN, M. JOSE CANET, TRINIDAD SANSALONI, VICENC ALMENAR, and JAVIER VALLS. "POWER CONSUMPTION REDUCTION IN A VITERBI DECODER FOR OFDM-WLAN." Journal of Circuits, Systems and Computers 18, no. 07 (2009): 1333–37. http://dx.doi.org/10.1142/s0218126609005691.

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WLAN standards make use of different transmission modes to cope with different channel conditions, these modes make use of different modulation constellations and code rates. Data encoding is done with a 64-state convolutional code of rate 1/2, some modes employ this basic rate and others puncture the encoded data to obtain a rate of 3/4. At the receiver, the decision depth needed by the Viterbi decoder is higher for decoding punctured modes than for decoding non-punctured modes, this means that punctured modes need a greater area and, then, they cause a higher power consumption. This fact is used in this letter to reduce the power consumption of the Viterbi decoder when dealing with half-rate code modes, an architecture that disables the unnecessary hardware in the non-punctured modes allows a reduction of 20% in the dynamic power consumption with an area increase of only 1%.

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Louet, Yves, Rami Othman, and Alexandre Skrzypczak. "A Soft-Output STBC Decoder for Aeronautical Telemetry." Journal of Telecommunications and Information Technology 1 (March 31, 2020): 13–20. http://dx.doi.org/10.26636/jtit.2020.138319.

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Alamouti encoding is a well-known space time block encoding technique used to improve the received signal quality in Rayleigh fading channels. In aeronautical telemetry, this encoding technique is applied to shaped oﬀset quadrature phase shift keying tier generation (SOQPSK-TG) modulation in order to handle the two-antenna issue. It is provided for in telemetry-related IRIG standards. In this paper, we propose a unique decoding architecture for Alamouti-encoded SOQPSK-TG signals, taking advantage of pulse amplitude modulation decomposition with soft and hard outputs. We exploit this result to obtain a Viterbi algorithm (VA) for hard decoding and a soft output Viterbi algorithm (SOVA) for soft and hard decoding, with a twofold beneﬁt: operation using one trellis structure, unlike decoders that are based on the 8-waveforms cross-correlated trellis-coded quadrature modulation (XTCQM) approximation, and very attractive bit error rate performance, as well as a complexity trade-oﬀ

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Kakkara, Varsha, Karthi Balasubramanian, B. Yamuna, Deepak Mishra, Karthikeyan Lingasubramanian, and Senthil Murugan. "A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study." PeerJ Computer Science 6 (March 2, 2020): e250. http://dx.doi.org/10.7717/peerj-cs.250.

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Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This article is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the Viterbi decoder. Design of a Viterbi decoder and possible hardware Trojan models for the same are proposed. An FPGA-based implementation of the decoder and the associated Trojan circuits have been discussed. The noise-added encoded input data stream is stored in the block RAM of the FPGA and the decoded data stream is monitored on the PC through an universal asynchronous receiver transmitter interface. The implementation results show that there is barely any change in the LUTs used (0.5%) and power dissipation (3%) due to the insertion of the proposed Trojan circuits, thus establishing the surreptitious nature of the Trojan. In spite of the fact that the Trojans cause negligible changes in the circuit parameters, there are significant changes in the bit error rate (BER) due to the presence of Trojans. In the absence of Trojans, BER drops down to zero for signal to noise rations (SNRs) higher than 6 dB, but with the presence of Trojans, BER doesn’t reduce to zero even at a very high SNRs. This is true even with the Trojan being activated only once during the entire duration of the transmission.

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Summerfield, S. "Analysis of convolutional encoders and synthesis of rate-2/n Viterbi decoders." IEEE Transactions on Information Theory 42, no. 4 (1996): 1280–85. http://dx.doi.org/10.1109/18.508860.

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Li, Bin, and P. Ho. "Viterbi algorithm with data-aided phase reference estimation for convolutionally encoded PSK." Electronics Letters 32, no. 16 (1996): 1453. http://dx.doi.org/10.1049/el:19960998.

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Sidorenko, Vladimir, Wenhui Li, Onur Günlü, and Gerhard Kramer. "Skew Convolutional Codes." Entropy 22, no. 12 (2020): 1364. http://dx.doi.org/10.3390/e22121364.

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A new class of convolutional codes, called skew convolutional codes, that extends the class of classical fixed convolutional codes, is proposed. Skew convolutional codes can be represented as periodic time-varying convolutional codes but have a description as compact as fixed convolutional codes. Designs of generator and parity check matrices, encoders, and code trellises for skew convolutional codes and their duals are shown. For memoryless channels, one can apply Viterbi or BCJR decoding algorithms, or a dualized BCJR algorithm, to decode skew convolutional codes.

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WANG, Yung-Yi, and Jiunn-Tsair CHEN. "The Jiggle-Viterbi Algorithm for the RFID Reader Using Structured Data-Encoded Waveforms." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E93-A, no. 11 (2010): 2108–14. http://dx.doi.org/10.1587/transfun.e93.a.2108.

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Vitetta, G. M., and D. P. Taylor. "Viterbi decoding of differentially encoded PSK signals transmitted over Rayleigh frequency-flat fading channels." IEEE Transactions on Communications 43, no. 2/3/4 (1995): 1256–59. http://dx.doi.org/10.1109/26.380163.

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Tomlinson, M., and M. N. A. Abu-Rgheff. "The TAR decoder-a bandpass Viterbi/FFT decoder for convolutional encoded spread-spectrum signals." IEEE Transactions on Communications 44, no. 11 (1996): 1392–98. http://dx.doi.org/10.1109/26.544452.

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Che-Hsi Lai and K. Kiasaleh. "Modified Viterbi decoders for joint data detection and timing recovery of convolutionally encoded PPM and OPPM optical signals." IEEE Transactions on Communications 45, no. 1 (1997): 90–94. http://dx.doi.org/10.1109/26.554290.

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Journal articles on the topic 'Viterbi encoder'

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