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Journal articles on the topic 'Vivado Design Suite'
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1
Cirugeda-Roldán, Eva M., María Sofía Martínez-García, Alberto Sanchez, and Angel de Castro. "Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx." Electronics 10, no. 16 (2021): 1952. http://dx.doi.org/10.3390/electronics10161952.
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Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet included.
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Asha Devi, Dharmavaram, Chintala Sandeep, and Sai Sugun L. "Design of Power Efficient 32-Bit Processing Unit." International Journal of Engineering & Technology 7, no. 2.16 (2018): 52. http://dx.doi.org/10.14419/ijet.v7i2.16.11415.
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The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit. The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.
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Kurdi, Aous H., Janos L. Grantner, and Ikhlas M. Abdel-Qader. "Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection." International Journal of Reconfigurable Computing 2017 (2017): 1–13. http://dx.doi.org/10.1155/2017/1325493.
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In this paper, the design and the implementation of a pipelined hardware accelerator based on a fuzzy logic approach for an edge detection system are presented. The fuzzy system comprises a preprocessing stage, a fuzzifier with four fuzzy inputs, an inference system with seven rules, and a defuzzification stage delivering a single crisp output, which represents the intensity value of a pixel in the output image. The hardware accelerator consists of seven stages with one clock cycle latency per stage. The defuzzification stage was implemented using three different defuzzification methods. These methods are the mean of maxima, the smallest of maxima, and the largest of maxima. The defuzzification modules are interchangeable while the system runs using partial reconfiguration design methodology. System development was carried out using Vivado High-Level Synthesis, Vivado Design Suite, Vivado Simulator, and a set of Xilinx 7000 FPGA devices. Depending upon the speed grade of the device that is employed, the system can operate at a frequency range from 83 MHz to 125 MHz. Its peak performance is up to 58 high definition frames per second. A comparison of this system’s performance and its software counterpart shows a significant speedup in the magnitude of hundred thousand times.
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Zou, Yong Yang, Ming Chen, and Kang Lin Wei. "Design of Custom AXI4 IP Based on AXI4 Protocol." Applied Mechanics and Materials 687-691 (November 2014): 2326–30. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.2326.
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In addition to its own function, the realization of the custom AXI4 IP ,to a large extent,depends on the development tools.The method of custom AXI4 IP is mainly introduced in this paper.The Xilinx Vivado Design Suite is the development environment for custom AXI4 IP.The generated IP is a AXI4 slave IP which implements the data access.In order to accurately verify the AXI4 slave IP,an embedded system on a chip is created to make a processor and the generated slave IP link together.TheZynq-7000 All Programmable SoC is fully taken advantage of to prove that the AXI4 slave IP functions well.A simple application program runs in a SoC.The terminal that can display output results shows the slave IP work well and gets the desired results.
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Gupta, Ramji, Alpana Pandey, and R. K.Baghel. "Efficient design of chaos based 4 bit true random number generator on FPGA." International Journal of Engineering & Technology 7, no. 3 (2018): 1783. http://dx.doi.org/10.14419/ijet.v7i3.16586.
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True random number generator is a basic building block of any modern secure communication and cryptography system. FPGA implementation of any system has a flexible architecture and low-cost test cycle. In this paper, we present an FPGA implementation of a high speed true random number generator based on chaos oscillator which gives optimize ratio of bit rate to area. The proposed generator is faster and more compact than the existing chaotic oscillator based TRNGs. The Experimental result shows that the proposed TRNG gives 1439 Mbps with optimizing the use of LUTs and registers. It is verified that the generator passes all the NIST SP 800-22 tests. The proposed TRNG is implemented in two FPGA families Nexus 4 (Artix 7) DDR XC7A100TCSG-1 and Basys 3 XC7A35T1CPG236C (Artix 7) using Xilinx Vivado v.2017.3 design suite.
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Tripathi, Abhishek N., and Arvind Rajawat. "Fast and Accurate System-Level Power Estimation Model for FPGA-Based Designs." Journal of Circuits, Systems and Computers 28, no. 13 (2019): 1950218. http://dx.doi.org/10.1142/s0218126619502189.
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In this paper, we present an efficient and fast system-level power estimation model for the FPGA-based designs. To estimate the dynamic power early, first time, LLVM IR code analysis is employed at the C-level designs and then the neural network-based estimation model is built from the information obtained from this high-level profiling. The model accuracy is validated through designs of heterogeneous domains from the CHStone and MachSuite benchmarks. An insignificant relative error of 0.21–3.6% is observed for the analyzed benchmark designs with the exceptional increase in the estimation speed by 63 times of magnitude as compared to the Xilinx Vivado Design Suite. Moreover, the model eliminates the need for synthesis-based exploration. In addition, the effectiveness of proposed approach is also verified through a comparison with the other reported works.
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Singaravelan, Hema, and Dr Kiran V. "32-bit Kogge-Stone based Hybrid Adder Implemented using Standard Cells of Different Logic Families." Journal of University of Shanghai for Science and Technology 23, no. 09 (2021): 196–204. http://dx.doi.org/10.51201/jusst/21/09539.
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Adders performs a critical role in all computational operations, thereby optimizing them with respect to design constraints for a system is essential. In this paper, standard cells of different logic families, namely- CMOS, Pseudo NMOS, and MGDI, are designed in Cadence Design Suite Virtuoso 6.1.7 in 180nm technology and characterized using Liberate 15.1.3. The standard cell libraries thus created are then applied to 32-bit KSA (Kogge-Stone Adder) and KSA based proposed hybrid adder that are implemented in Verilog, functionally verified on Xilinx Vivado 2020.2 and synthesized on Cadence Genus 15.22. Pseudo NMOS logic shows 14.03% area savings and MGDI offers 54.43% power saving based on area per cell over the traditional CMOS technology. It is also seen that the proposed adder offers a decrease in power and delay by 32.13% and 13.75% over KSA, respectively, in CMOS logic. Further discussions are made and suitable applications for all designs are also discussed.
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Hou, Yumin, Xu Wang, Jiawei Fu, Junping Ma, Hu He, and Xu Yang. "Improving ILP via Fused In-Order Superscalar and VLIW Instruction Dispatch Methods." Journal of Circuits, Systems and Computers 28, no. 02 (2018): 1950020. http://dx.doi.org/10.1142/s0218126619500208.
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In order to expand the computation capability of digital signal processing on a General Purpose Processor (GPP), we propose a fused microarchitecture that improves Instruction Level Parallelism (ILP) by supporting both in-order superscalar and very long instruction word (VLIW) dispatch methods in a single pipeline. This design is based on ARMv7-A&R Instruction Set Architecture (ISA). To provide a performance comparison, we first design an in-order superscalar processor, considering that ARM GPPs always adopt superscalar approaches. And then we expand VLIW dispatch method based on this processor, to realize the fused microarchitecture. The two designs are both evaluated on the Xilinx 7-series FPGA (XC7K325T-2FFG900C), using Xilinx Vivado design suite. The results show that, compared with the superscalar processor, the processor working under VLIW mode can improve the performance by 15% and 8%, respectively, when running EEMBC and DSPstone benchmarks. We also run the two benchmarks on ARM Cortex-A9 processor, which is integrated in the Zynq-7000 AP SoC device on Xilinx ZC706 evaluation board. The processor in VLIW mode shows 44% and 30% performance improvements than ARM Cortex-A9. The fused microarchitecture adopts a combined bimodal and PAp branch prediction method. This method achieves 93.7% prediction accuracy with limited hardware overhead.
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Srinivaas, Charrith. "A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm Using Verilog HDL." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (2021): 1876–79. http://dx.doi.org/10.22214/ijraset.2021.36731.
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As the technology is getting more and more advanced day by day in a rapid pace the problem for the security of data is also increasing at a very staggering rate. The hackers are equipped with new advanced tools and techniques to break any security system. Hence people are getting even more concerned about their data and data’s security. The data security can be achieved by either software or hardware implementations or both put together working in harmony. In this work Field Programmable Gate Arrays (FPGA) device is used for hardware implementation since these devices are less complex, more flexible and provide and have far greater more efficiency. This work mainly focuses on the hardware execution of one of the security algorithms that is the Advanced Encryption Standard (AES) algorithm which is the most highly used algorithm for Encryption. The AES algorithm is executed on Vivado 2014.2 ISE Design Suite and therefore the results are observed on 28 nanometers (nm) Artix-7 FPGA. This work Mainly discusses the design implementation of the AES algorithm and the resources which are consumed in implementing the AES design on Artix-7 FPGA. The resources which are consumed are as follows- Slice Register (SR), Look-Up Tables (LUTs), Input/Output (I/O) and Global Buffer.
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Ramesh Babu Chukka, Sudhakar Jyothula, Vijaya Sree Ganta ,. "DESIGN OF HIGH THROUGHPUT ADD COMPARE AND SELECT UNIT FOR LOW POWER VITERBI DECODER." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 1 (2021): 954–60. http://dx.doi.org/10.17762/itii.v9i1.223.
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The main purpose of this paper is to focus on the design of Viterbi Decoder (VD) with low power, which is significant for receiver section of data communication applications such as Radar, Satellite, Telephone and Automatic speech recognition. The Viterbi decoder algorithm consists of three most important blocks – Branch Metric Unit (BMU), Add Compare and Select (ACS) Unit and Survivor Memory Unit (SMU). BMU computes the metrics between the input and output state transitions. ACS unit include the Path Metric Unit (PMU), which computes the metrics with the sequence to a next state of a path and selects the lower metric value as a survivor path. SMU stores the data bits which utilizes the trace back method to fetch the likelihood path from the current state to a previous state. An ACS unit is an essential block for VD. The basic recursive ACSU design consists of Ripple Carry Adder (RCA), Comparator and a Selector block, which consume more area, power and operates with high junction temperature. To overcome these drawbacks, a modified ACSU design is implemented with recursive cancellation technique. ACS unit is modified by including a trace back mechanism to obtain a low latency and high speed in VD. It is designed with low complexity multiplexers, adders, logical AND gate and comparator block. This breaking recursive ACSU design utilizes less power, high throughput, low latency and also operates at low temperature. This analysis and simulation process are accomplished using Vivado Design Suite.
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Bibilo, P. N., Yu Yu Lankevich, and V. I. Romanov. "Logical minimization for combinatorial structure in FPGA." Informatics 18, no. 1 (2021): 7–24. http://dx.doi.org/10.37661/1816-0301-2021-18-1-7-24.
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The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA. Programs are designed for shared and separated function minimization in a disjunctive normal form (DNF) class and minimization of multilevel representations of fully defined Boolean functions based on Shannon expansion with finding equal and inverse cofactors. The graphical form of such representations is widely known as binary decision diagrams (BDD). For technological mapping the program of "enlargement" of obtained Shannon expansion formulas was applied in a way that each of them depends on a limited number of k input variables and can be implemented on one LUT-k – a programmable unit of FPGA with k input variables. It is shown that a preliminary logic minimization, which is performed on the domestic programs, allows improving design results of foreign CAD systems such as Leonardo Spectrum (Mentor Graphics), ISE (Integrated System Environment) Design Suite and Vivado (Xilinx). The experiments were performed for FPGA families’ Virtex-II PRO, Virtex-5 and Artix-7 (Xilinx) on standard threads of industrial examples, which define both DNF systems of Boolean functions and systems represented as interconnected logical equations.
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Marinova, Galia, and Zdravka Tchobanova. "Circuit Design for Green Communications – Methods, Tools and Examples." Spring 2017 5, no. 2 (2017): 1–11. http://dx.doi.org/10.33107/ijbte.2017.5.2.01.
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The paper makes an overview of the existing methods applied for circuit design with low power consumption objective. It considers Computer-Aided Design (CAD) tools and modules for power consumption estimation at the design stage. For analog and mixed analog-digital circuit design, the power estimation options in ORCAD Design Suit with PSpice and Analog Filter Wizard are studied. For digital communication systems the study covers the power estimation, analysis and optimization in ISE and Vivado systems, Xilinx Power Estimator (XPE) tool and spreadsheet, the XPower Analyzer, as well as similar tools proposed by ALTERA - PowerPlay Early Power Estimator and QUARTUS II Power Play Power Analyzer. Two examples are developed: Power consumption estimation of a Universal Software Radio Peripheral (USRP)-based communication system design, based on datasheets and software energy monitoring tools, and power consumption estimation of a Kasami pseudo-random sequence generator circuit design on FPGA using Vivado.
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Rajashekhar, U., and Neelappa Neelappa. "Development of Automated BCI System to Assist the Physically Challenged Person Through Audio Announcement With Help of EEG Signal." WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL 16 (May 26, 2021): 302–14. http://dx.doi.org/10.37394/23203.2021.16.26.
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Individuals face numerous challenges with many disorders, particularly when multiple disfunctions are diagnosed and especially for visually effected wheelchair users. This scenario, in reality creates in a degree of incapacity on the part of the wheelchair user in terms of performing simple activities. Based on their specific medical needs confined patients are treated in a modified method. Independent navigation is secured for individuals with vision and motor disabilities. There is a necessity for communication which justifies the use of virtual reality (VR) in this navigation situation. For the effective integration of locomotion besides, it must be under natural guidance. Electroencephalography (EEG), which uses random brain impulses, has made significant progress in the field of health. The custom of an automated audio announcement system modified to have the help of Virtual Reality (VR) and EEG for training of locomotion and individualised interaction of wheelchair users with visual disability is demonstrated in this study through an experiment. Enabling the patients who were otherwise deemed incapacitated to participate in social activities, as the aim was to have efficient connections. The natural control, feedback, stimuli, and protection these subsequent principles founded this project. Via properly conducted experiments, a multilayer computer rehabilitation system was created that integrated natural interaction assisted by EEG, which enabled the movements in the virtual environment and real wheelchair. For blind wheelchair operator patients this study involved of expounding the proper methodology. For educating the value of life and independence of blind wheelchair users, outcomes proven that VR with EEG signals has that potential. To protect their life straightaway and to report all these disputes, the military system should have high speed, more precise portable prototype device for nursing the soldier health, recognition of solider location and report about health sharing system to the concerned system. FPGA-based soldier’s health observing and position gratitude system is proposed in this paper. Reliant on heart rate which is centred on EEG signals the soldier health is observed in systematic bases. By emerging Verilog HDL programming language and executing on Artix-7 development FPGA board of part name XC7ACSG100t the whole work is approved in a Vivado Design Suite. Classification of different abnormalities, and cloud storage of EEG along with type of abnormalities, artifact elimination, abnormalities identification based on feature extraction, exist in the segment of suggested architecture. Irregularity circumstances are noticed through developed prototype system and alert the physically challenged (PHC) individual via audio announcement. An actual method for eradicating motion artefacts from EEG signals that have anomalies in the PHC person's brain has been established, and the established system is a portable device that can deliver differences in brain signal variation intensity. Primarily the EEG signals can be taken and the undesirable artifact can be detached, later structures can be mined by DWT these are the two stages through which artifact deletion can be completed. The anomalies in signal can be noticed and recognized by using machine learning algorithms known as Multirate SVM classifiers, when the features have been extracted using a combination of HMM and GMM. Intended for capable declaration about action taken by a blind person, these result signals are protected in storage devices and conveyed to the controller. Pretending daily motion schedules allows the pretentious EEG signals to be caught. Aimed at the validation of planned system, the database can be used and continued with numerous recorded signals of EEG. The projected strategy executes better in terms of re-storing theta, delta, alpha, and beta (TDAB) complexes of the original EEG with less alteration and a higher signal to noise ratio (SNR) value of the EEG signal which illustrates in the quantitative analysis. The projected method used Verilog HDL and MATLAB software for both formation and authorization of results in order to yield improved results. Since from the achieved results, it is initiated that 32% enhancement in SNR, 14% in MSE and 65% enhancement in recognition of anomalies, hence design is effectively certified and proved for standard EEG signals datasets on FPGA.
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İlarslan, Mustafa, A. Serdar Türk, Salih Demirel, M. Emre Aydemir, and A. Kenan Keskin. "A Compact Vivaldi Shaped Partially Dielectric Loaded TEM Horn Antenna for UWB Communication." International Journal of Antennas and Propagation 2014 (2014): 1–6. http://dx.doi.org/10.1155/2014/847169.
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Ultrawideband (UWB) antennas are of huge demand and Vivaldi antennas as well as the TEM horn antennas are good candidates for UWB applications as they both have relatively simple geometry and high gain over a wide bandwidth. The aim of this study is to design a compact antenna that achieves maximum gain over a bandwidth between 1.5 and 10.6 GHz while minimizing its size. The idea is to make use of combined respective advantages of Vivaldi and TEM horn antennas to achieve the desired goals by shaping the TEM horn antenna to look like a Vivaldi antenna. The antenna structure is modified by a dielectric load in the center to increase the gain bandwidth. It is placed in a surrounding box made of PEC material to reduce the undesired side lobes and to obtain more directive radiation pattern. The simulations are performed by using the CST STUDIO SUITE electromagnetic (EM) simulation software and they are later verified by the actual measurements. The Vivaldi shaped partially dielectric loaded (VS-PDL) TEM horn antenna is proposed as a compact UWB antenna for systems using the newly established UWB band and also for the communication systems of popular bands like ISM, Wi-Fi, and GSM.
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"A Systematic Method for Hardware Software Codesign using Vivado HLS." International Journal of Recent Technology and Engineering 8, no. 4 (2019): 467–72. http://dx.doi.org/10.35940/ijrte.d7008.118419.
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This paper aims to provide increased productivity for designing, integrating and implementing systems using xilinx vivado design suite. It can accelerate design implementation with place and route tools that analytically optimize for multiple and concurrent design metrics such as timing, congestion, total wire length, utilization and power; it also provides design analysis capabilities at each design stage. An overview of vivado design suite is illustrated with configuration, implementation, detailed implementation, summary, settings along with component name. Here the component DDS compiler has been chosen and the waveform repository, design settings are added to it. Improved productivity results are indicated through simulation, synthesis, implementation, bitstream generation.
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Rakesh, S., and K. S. Vijula Grace. "Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit." Journal of Circuits, Systems and Computers, July 29, 2021, 2250016. http://dx.doi.org/10.1142/s0218126622500165.
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Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.
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"Euler and RK4 Algorithms Based Implementation of Autonomous Chaotic Generator." International Journal of Engineering and Advanced Technology 8, no. 6 (2019): 4161–65. http://dx.doi.org/10.35940/ijeat.f9316.088619.
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Chaotic systems plays a vital role in the field of security, data hiding and steganography. FPGA implementation makes more advantageous compared to analog one. Different chaotic systems like chaos generator and nondeterministic number generator used for security purpose and key generation were successfully realized in FPGA. In this paper, FPGA implementation of Pandey-Baghel-Singh chaotic system (PBSCS) using Euler and RK4 numerical algorithms is presented. Pandey-Baghel-Singh chaotic system were obtained using numerical differential solution and numerically modelled in Verilog with the environment of Xilinx Vivado 2017.3 design suite. The design is verified using experimental setup with the help of interfacing to PC and FPGA family of Artix-7 Nexys 4 DDR and Basys3. Performance of the FPGA based chaotic generator using Euler and RK4 algorithm are analyzed using 1 GB data sets with the maximum operating frequency achieved up to 359.71 MH
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"Ternary Content Addressable Memory." Special 9, no. 4s (2020): 12–16. http://dx.doi.org/10.35940/ijeat.a1004.0594s20.
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Memory Technology plays a vital role in fast searching applications. Content Addressable Memory (CAM) is a special type of memory used for search operation. CAM provides access to the stored data by its content instead of the address. Advanced version of CAM is known as Ternary CAM (TCAM) which is a memory that can also store don’t care bit. TCAM is most relevant in routers in networking applications. Review of TCAM design techniques at different aspects are carried out, and obtained that an Energy Efficient TCAM (EE-TCAM) is the one which is having less power consumption. Compared with other SRAM-based TCAM designs, EE-TCAM use up reduced energy as it selectively activates only one row of SRAM at a time for search operation instead of activating the whole SRAM memory as in the other architectures. Partitioning of the TCAM table, designing of a pre-classifier and memory mapping are done prior to the work. This paper focuses on designing an EE-TCAM using Verilog HDL on Zybo7000 platform using Vivado design suite. Functional analysis of a 6*6 EE-TCAM is performed and power, delay and resource utilization are obtained. From the obtained results it is clear that EE-TCAM is having very less power and delay.
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Nayak, Jayant Kumar, Vatsala Prasad, and Ranjan Ganguli. "A Field Programmable Gate Array (FPGA) Based Non-Linear Filters for Gas Turbine Prognostics." International Journal of Prognostics and Health Management 12, no. 3 (2021). http://dx.doi.org/10.36001/ijphm.2021.v12i3.2960.
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The removal of noise from signals obtained through the health monitoring systems in gas turbines is an important consideration for accurate prognostics. Several filters have been designed and tested for this purpose, and their performance analysis has been conducted. Linear filters are inefficient in the removal of outliers and noise because they cause smoothening of the sharp features in the signal which can indicate the onset of a fault event. On the other hand, non-linear filters based on image processing methods can provide more precise results for gas turbine health signals. Among others, the weighted recursive median (WRM) filter has been shown to provide greater accuracy due to its weight adaptability depending on the signal type. However, sampling data at high rates is possible which needs hardware implementation of the filter. In this paper, the design, simulation and implementation of WRM filters on the FPGA (Field Programmable Gate Arrays) platforms Vivado Design Suite by Xilinx and Quartus Pro Lite Edition 19.3 has been performed. The architectural detail and performance result with the FPGA filters when subjected to abrupt and gradual fault signal is presented.
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Yu, Fei, Zinan Zhang, Hui Shen, et al. "Design and FPGA Implementation of a Pseudo-random Number Generator Based on a Hopfield Neural Network Under Electromagnetic Radiation." Frontiers in Physics 9 (June 4, 2021). http://dx.doi.org/10.3389/fphy.2021.690651.
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When implementing a pseudo-random number generator (PRNG) for neural network chaos-based systems on FPGAs, chaotic degradation caused by numerical accuracy constraints can have a dramatic impact on the performance of the PRNG. To suppress this degradation, a PRNG with a feedback controller based on a Hopfield neural network chaotic oscillator is proposed, in which a neuron is exposed to electromagnetic radiation. We choose the magnetic flux across the cell membrane of the neuron as a feedback condition of the feedback controller to disturb other neurons, thus avoiding periodicity. The proposed PRNG is modeled and simulated on Vivado 2018.3 software and implemented and synthesized by the FPGA device ZYNQ-XC7Z020 on Xilinx using Verilog HDL code. As the basic entropy source, the Hopfield neural network with one neuron exposed to electromagnetic radiation has been implemented on the FPGA using the high precision 32-bit Runge Kutta fourth-order method (RK4) algorithm from the IEEE 754-1985 floating point standard. The post-processing module consists of 32 registers and 15 XOR comparators. The binary data generated by the scheme was tested and analyzed using the NIST 800.22 statistical test suite. The results show that it has high security and randomness. Finally, an image encryption and decryption system based on PRNG is designed and implemented on FPGA. The feasibility of the system is proved by simulation and security analysis.
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"Design an All Digital PLL with Ripple Reduction Technique." VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE 8, no. 10 (2019): 3164–68. http://dx.doi.org/10.35940/ijitee.j9518.0881019.
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The article describes about the design and implementation of advance version of Phase Lock Loop (PLL) is All Digital PLL. Research work is on ADPLL where parameter ripple is reduced by applying the technique of ripple reduction technique. Ripple reduction technique reduces the use of Kth counter, Kth counter comes under consideration when enable is ON. Phase locked loops are most widely used in communication system. Most of the PLL’s that are used currently are hybrid type PLL’s where all the blocks are assumed to be digital. The circuit design of ADPLL consists of Digital Controlled Oscillator (DCO), loop filter and Phase Frequency detector (PFD). Here phase detector used is Ex-or gate, for loop filter, Kth counter is used and Increment/Decrement circuit is used as DCO. Divide-by-N counter is used for feedback system. The output of the DCO is going in the PFD through the feedback network. Xilinx Vivado suit 2018.2 tools is used for simulating Verilog code. Board chosen in vivado is zed board Zynq. First, with the help of circuit diagram of ADPLL Verilog code is being written on project window. After compilation of code it is simulated with the help of test bench. After that it is going to be implemented and verified with the board zedboard. Number of LUTs used are 32 and Flip Flops used are 35. This paper presents an all digital approach for the design, simulation, synthesis and implementation of FPGA based ADPLL centered at 195.31 KHz using Verilog HDL code. The proposed design methodology resulted in reduction of ripple, power dissipation, junction temperature of board. Proposed research work further can be used in communication for frequency synthesizer. Any system whether it is from communication or digital etc ADPLL is common to use for ripple reduction at its output. So ADPLL is basic building block in any type of communication system.
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Prongnuch, Sethakarn, and Suchada Sitjongsataporn. "Exterior Car Parking Assistance Algorithm Based on Reconfigurable System for Future Industry." Journal of Mobile Multimedia, August 21, 2020. http://dx.doi.org/10.13052/jmm1550-4646.161210.
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A car accident while parking the car is caused by the car driver, who is invisible around the car. However, there are no solutions for parking assistance when the driver is outside the car. The objective of this paper is to propose a reconfigurable embedded system design by voice controlled parking assistance system for a prototype electric vehicle connected to a smartphone via Bluetooth. Hardware and software co-design using the Xilinx VIVADO as a software design tool is introduced. We design the hardware and software on an ARM multicore processor and the reconfigurable system board model ZYBO: XC7Z010 by considering it as hardware accelerator. The hardware of the proposed voice controlled exterior car parking assistance system is installed on the miniature electric vehicle. The experiments are tested successfully at the parking area for both reverse parking and reverse parallel parking. This proposed system is better suited for users so that they can control their car comfortably while parking safely.