Log in

Relevant bibliographies by topics / VLSI analog circuits / Journal articles

To see the other types of publications on this topic, follow the link: VLSI analog circuits.

Journal articles on the topic 'VLSI analog circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'VLSI analog circuits.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Bartolozzi, Chiara, and Giacomo Indiveri. "Synaptic Dynamics in Analog VLSI." Neural Computation 19, no. 10 (2007): 2581–603. http://dx.doi.org/10.1162/neco.2007.19.10.2581.

Full text

Abstract:

Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.

APA, Harvard, Vancouver, ISO, and other styles

2

Chieh-Yuan Chao, Hung-Jen Lin, and L. Miler. "Optimal testing of VLSI analog circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, no. 1 (1997): 58–77. http://dx.doi.org/10.1109/43.559332.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Zarabadi, S. R., M. Ismail, and Chung-Chih Hung. "High performance analog VLSI computational circuits." IEEE Journal of Solid-State Circuits 33, no. 4 (1998): 644–49. http://dx.doi.org/10.1109/4.663572.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Card, H. C., and W. R. Moore. "VLSI DEVICES AND CIRCUITS FOR NEURAL NETWORKS." International Journal of Neural Systems 01, no. 02 (1989): 149–65. http://dx.doi.org/10.1142/s0129065789000062.

Full text

Abstract:

This paper provides a tutorial of various VLSI approaches to synthesizing artificial neural networks as microelectronic systems. The means by which the network learns and the synaptic weights become modified is a central theme in this study. The majority of the presentation is concerned with analog circuit approaches to neurons and synapses, employing CMOS circuits. Also included is recent work towards VLSI in situ learning circuits which implement qualitative approximations to Hebbian learning with economy of transistors. An attempt is also made to anticipate relevant developments in VLSI devices which would be suited to neural networks, just as conventional MOS transistors are well suited to traditional digital computer systems.

APA, Harvard, Vancouver, ISO, and other styles

5

Vasudeva, G., and Uma B. V. "22nm FINFET Based High Gain Wide Band Differential Amplifier." International Journal of Circuits, Systems and Signal Processing 15 (February 5, 2021): 55–62. http://dx.doi.org/10.46300/9106.2021.15.7.

Full text

Abstract:

Differential Amplifier is a primary building block of analog and mixed signal circuit for pre-processing and signal conditioning of analog signal. FINFET devices with high-k gate oxide at 22nm technology are predominantly used for high speed and low power complex VLSI circuits. FINFET based differential amplifiers are widely used in ADC’s and signal Processing applications due to their advantages in terms of power dissipation. Analog front end of complex VLSI circuits need to offer high gain, higher stability and low noise figure. Designing of FINFET based VLSI sub-circuits requires proper design procedure that can provide designers flexibility in controlling the circuit performances. In this paper, differential amplifier is designed using model parameters of high-k FINFET in 22nm technology. The conventional procedures for designing MOSFET based differential amplifier are modified for designing FINFET based differential amplifier. Schematic capture is carried out in Cadence environment and simulations are obtained considering 22nm FINFET PDK. The performance metrics are evaluated and optimized considering multiple iterations. The designed differential amplifier has slew rate of 6V/µSec and settling time of 0.9 µSec which is a desired metric for ADCs. Power Supply Rejection Ratio (PSRR) is 83 dB and dynamic range is 1.6754 V. Open loop DC gain of DA is achieved to be 103 dB with phase margin of 630 that demonstrates the advantages of DA designed in this work suitable for analog front end

APA, Harvard, Vancouver, ISO, and other styles

6

Maher, M. A. C., S. P. Deweerth, M. A. Mahowald, and C. A. Mead. "Implementing neural architectures using analog VLSI circuits." IEEE Transactions on Circuits and Systems 36, no. 5 (1989): 643–52. http://dx.doi.org/10.1109/31.31311.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Indiveri, Giacomo. "Modeling Selective Attention Using a Neuromorphic Analog VLSI Device." Neural Computation 12, no. 12 (2000): 2857–80. http://dx.doi.org/10.1162/089976600300014755.

Full text

Abstract:

Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

APA, Harvard, Vancouver, ISO, and other styles

8

Koch, Christof. "Seeing Chips: Analog VLSI Circuits for Computer Vision." Neural Computation 1, no. 2 (1989): 184–200. http://dx.doi.org/10.1162/neco.1989.1.2.184.

Full text

Abstract:

Vision is simple. We open our eyes and, instantly, the world surrounding us is perceived in all its splendor. Yet Artificial Intelligence has been trying with very limited success for over 20 years to endow machines with similar abilities. A large van, filled with computers and driving unguided at a mile per hour across gently sloping hills in Colorado and using a laser-range system to “see” is the most we have accomplished so far. On the other hand, computers can play a decent game of chess or prove simple mathematical theorems. It is ironic that we are unable to reproduce perceptual abilities which we share with most animals while some of the features distinguishing us from even our closest cousins, chimpanzees, can be carried out by machines. Vision is difficult.

APA, Harvard, Vancouver, ISO, and other styles

9

Ismail, Mohammed, Robert Brannen, Shigetaka Takagi, et al. "Configurable CMOS multiplier/divider circuits for analog VLSI." Analog Integrated Circuits and Signal Processing 5, no. 3 (1994): 219–34. http://dx.doi.org/10.1007/bf01261414.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Lopez-Martin, Antonio J., and Alfonso Carlosena. "Design of MOS-translinear Multiplier/Dividers in Analog VLSI." VLSI Design 11, no. 4 (2000): 321–29. http://dx.doi.org/10.1155/2000/21852.

Full text

Abstract:

A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-μm CMOS process, are provided in order to verify the correctness of the proposed approach.

APA, Harvard, Vancouver, ISO, and other styles

11

Horiuchi, Timothy K., and Christof Koch. "Analog VLSI-Based Modeling of the Primate Oculomotor System." Neural Computation 11, no. 1 (1999): 243–65. http://dx.doi.org/10.1162/089976699300016908.

Full text

Abstract:

One way to understand a neurobiological system is by building a simulacrum that replicates its behavior in real time using similar constraints. Analog very large-scale integrated (VLSI) electronic circuit technology provides such an enabling technology. We here describe a neuromorphic system that is part of a long-term effort to understand the primate oculomotor system. It requires both fast sensory processing and fast motor control to interact with the world. A one-dimensional hardware model of the primate eye has been built that simulates the physical dynamics of the biological system. It is driven by two different analog VLSI chips, one mimicking cortical visual processing for target selection and tracking and another modeling brain stem circuits that drive the eye muscles. Our oculomotor plant demonstrates both smooth pursuit movements, driven by a retinal velocity error signal, and saccadic eye movements, controlled by retinal position error, and can reproduce several behavioral, stimulation, lesion, and adaptation experiments performed on primates.

APA, Harvard, Vancouver, ISO, and other styles

12

Deweerth, Stephen P. "Analog VLSI circuits for stimulus localization and centroid computation." International Journal of Computer Vision 8, no. 3 (1992): 191–202. http://dx.doi.org/10.1007/bf00055151.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Andreou, Andreas G., and Kwabena A. Boahen. "Synthetic Neural Circuits Using Current-Domain Signal Representations." Neural Computation 1, no. 4 (1989): 489–501. http://dx.doi.org/10.1162/neco.1989.1.4.489.

Full text

Abstract:

We present a new approach to the engineering of collective analog computing systems that emphasizes the role of currents as an appropriate signal representation and the need for low-power dissipation and simplicity in the basic functional circuits. The design methodology and implementation style that we describe are inspired by the functional and organizational principles of neuronal circuits in living systems. We have implemented synthetic neurons and synapses in analog CMOS VLSI that are suitable for building associative memories and self-organizing feature maps.

APA, Harvard, Vancouver, ISO, and other styles

14

Rajendran, Selvakumar, Arvind Chakrapani, Srihari Kannan, and Abdul Quaiyum Ansari. "A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 14, no. 4 (2021): 377–97. http://dx.doi.org/10.2174/2352096514666210127140831.

Full text

Abstract:

Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in μm and nm technology. The current mirror (CM) is a basic building block used to enhance performance characteristics by constructing complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technologybased current mirror (CM) circuits are discussed with their advantages and disadvantages accompanied by the performance analysis of different parameters. It also briefs various techniques which are employed for improvising the current mirror performance like gain boosting and bandwidth extension. Besides, this paper lists the CMs that use different types of MOS devices like Floating Gate MOS, Bulk-driven MOS, and Quasi-Floating Gate MOS. As a result, the paper performs a detailed review of CMOS Current mirrors and their techniques. Results: Basic CM circuits that can act as building blocks in the VLSI circuits are simulated using 0.25 μm, BSIM and Level 1 technology. In addition, various devices based CMs are investigated and compared. Conclusion: The comprehensive discussion shows that the current mirror plays a significant role in analog/mixed-signal circuits design to realize complex systems for low-power biomedical and wireless applications.

APA, Harvard, Vancouver, ISO, and other styles

15

Li, Mu, Yigang He, and Ying Long. "Analog VLSI implementation of wavelet transform using switched-current circuits." Analog Integrated Circuits and Signal Processing 71, no. 2 (2011): 283–91. http://dx.doi.org/10.1007/s10470-011-9705-7.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Andreou, A. G., K. A. Boahen, P. O. Pouliquen, A. Pavasovic, R. E. Jenkins, and K. Strohbehn. "Current-mode subthreshold MOS circuits for analog VLSI neural systems." IEEE Transactions on Neural Networks 2, no. 2 (1991): 205–13. http://dx.doi.org/10.1109/72.80331.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Boahen, K. A., P. O. Pouliquen, A. G. Andreou, and R. E. Jenkins. "A heteroassociative memory using current-mode MOS analog VLSI circuits." IEEE Transactions on Circuits and Systems 36, no. 5 (1989): 747–55. http://dx.doi.org/10.1109/31.31323.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Chiblè, H., and A. Ghandour. "Different Analog Signal Processing Mathematical Functions with CMOS VLSI Circuits." International Journal of Modelling and Simulation 29, no. 3 (2009): 227–37. http://dx.doi.org/10.1080/02286203.2009.11442528.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Jabri, Marwan, and Barry Flower. "Weight Perturbation: An Optimal Architecture and Learning Technique for Analog VLSI Feedforward and Recurrent Multilayer Networks." Neural Computation 3, no. 4 (1991): 546–65. http://dx.doi.org/10.1162/neco.1991.3.4.546.

Full text

Abstract:

Previous work on analog VLSI implementation of multilayer perceptrons with on-chip learning has mainly targeted the implementation of algorithms like backpropagation. Although backpropagation is efficient, its implementation in analog VLSI requires excessive computational hardware. In this paper we show that, for analog parallel implementations, the use of gradient descent with direct approximation of the gradient using “weight perturbation” instead of backpropagation significantly reduces hardware complexity. Gradient descent by weight perturbation eliminates the need for derivative and bidirectional circuits for on-chip learning, and access to the output states of neurons in hidden layers for off-chip learning. We also show that weight perturbation can be used to implement recurrent networks. A discrete level analog implementation showing the training of an XOR network as an example is described.

APA, Harvard, Vancouver, ISO, and other styles

20

Singh, Anil, Ayushi Goel, and Alpana Agarwal. "A Digital-Based Low-Power Fully Differential Comparator." Journal of Circuits, Systems and Computers 26, no. 01 (2016): 1750002. http://dx.doi.org/10.1142/s0218126617500025.

Full text

Abstract:

Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in Cadence[Formula: see text] Virtuoso Analog Design Environment using UMC 180[Formula: see text]nm CMOS technology at 1.8[Formula: see text]V supply.

APA, Harvard, Vancouver, ISO, and other styles

21

Jyhfong Lin, Wing-Hung Ki, T. Edwards, and S. Shamma. "Analog VLSI implementations of auditory wavelet transforms using switched-capacitor circuits." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 41, no. 9 (1994): 572–83. http://dx.doi.org/10.1109/81.317956.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Indiveri, G. "Neuromorphic analog VLSI sensor for visual tracking: circuits and application examples." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46, no. 11 (1999): 1337–47. http://dx.doi.org/10.1109/82.803473.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Kalpana, P., and K. Gunavathi. "Wavelet based fault detection in analog VLSI circuits using neural networks." Applied Soft Computing 8, no. 4 (2008): 1592–98. http://dx.doi.org/10.1016/j.asoc.2007.10.023.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

McCarthy, T. "Design of analog-digitaal VLSI circuits for telecommunications and signal processing." Microelectronics Journal 26, no. 5 (1995): xxii—xxiii. http://dx.doi.org/10.1016/0026-2692(95)90055-1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Yoon, Kwang S., and Phillip E. Allen. "An adjustable accuracy model for VLSI analog circuits using lookup tables." Analog Integrated Circuits and Signal Processing 1, no. 1 (1991): 45–63. http://dx.doi.org/10.1007/bf02151025.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Abo El-sSoud, Mohy El-Din, Hassan Soliman, Laila El-ghanam, and Roshdy AbdelRassoul. "Low-Voltage CMOS Circuits for Analog VLSI Programmable Neural Networks.(Dept.E)." MEJ. Mansoura Engineering Journal 28, no. 4 (2021): 21–30. http://dx.doi.org/10.21608/bfemu.2021.142391.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Kanazawa, Yusuke, Tetsuya Asai, and Yoshihito Amemiya. "Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses." Journal of Robotics and Mechatronics 15, no. 2 (2003): 208–18. http://dx.doi.org/10.20965/jrm.2003.p0208.

Full text

Abstract:

We discuss the integration architecture of spiking neurons, predicted to be next-generation basic circuits of neural processor and dynamic synapse circuits. A key to development of a brain-like processor is to learn from the brain. Learning from the brain, we try to develop circuits implementing neuron and synapse functions while enabling large-scale integration, so large-scale integrated circuits (LSIs) realize functional behavior of neural networks. With such VLSI, we try to construct a large-scale neural network on a single semiconductor chip. With circuit integration now reaching micron levels, however, problems have arisen in dispersion of device performance in analog IC and in the influence of electromagnetic noise. A genuine brain computer should solve such problems on the network level rather than the element level. To achieve such a target, we must develop an architecture that learns brain functions sufficiently and works correctly even in a noisy environment. As the first step, we propose an analog circuit architecture of spiking neurons and dynamic synapses representing the model of artificial neurons and synapses in a form closer to that of the brain. With the proposed circuit, the model of neurons and synapses can be integrated on a silicon chip with metal-oxide-semiconductor (MOS) devices. In the sections that follow, we discuss the dynamic performance of the proposed circuit by using a circuit simulator, HSPICE. As examples of networks using these circuits, we introduce a competitive neural network and an active pattern recognition network by extracting firing frequency information from input information. We also show simulation results of the operation of networks constructed with the proposed circuits.

APA, Harvard, Vancouver, ISO, and other styles

28

Raj, Baldev, G. M. Bhat, and Sandeep Thakur. "Fault modeling and parametric fault detection in analog VLSI circuits using discretization." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 3 (2019): 1598. http://dx.doi.org/10.11591/ijece.v9i3.pp1598-1605.

Full text

Abstract:

<p>In this article we describe new model for determination of fault in circuit and also we provide detailed analysis of tolerance of circuit, which is considered one of the important parameter while designing the circuit. We have done mathematical analysis to provide strong base for our model and also done simulation for the same. This article describes detailed analysis of parametric fault in analog VLSI circuit. The model is tested for different frequencies for compactness and its flexibility. The tolerance analysis is also done for this purpose. All the simulation are done in MATLAB software.</p>

APA, Harvard, Vancouver, ISO, and other styles

29

De, Bishnu Prasad, Kanchan Baran Maji, Rajib Kar, Durbadal Mandal, and Sakti Prasad Ghoshal. "Design of Optimal CMOS Analog Amplifier Circuits Using a Hybrid Evolutionary Optimization Technique." Journal of Circuits, Systems and Computers 27, no. 02 (2017): 1850029. http://dx.doi.org/10.1142/s0218126618500299.

Full text

Abstract:

This paper proposes an efficient design technique for two commonly used VLSI circuits, namely, CMOS current mirror load-based differential amplifier circuit and CMOS two-stage operational amplifier. The hybrid evolutionary method utilized for these optimal designs is random particle swarm optimization with differential evolution (RPSODE). Random PSO utilizes the weighted particles for monitoring the search directions. DE is a robust evolutionary technique. It has demonstrated an exclusive performance for the optimization problems which are continuous and global but suffers from the uncertainty issues. PSO is a robust optimization method but suffers from sub-optimality problem. This paper effectively hybridizes the random PSO and DE to remove the limitations related to both the techniques individually. In this paper, RPSODE is employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained from RPSODE technique are validated in SPICE environment. SPICE-based simulation results justify that RPSODE is a much better technique than other formerly reported methods for the designs of the above mentioned circuits in terms of MOS area, gain, power dissipation, etc.

APA, Harvard, Vancouver, ISO, and other styles

30

Salmanpour, Ava, Ebrahim Farshidi, and Karim Ansari Asl. "A New Low Voltage Analog Circuit Model for Hodgkin–Huxley Neuron Employing FGMOS Transistors." Journal of Circuits, Systems and Computers 27, no. 09 (2018): 1850141. http://dx.doi.org/10.1142/s0218126618501414.

Full text

Abstract:

A low voltage analog VLSI circuit model for Hodgkin–Huxley (HH) neuron cell equations (HH neuron model) is presented. Floating gate MOSFET (FGMOS) transistors in weak inversion region have been used to model HH equations such as gating variables, [Formula: see text] and [Formula: see text] functions and combined action of [Formula: see text], [Formula: see text] and [Formula: see text]. The combination of [Formula: see text], [Formula: see text] and [Formula: see text] controls the Na[Formula: see text] and K[Formula: see text] channel currents. The superiorities of the proposed circuits are low supply voltage, low power consumption, less circuit complexity and as a result, low costs are compared to the previous works. The proposed circuit which uses 24 transistors is simulated in Hspice software using 0.18[Formula: see text] technology and consumes 119[Formula: see text][Formula: see text]W.

APA, Harvard, Vancouver, ISO, and other styles

31

Kalpana, Palanisamy, and Kandasamy Gunavathi. "Test-Generation-Based Fault Detection in Analog VLSI Circuits Using Neural Networks." ETRI Journal 31, no. 2 (2009): 209–14. http://dx.doi.org/10.4218/etrij.09.0108.0383.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Raffo, L., S. P. Sabatini, G. M. Bo, and G. M. Bisio. "Analog VLSI circuits as physical structures for perception in early visual tasks." IEEE Transactions on Neural Networks 9, no. 6 (1998): 1483–94. http://dx.doi.org/10.1109/72.728397.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Van Peteghem, P. M., and J. F. Duque-Carrillo. "Compact high-frequency output buffer for testing of analog CMOS VLSI circuits." IEEE Journal of Solid-State Circuits 24, no. 2 (1989): 540–42. http://dx.doi.org/10.1109/4.18620.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Deweerth, Stephen P. "Converting spatially encoded sensory information to motor signals using analog VLSI circuits." Autonomous Robots 2, no. 2 (1995): 93–104. http://dx.doi.org/10.1007/bf00735429.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Vineela, J., G. Praneetha, R. Harshad, K. Masrunnisa, M. Pruthvi Kumar, and T. Sandeep. "A Complete Analysis of Tolerance of Component in Analog VLSI Circuits Using Sensitivity." International Journal of Hybrid Information Technology 9, no. 7 (2016): 9–18. http://dx.doi.org/10.14257/ijhit.2016.9.7.02.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Thakur, Sandeep. "A Comprehensive Approach for Modeling and Diagnosis of Various Faults in Analog VLSI Circuits." International Journal of Signal Processing, Image Processing and Pattern Recognition 9, no. 10 (2016): 97–108. http://dx.doi.org/10.14257/ijsip.2016.9.10.10.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Thakur, Sandeep. "A Complete Monte Carlo and Sensitivity Analysis of Various Elements in Analog VLSI Circuits." International Journal of u- and e- Service, Science and Technology 9, no. 11 (2016): 239–50. http://dx.doi.org/10.14257/ijunesst.2016.9.11.21.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Maass, Wolfgang. "On the Computational Power of Winner-Take-All." Neural Computation 12, no. 11 (2000): 2519–35. http://dx.doi.org/10.1162/089976600300014827.

Full text

Abstract:

This article initiates a rigorous theoretical analysis of the computational power of circuits that employ modules for computing winner-take-all. Computational models that involve competitive stages have so far been neglected in computational complexity theory, although they are widely used in computational brain models, artificial neural networks, and analog VLSI. Our theoretical analysis shows that winner-take-all is a surprisingly powerful computational module in comparison with threshold gates (also referred to as McCulloch-Pitts neurons) and sigmoidal gates. We prove an optimal quadratic lower bound for computing winner-takeall in any feedforward circuit consisting of threshold gates. In addition we show that arbitrary continuous functions can be approximated by circuits employing a single soft winner-take-all gate as their only nonlinear operation. Our theoretical analysis also provides answers to two basic questions raised by neurophysiologists in view of the well-known asymmetry between excitatory and inhibitory connections in cortical circuits: how much computational power of neural networks is lost if only positive weights are employed in weighted sums and how much adaptive capability is lost if only the positive weights are subject to plasticity.

APA, Harvard, Vancouver, ISO, and other styles

39

Kraus, W., and D. Schmitt-Landsiedel. "Influence of gate tunneling currents on switched capacitor integrators." Advances in Radio Science 7 (May 19, 2009): 225–29. http://dx.doi.org/10.5194/ars-7-225-2009.

Full text

Abstract:

Abstract. In order to achieve a higher level of integration in modern VLSI systems, not only the lateral geometrical dimensions have to be scaled. Lowering the supply voltage also requires scaling down the oxide thickness of the transistors. While the oxide thickness is scaled down proportionally with the supply voltage, the gate tunneling currents grow exponentially, which results in special issues concerning deviations in charge based analog and mixed signal circuitry. The influence of gate tunneling currents on this kind of circuits will be demonstrated at a fully differential switched capacitor integrator. The used process data is derived from the International Technology Roadmap for Semiconductors (ITRS Roadmap, 2006). The Parameter sets for the simulations are based on the Predictive Technology Model of the Arizona State University Modelling Group for the 65 nm Technology node (Predictive Technology Model, 2008).

APA, Harvard, Vancouver, ISO, and other styles

40

Sivaganesan S, Maria Antony S, and Udayakumar E. "An Event-Based Neural Network Architecture with Content Addressable Memory." International Journal of Embedded and Real-Time Communication Systems 11, no. 1 (2020): 23–40. http://dx.doi.org/10.4018/ijertcs.2020010102.

Full text

Abstract:

A hybrid analog/digital very large-scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights was designed. The synaptic weight values are stored in an asynchronous module, which is interfaced to a fast current-mode event-driven DAC for producing synaptic currents with the appropriate amplitude values. It acts as a transceiver, receiving asynchronous events for input, performing neural computations with hybrid analog/digital circuits on the input spikes, and eventually producing digital asynchronous events in output. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the address event representation (AER). Using this representation, it is possible to interface the device to a workstation or a microcontroller and explore the effect of different types of spike-timing dependent plasticity (STDP) learning algorithms for updating the synaptic weights values in the CAM module.

APA, Harvard, Vancouver, ISO, and other styles

41

Bowman, Jesse, and A. Ege Engin. "Virtual Ground Fence: A Simple Method for Protection against High Frequency Simultaneous Switching Noise." International Symposium on Microelectronics 2012, no. 1 (2012): 001081–84. http://dx.doi.org/10.4071/isom-2012-thp25.

Full text

Abstract:

When integrating sensitive RF analog devices with complex VLSI digital components, simultaneously switching drivers cause supply voltage fluctuations which can propagate both horizontally and vertically between the power/ground planes. The same voltage source on a printed circuit board can be shared to increase power efficiency and reduce space used. In order to accomplish this, on board filtering is needed to isolate the noise between these two types of devices for proper operation. Hence, accurate estimation and improvement of the performance of power/ground planes is critical in a mixed-signal system. We present a new method to minimize the noise transfer at high frequencies to the power distribution system, called the Virtual Ground Fence. At its basic level, the Virtual Ground Fence consists of quarter-wave transmission-line stubs that act as short circuits between power and ground planes at their design frequency. We will present various configurations of Virtual Ground Fence for different coupling scenarios.

APA, Harvard, Vancouver, ISO, and other styles

42

Venkatesh, G. K., S. Bhargavi, Basavaraj V. Hiremath, and C. Anil Kumar. "Design and Performance Analysis of Low Power and High Throughput of Analog Data Compression and Decompression using ANN in 32nm FinFET Technology." International Journal of Circuits, Systems and Signal Processing 15 (July 28, 2021): 730–44. http://dx.doi.org/10.46300/9106.2021.15.81.

Full text

Abstract:

The development and fabrication of integrated circuits for the applicational areas of VLSI such as processing of the signal, medicine tomography, telecommunication turn out to be a novel technology for the upcoming innovations. The fabrication of IC’s is attributable to the methodology in the technology of VLSI and when compared to artificial Neural Network, the genetic performance of these productions is approximately the same and are typically employed for diagnosing the syndrome, compression as well as the decompression of signal used in the medical domain. Techniques such as HMM, DCT, as well as PCA are employed for compression and decompression of signals but these approaches still possess some disadvantages. Therefore, to overcome these issues, a chip-level design for Artificial Neural Network is proposed that makes use of FinFET 32 nm technology and includes sigmoid activation function (SAF), Gilbert cell number, as well as bias circuits to prolong the compressed magnitude relation and accuracy. As a result, with the help of the Cadence Virtuoso analog tool, the Artificial Neural Network has been designed using FinFET 32nm technology along with all the details of sub-units such as Layout vs Schematic (LVS), Design rule check (DRC), RC extraction as well as chip level (GDS-II). Feed Forward Artificial Neural Network (FWANN) is considered as one of the most basic types of ANN and it is implemented using the concept of Back Propagation (BP). The simulation results of the suggested 16-bit 6TRAM cell were found to have 8%, 21%, and 0.9% improvement in consuming power, delay, and compressed data losses respectively.

APA, Harvard, Vancouver, ISO, and other styles

43

NIRANJAN, VANDANA, ASHWANI KUMAR, and SHAIL BALA JAIN. "COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 08 (2014): 1450108. http://dx.doi.org/10.1142/s0218126614501084.

Full text

Abstract:

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

APA, Harvard, Vancouver, ISO, and other styles

44

Cho, Koon-Shik, and Jun-Dong Cho. "Low Power Digital Multimedia Telecommunication Designs." VLSI Design 12, no. 3 (2001): 301–15. http://dx.doi.org/10.1155/2001/43078.

Full text

Abstract:

The increasing prominence of wireless multimedia systems and the need to limit power capability in very-high density VLSI chips have led to rapid and innovative developments in low-power design. Power reduction has emerged as a significant design constraint in VLSI design. The need for wireless multimedia systems leads to much higher power consumption than traditional portable applications. This paper presents possible optimization technique to reduce the energy consumption for wireless multimedia communication systems. Four topics are presented in the wireless communication systems subsection which deal with architectures such as PN acquisition, parallel correlator, matched filter and channel coding. Two topics include the IDCT and motion estimation in multimedia application.These topics consider algorithms and architectures for low power design such as using hybrid architecture in PN acquisition, analyzing the algorithm and optimizing the sample storage in parallel correlator, using complex matched filter that analog operational circuits controlled by digital signals, adopting bit serial arithmetic for the ACS operation in viterbi decoder, using CRC to adaptively terminate the SOVA iteration in turbo decoder, using codesign in RS codec, disabling the processing elements as soon as the distortion values become great than the minimum distortion value in motion estimation, and exploiting the relative occurrence of zero-valued DCT coefficient in IDCT.

APA, Harvard, Vancouver, ISO, and other styles

45

Akinwande, A. I., P. P. Ruden, P. J. Vold, et al. "A self-aligned gate III-V heterostructure FET process for ultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits." IEEE Transactions on Electron Devices 36, no. 10 (1989): 2204–16. http://dx.doi.org/10.1109/16.40901.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Wyatt, John L., and David L. Standley. "Criteria for Robust Stability In A Class Of Lateral Inhibition Networks Coupled Through Resistive Grids." Neural Computation 1, no. 1 (1989): 58–67. http://dx.doi.org/10.1162/neco.1989.1.1.58.

Full text

Abstract:

In the analog VLSI implementation of neural systems, it is sometimes convenient to build lateral inhibition networks by using a locally connected on-chip resistive grid to interconnect active elements. A serious problem of unwanted spontaneous oscillation often arises with these circuits and renders them unusable in practice. This paper reports on criteria that guarantee these and certain other systems will be stable, even though the values of designed elements in the resistive grid may be imprecise and the location and values of parasitic elements may be unknown. The method is based on a rigorous, somewhat novel mathematical analysis using Tellegen's theorem (Penfield et al. 1970) from electrical circuits and the idea of a Popov multiplier (Vidyasagar 1978; Desoer and Vidya sagar 1975) from control theory. The criteria are local in that no overall analysis of the interconnected system is required for their use, empirical in that they involve only measurable frequency response data on the individual cells, and robust in that they are insensitive to network topology and to unmodelled parasitic resistances and capacitances in the interconnect network. Certain results are robust in the additional sense that specified nonlinear elements in the grid do not affect the stability criteria. The results are designed to be applicable, with further development, to complex and incompletely modeled living neural systems.

APA, Harvard, Vancouver, ISO, and other styles

47

Sinha, Pankaj Kumar, and Preetha Sharan. "Multiplexer Based Multiplications for Signal Processing Applications." Indonesian Journal of Electrical Engineering and Computer Science 9, no. 3 (2018): 583. http://dx.doi.org/10.11591/ijeecs.v9.i3.pp583-586.

Full text

Abstract:

<p>In signal processing, Filter is a device that removes the unwanted signals. In any electronic circuits, Filters are widely used in the fundamental hands on tool. The basic function of the filter is to selectively allow the desired signal to pass through and /or control the undesired signal based on the frequency. A signal processing filter satisfies a set of requirements which are realization and improvement of the filter. A filter system consists of an analog to digital converter is used to sample the input signal, traced by a microprocessor and some components such as memory to store the data and filter coefficients. Filters can easily be designed to be “linear phase” and it is easy to implement. In this paper, the birecoder multiplier (BM) is designed in terms of VLSI design environment. The proposed multiplier is implemented by using VHDL language and Xilinx ISE for synthesis. The multiplier is mainly used for image processing applications as well as signal processing applications.</p>

APA, Harvard, Vancouver, ISO, and other styles

48

NAKADA, KAZUKI, TETSUYA ASAI, and HATSUO HAYASHI. "ANALOG VLSI IMPLEMENTATION OF RESONATE-AND-FIRE NEURON." International Journal of Neural Systems 16, no. 06 (2006): 445–56. http://dx.doi.org/10.1142/s0129065706000846.

Full text

Abstract:

We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

APA, Harvard, Vancouver, ISO, and other styles

49

Dhare, Vaishali, and Usha Mehta. "SAF Analyses of Analog and Mixed Signal VLSI Circuit : Digital to Analog Converter." International Journal of VLSI Design & Communication Systems 6, no. 3 (2015): 49–58. http://dx.doi.org/10.5121/vlsic.2015.6305.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Li, XiaoFu, Md Raf E. Ul Shougat, Scott Kennedy, et al. "A four-state adaptive Hopf oscillator." PLOS ONE 16, no. 3 (2021): e0249131. http://dx.doi.org/10.1371/journal.pone.0249131.

Full text

Abstract:

Adaptive oscillators (AOs) are nonlinear oscillators with plastic states that encode information. Here, an analog implementation of a four-state adaptive oscillator, including design, fabrication, and verification through hardware measurement, is presented. The result is an oscillator that can learn the frequency and amplitude of an external stimulus over a large range. Notably, the adaptive oscillator learns parameters of external stimuli through its ability to completely synchronize without using any pre- or post-processing methods. Previously, Hopf oscillators have been built as two-state (a regular Hopf oscillator) and three-state (a Hopf oscillator with adaptive frequency) systems via VLSI and FPGA designs. Building on these important implementations, a continuous-time, analog circuit implementation of a Hopf oscillator with adaptive frequency and amplitude is achieved. The hardware measurements and SPICE simulation show good agreement. To demonstrate some of its functionality, the circuit’s response to several complex waveforms, including the response of a square wave, a sawtooth wave, strain gauge data of an impact of a nonlinear beam, and audio data of a noisy microphone recording, are reported. By learning both the frequency and amplitude, this circuit could be used to enhance applications of AOs for robotic gait, clock oscillators, analog frequency analyzers, and energy harvesting.

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!