Relevant bibliographies by topics / VLSI architecture

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'VLSI architecture'

Author: Grafiati
Published: 4 June 2021
Last updated: 26 July 2025

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Journal articles on the topic "VLSI architecture"

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ACHARYA, TINKU, and AMAR MUKHERJEE. "HIGH-SPEED PARALLEL VLSI ARCHITECTURES FOR IMAGE DECORRELATION." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (1995): 343–65. http://dx.doi.org/10.1142/s021800149500016x.

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We present a new high speed parallel architecture and its VLSI implementation to design a special purpose hardware for real-time lossless image compression/ decompression using a decorrelation scheme. The proposed architecture can easily be implemented using state-of-the-art VLSI technology. The hardware yields a high compression rate. A prototype 1-micron VLSI chip based on this architectural idea has been designed. The scheme is favourably comparable to the lossless JPEG standard image compression schemes. We also discuss the parallelization issues of the lossless JPEG standard still compres
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LEE, HANHO, and GERALD E. SOBELMAN. "VLSI DESIGN OF DIGIT-SERIAL FPGA ARCHITECTURE." Journal of Circuits, Systems and Computers 13, no. 01 (2004): 17–52. http://dx.doi.org/10.1142/s021812660400126x.

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This paper presents a novel application-specific field-programmable gate array (FPGA) architecture that satisfies efficient implementation of digit-serial DSP architectures on a digit wide basis. Digit-serial DSP designs have been an effective implementation method for FPGAs. To efficiently realize a digit-serial DSP design on FPGAs, one must create an FPGA architecture optimized for those types of systems. We examine the various circuits used in digit-serial DSP designs to extract their key features that should be reflected in the new FPGA architecture. We explain the design methodology, layo
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Hicks, P. J. "Book Review: VLSI Architecture." International Journal of Electrical Engineering Education 22, no. 3 (1985): 244. http://dx.doi.org/10.1177/002072098502200314.

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Hirayama, M. "VLSI oriented asynchronous architecture." ACM SIGARCH Computer Architecture News 14, no. 2 (1986): 290–96. http://dx.doi.org/10.1145/17356.17390.

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ERTEN, GAIL, and FATHI M. SALAM. "TWO CELLULAR ARCHITECTURES FOR INTEGRATED IMAGE SENSING AND PROCESSING ON A SINGLE CHIP." Journal of Circuits, Systems and Computers 08, no. 05n06 (1998): 637–59. http://dx.doi.org/10.1142/s0218126698000407.

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Two architectures for a programmable image processor with on-chip light sensing capability are described. The first is a VLSI implementation of a cellular neural network. The second is a distributed dual-structure mutation of the first architecture. The distributed dual architecture leverages the speed of silicon against the large silicon area requirements. Moreover, the innovative integrated nature of the dual-structure design significantly reduces the bottleneck and computational overload caused by data transfer from sensory focal plane to the image processor. The paper also describes VLSI c
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Korneev, V. V., and I. E. Tarasov. "VLSI Architecture with a Configurable Pipeline." Programmnaya Ingeneria 11, no. 5 (2020): 270–76. http://dx.doi.org/10.17587/prin.11.270-276.

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The analysis carried out in the article shows the possibility of creating a problem-oriented VLSI, fabricated according to the technological standards of 28 nm or less, for at least one family of digital signal processing problems using similar computing nodes in structure. The use of distributed arithmetic allows one to apply a technique based on performing only those multiplication steps for which non-zero digits are set in the corresponding positions of the filter coefficients. Therefore, the performance of 200 nodes executing 2 steps at 1 GHz is equivalent to approximately 80 GMAC/s/mm2 fo
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Chiper, Doru Florin. "An Improved VLSI Algorithm for an Efficient VLSI Implementation of a Type IV DCT That Allows an Efficient Incorporation of Hardware Security with a Low Overhead." Electronics 12, no. 1 (2023): 243. http://dx.doi.org/10.3390/electronics12010243.

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This paper aims to solve one of the most challenging problems in designing VLSI chips for common goods, namely an efficient incorporation of security techniques while maintaining high performances of the VLSI implementation with a reduced hardware complexity. In this case, it is very important to maintain high performance at a low hardware complexity and the overheads introduced by the security techniques should be as low as possible. This paper proposes an improved approach based on a new VLSI algorithm for including the obfuscation technique in the VLSI implementation of one important DSP al
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Ryzhenko, Igor Nikolaevich, Oleg Vladimirovich Nepomnyaschy, Aleksandr Ivanovich Legalov, and Vladimir Viktorovich Shaidurov. "Methods for Change Parallelism in Process of High-level VLSI Synthesis." Modeling and Analysis of Information Systems 29, no. 1 (2022): 60–72. http://dx.doi.org/10.18255/1818-1015-2022-1-60-72.

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In this paper methods for increasing the efficiency of VLSI development based on the method of architecture-independent design are proposed. The route of high-level VLSI synthesis is considered. The principle of constructing a VLSI hardware model based on the functional-flow programming paradigm is stated.The results of the development of methods and algorithms for transformation functional-parallel programs into programs in HDL languages that support the design process of digital chips are presented. The principles of assessment are considered and the classes of resources required for the ana
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Pushpalatha, P., and K. Babulu. "Design and implementation of systolic architecture based FIR filter." i-manager's Journal on Digital Signal Processing 10, no. 1 (2022): 17. http://dx.doi.org/10.26634/jdp.10.1.18852.

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In signal processing, a filter is a device or process that removes some unwanted components or features from a signal. Digital filters are mainly divided into Infinite Impulse Response (IIR) filters and Finite Impulse Response (FIR) filters. FIR filters are mostly used in applications like image processing, communications, Digital Signal Processing (DSP) etc. One of the most used filters for designing of VLSI circuits is FIR filter. Systolic architecture is a Processing Element (PE) network that generates and passes data rhythmically through the system. The concept of systolic architecture can
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Jeevitha, M., and R. Muthaiah. "VLSI Based Combined Multiplier Architecture." Journal of Artificial Intelligence 6, no. 2 (2013): 145–53. http://dx.doi.org/10.3923/jai.2013.145.153.

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Dissertations / Theses on the topic "VLSI architecture"

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Spray, Andrew J. C. "VLSI parallel processing architectures." Thesis, Bangor University, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.278108.

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Grzeszczak, Aleksander. "VLSI architecture for Discrete Wavelet Transform." Thesis, University of Ottawa (Canada), 1995. http://hdl.handle.net/10393/9908.

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In this thesis, we present a new simple and efficient VLSI architecture (DWT-SA) for computing the Discrete Wavelet Transform. The proposed architecture is systolic in nature, modular and extendible to 1-D or 2-D DWT transform of any size. The DWT-SA has been designed, simulated and implemented in silicon. The following are the features of the DWT-SA architecture: (1) It has an efficient (close to 100%) hardware utilization. (2) It works with data streams of arbitrary size. (3) The design is cascadable, for computation of one, two or three dimensional DWT. (4) It requires a minimum interface c
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Renaudin, Marc. "Architecture VLSI pour le codage d'images." Grenoble INPG, 1990. http://www.theses.fr/1990INPG0118.

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Une synthese bibliographique tres complete des techniques de codage de sequences d'images animees et leur evolution au cours des dernieres annees offre une vue d'ensemble sur le domaine de la compression d'images, et decrit les grandes classes d'algorithmes utilises dans les codeurs de la premiere generation. L'estimation de mouvement est la tache la plus intensive en calculs dans les codeurs hybrides a compensation de mouvement. L'etude architecturale des differents niveaux de structure, s'appuyant sur une methode classique de synthese d'architectures systoliques, conduit a la maitrise d'un e
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Arrigo, Jeanette Fay Freauf. "Improved VLSI architecture for attitude determination computations." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3195257.

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Thesis (Ph. D.)--University of California, San Diego, 2006.<br>Title from first page of PDF file (viewed February 28, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references.
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Arias, Estrada Miguel Octavio. "VLSI architecture for a motion vision sensor." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0023/NQ31480.pdf.

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Wilson, Denise M. "Analog VLSI architecture for chemical sensing microsystems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13322.

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Tabak, Daniel. "VLSI ORIENTED COMPUTER ARCHITECTURE AND SOME APPLICATIONS." International Foundation for Telemetering, 1985. http://hdl.handle.net/10150/615746.

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International Telemetering Conference Proceedings / October 28-31, 1985 / Riviera Hotel, Las Vegas, Nevada<br>The paper surveys the particular problems, arising in the architectural design of computing systems, realized on VLSI chips. Particular difficulties due to limited on-chip density and power dissipation are discussed. The difficulties of the realization of on-chip communications between various subsystems (between themselves and between other offchip systems) are stressed. A number of design principles for the realization of on-chip communication paths is presented. Two design philosoph
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Min, Byoung-Ki. "Architecture VLSI pour le décodeur de Viterbi /." Paris : École nationale supérieure des télécommunications, 1992. http://catalogue.bnf.fr/ark:/12148/cb35585898j.

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Ila, Viorela. "VLSI architecture for motion estimation in underwater imaging." Doctoral thesis, Universitat de Girona, 2005. http://hdl.handle.net/10803/7732.

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El treball desenvolupat en aquesta tesi aprofundeix i aporta solucions innovadores en el camp orientat a tractar el problema de la correspondència en imatges subaquàtiques. En aquests entorns, el que realment complica les tasques de processat és la falta de contorns ben definits per culpa d'imatges esborronades; un fet aquest que es deu fonamentalment a il·luminació deficient o a la manca d'uniformitat dels sistemes d'il·luminació artificials. <br/>Els objectius aconseguits en aquesta tesi es poden remarcar en dues grans direccions. Per millorar l'algorisme d'estimació de moviment es va propos
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Tsui, Steven. "A reduced-power VLSI architecture for sequential decoding." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0027/MQ31262.pdf.

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Books on the topic "VLSI architecture"

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Kenzo, Watanabe, ed. VLSI and computer architecture. Nova Science Publisher, 2009.

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Shankar, Ravi. VLSI and computer architecture. Academic Press, 1989.

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1925-, Hannemann Rob, Kraus Allan D, and Pecht Michael, eds. Physical architecture of VLSI systems. Wiley, 1994.

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1961-, Ranganathan N., ed. VLSI algorithms and architectures. IEEE Computer Society Press, 1993.

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Liu, Leibo, Guiqiang Peng, and Shaojun Wei. Massive MIMO Detection Algorithm and VLSI Architecture. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-6362-7.

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Jonker, Petrus Paulus. Morphological Image Processing: Architecture and VLSI design. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-2804-3.

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Dally, William J. A VLSI Architecture for Concurrent Data Structures. Springer US, 1987. http://dx.doi.org/10.1007/978-1-4613-1995-5.

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Jonker, Petrus Paulus. Morphological image processing: Architecture and VLSI design. Kluwer, 1992.

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Dally, William J. A VLSI Architecture for Concurrent Data Structures. Springer US, 1987.

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Mohanty, Basant Kumar, Rajeev Kumar Arya, Durgesh Nandan, and Sanjeev Kumar. VLSI Architecture for Signal, Speech, and Image Processing. Apple Academic Press, 2022. http://dx.doi.org/10.1201/9781003277538.

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Book chapters on the topic "VLSI architecture"

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Lu, Priscilla M., Don E. Blahut, and Kevin S. Grant. "Architecture of Modern VLSI Processors." In The Kluwer International Series in Engineering and Computer Science. Springer US, 1987. http://dx.doi.org/10.1007/978-1-4613-1985-6_13.

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Yeap, Gary. "Architecture and System." In Practical Low Power Digital VLSI Design. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-6065-4_7.

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Pop, Paul, Wajid Hassan Minhass, and Jan Madsen. "Biochip Architecture Model." In Microfluidic Very Large Scale Integration (VLSI). Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29599-2_3.

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Touhafi, Abdellah, Wouter Brissinck, and Erik Dirkx. "Scalable Run Time Reconfigurable Architecture." In VLSI: Systems on a Chip. Springer US, 2000. http://dx.doi.org/10.1007/978-0-387-35498-9_11.

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Fakhraie, Sied Mehdi, and Kenneth Carless Smith. "Foundations: Architecture Design." In VLSI — Compatible Implementations for Artificial Neural Networks. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6311-2_4.

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Williams, S. R., and J. G. Cleary. "The VLSI Implementation of the ∑ Architecture." In VLSI for Artificial Intelligence and Neural Networks. Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3752-6_25.

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Romanova, Claudia, and Ulrich Wagner. "A VLSI Architecture for Anti-Aliasing." In Advances in Computer Graphics Hardware IV. Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-76298-7_4.

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Sakamura, Ken. "TRON VLSI CPU: Concepts and Architecture." In TRON Project 1987 Open-Architecture Computer Systems. Springer Japan, 1987. http://dx.doi.org/10.1007/978-4-431-68069-7_17.

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Taraate, Vaibbhav. "System and Architecture Design." In Digital Design from the VLSI Perspective. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-4652-3_3.

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Kanopoulos, Nick, and Peter N. Marinos. "A high-performance single-chip vlsi signal processor architecture." In VLSI Algorithms and Architectures. Springer Berlin Heidelberg, 1986. http://dx.doi.org/10.1007/3-540-16766-8_15.

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Conference papers on the topic "VLSI architecture"

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Mattihalli, Channamallikarjuna, Suprith Ron, and Naveen Kolla. "VLSI Based Robust Router Architecture." In 2012 3rd International Conference on Intelligent Systems, Modelling and Simulation (ISMS). IEEE, 2012. http://dx.doi.org/10.1109/isms.2012.32.

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Louis, Roshna, M. Vinodhini, and N. S. Murty. "Reliable router architecture with elastic buffer for NoC architecture." In 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA). IEEE, 2015. http://dx.doi.org/10.1109/vlsi-sata.2015.7050463.

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Kathail, Vinod, and Tom Miller. "Architecture Exploration for Low Power Design." In 21st International Conference on VLSI Design (VLSID 2008). IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.132.

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Semwal, Sandeep, Rohit Kumar Nirala, Nivedita Rai, and Abhinav Kranti. "Architecture Dependent Constraint-Aware RFET Based 1T-DRAM." In 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT). IEEE, 2023. http://dx.doi.org/10.1109/vlsi-tsa/vlsi-dat57221.2023.10134488.

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Wu, Nai-Chun, Tsu-Hsiang Chen, and Chih-Tsun Huang. "Hardware-aware Model Architecture for Ternary Spiking Neural Networks." In 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT). IEEE, 2023. http://dx.doi.org/10.1109/vlsi-tsa/vlsi-dat57221.2023.10134319.

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Lotfi-Kamran, Pejman, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, and Zainalabedin Navabi. "Stall Power Reduction in Pipelined Architecture Processors." In 21st International Conference on VLSI Design (VLSID 2008). IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.34.

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Abbas, Syed Mohsin, Thibaud Tonnellier, Furkan Ercan, and Warren J. Gross. "High-Throughput VLSI Architecture for GRAND." In 2020 IEEE Workshop on Signal Processing Systems (SiPS). IEEE, 2020. http://dx.doi.org/10.1109/sips50750.2020.9195254.

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Sims, S., and J. Benkual. "Regulus: A high performance VLSI architecture." In COMPCON Spring 88. IEEE, 1988. http://dx.doi.org/10.1109/cmpcon.1988.4826.

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Grzeszczak, Yeap, and Panchanathan. "VLSI architecture for discrete wavelet transform." In Proceedings of Canadian Conference on Electrical and Computer Engineering CCECE-94. IEEE, 1994. http://dx.doi.org/10.1109/ccece.1994.405788.

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Babionitakis, K., K. Manolopoulos, K. Nakos, D. Reisis, N. Vlassopoulos, and V. A. Chouliaras. "A High Performance VLSI FFT Architecture." In 2006 13th IEEE International Conference on Electronics, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/icecs.2006.379912.

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Reports on the topic "VLSI architecture"

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Dally, William J., and Steve Lacy. VLSI Architecture: Past, Present, and Future. Defense Technical Information Center, 1998. http://dx.doi.org/10.21236/ada419586.

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Thangavel, Kalavathi Devi, Sakthivel Palaniappan, and Sathish Kumar Shanmugam. Performance Analysis of VLSI Architecture of Viterbi Decoder in WLAN Using the Sleepy Keeper Technique. "Prof. Marin Drinov" Publishing House of Bulgarian Academy of Sciences, 2020. http://dx.doi.org/10.7546/crabs.2020.08.11.

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Parhi, Keshab K. Concurrent Architectures for VLSI Signal and Image Processing. Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada276124.

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Pradhan, Dhiraj K. Fault-Tolerant Architectures for Multiprocessor and VLSI-Based Systems. Defense Technical Information Center, 1992. http://dx.doi.org/10.21236/ada267370.

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Pradhan, Dhiraj K. Fault Tolerant Architectures for Multiprocessors and VLSI-Based Systems. Defense Technical Information Center, 1991. http://dx.doi.org/10.21236/ada244034.

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Parhi, Keshab K. Low-Power VLSI Architectures for Error Control Coding and Wavelets. Defense Technical Information Center, 2001. http://dx.doi.org/10.21236/ada398592.

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Stine, Jr, and James E. Exploration and Evaluation of Nanometer Low-power Multi-core VLSI Computer Architectures. Defense Technical Information Center, 2015. http://dx.doi.org/10.21236/ada621986.

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