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Relevant bibliographies by topics / VLSI architecture / Dissertations / Theses

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Dissertations / Theses on the topic 'VLSI architecture'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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1

Spray, Andrew J. C. "VLSI parallel processing architectures." Thesis, Bangor University, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.278108.

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2

Grzeszczak, Aleksander. "VLSI architecture for Discrete Wavelet Transform." Thesis, University of Ottawa (Canada), 1995. http://hdl.handle.net/10393/9908.

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In this thesis, we present a new simple and efficient VLSI architecture (DWT-SA) for computing the Discrete Wavelet Transform. The proposed architecture is systolic in nature, modular and extendible to 1-D or 2-D DWT transform of any size. The DWT-SA has been designed, simulated and implemented in silicon. The following are the features of the DWT-SA architecture: (1) It has an efficient (close to 100%) hardware utilization. (2) It works with data streams of arbitrary size. (3) The design is cascadable, for computation of one, two or three dimensional DWT. (4) It requires a minimum interface c

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3

Renaudin, Marc. "Architecture VLSI pour le codage d'images." Grenoble INPG, 1990. http://www.theses.fr/1990INPG0118.

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Une synthese bibliographique tres complete des techniques de codage de sequences d'images animees et leur evolution au cours des dernieres annees offre une vue d'ensemble sur le domaine de la compression d'images, et decrit les grandes classes d'algorithmes utilises dans les codeurs de la premiere generation. L'estimation de mouvement est la tache la plus intensive en calculs dans les codeurs hybrides a compensation de mouvement. L'etude architecturale des differents niveaux de structure, s'appuyant sur une methode classique de synthese d'architectures systoliques, conduit a la maitrise d'un e

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4

Arrigo, Jeanette Fay Freauf. "Improved VLSI architecture for attitude determination computations." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3195257.

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Thesis (Ph. D.)--University of California, San Diego, 2006.<br>Title from first page of PDF file (viewed February 28, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references.

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5

Arias, Estrada Miguel Octavio. "VLSI architecture for a motion vision sensor." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0023/NQ31480.pdf.

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6

Wilson, Denise M. "Analog VLSI architecture for chemical sensing microsystems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13322.

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7

Tabak, Daniel. "VLSI ORIENTED COMPUTER ARCHITECTURE AND SOME APPLICATIONS." International Foundation for Telemetering, 1985. http://hdl.handle.net/10150/615746.

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International Telemetering Conference Proceedings / October 28-31, 1985 / Riviera Hotel, Las Vegas, Nevada<br>The paper surveys the particular problems, arising in the architectural design of computing systems, realized on VLSI chips. Particular difficulties due to limited on-chip density and power dissipation are discussed. The difficulties of the realization of on-chip communications between various subsystems (between themselves and between other offchip systems) are stressed. A number of design principles for the realization of on-chip communication paths is presented. Two design philosoph

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8

Min, Byoung-Ki. "Architecture VLSI pour le décodeur de Viterbi /." Paris : École nationale supérieure des télécommunications, 1992. http://catalogue.bnf.fr/ark:/12148/cb35585898j.

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9

Ila, Viorela. "VLSI architecture for motion estimation in underwater imaging." Doctoral thesis, Universitat de Girona, 2005. http://hdl.handle.net/10803/7732.

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El treball desenvolupat en aquesta tesi aprofundeix i aporta solucions innovadores en el camp orientat a tractar el problema de la correspondència en imatges subaquàtiques. En aquests entorns, el que realment complica les tasques de processat és la falta de contorns ben definits per culpa d'imatges esborronades; un fet aquest que es deu fonamentalment a il·luminació deficient o a la manca d'uniformitat dels sistemes d'il·luminació artificials. <br/>Els objectius aconseguits en aquesta tesi es poden remarcar en dues grans direccions. Per millorar l'algorisme d'estimació de moviment es va propos

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10

Tsui, Steven. "A reduced-power VLSI architecture for sequential decoding." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0027/MQ31262.pdf.

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11

Jalowiecki, Ian P. "VLSI associative strings : an architecture for image processing." Thesis, Brunel University, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.253300.

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12

Mok, Winston Ki-Cheong. "VLSI implementable associative memory based on neural network architecture." Thesis, University of British Columbia, 1989. http://hdl.handle.net/2429/27942.

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Neural network associative memories based on Hopfield's design have two failure modes. 1) Certain memories are not recallable as they do not lie in a local minimum of the system's Liapunov (energy) function, and 2) the associative memory converges to a non-memory location due to trapping by spurious local minima in the energy function surface. The properties of the first failure mechanism in the Hopfield and five related models were investigated. A new architecture eliminating such failures is proposed. The architecture is fully digital and modular. Furthermore, it is more silicon-area efficie

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Athreya, Jayantha Krishna V. "An analog VLSI architecture for image smoothing and segmentation." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0028/MQ39633.pdf.

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14

Goodenough, Norman John. "A heterogeneous VLSI architecture for real-time image processing." Thesis, University of Sheffield, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.364243.

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15

Shi, Jianfei, Gerald J. Grebowsky, Ward P. Horner, and James R. Chesney. "Prototype Architecture for a VLSI Level Zero Processing System." International Foundation for Telemetering, 1989. http://hdl.handle.net/10150/614729.

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International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California<br>While the complete process of preparing telemetry data for delivery to NASA's customers requires a number of steps or levels (level 0,1,2...etc.), the initial processing, generally referred to as Level Zero Processing (LZP), poses a real technical challenge for NASA in the 1990s Space Station Freedom era. This challenge is the result of requirements to provide real-time or near real-time LZP products at rates up to 150 Mbps. In addition, increase

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16

O'Leary, John Willis Carleton University Dissertation Engineering Electrical. "A VLSI architecture for linear predictive analysis of speech." Ottawa, 1989.

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17

Kosaraju, Naga M. "A VLSI Architecture for Rijndael, the Advanced Encryption Standard." [Tampa, Fla.] : University of South Florida, 2003. http://purl.fcla.edu/fcla/etd/SFE0000163.

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18

Geller, Ronnie Dee. "A VLSI architecture for a neurocomputer using higher-order predicates." Full text open access at:, 1987. http://content.ohsu.edu/u?/etd,137.

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19

Pajayakrit, A. "VLSI architecture and design for the Fermat Number Transform implementation." Thesis, University of Newcastle Upon Tyne, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379767.

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Chiu, Kuo-En, and 邱國恩. "VLSI Architecture of JPEG2000 Codec." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/73652927005268307145.

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碩士<br>義守大學<br>電機工程學系碩士班<br>94<br>The hierarchical modular design and hardware implementation of JPEG2000 codec are presented in this thesis. The codec includes three major modules: DWT, Quantizer, and EBCOT Tier-1. On the premise of reducing the hardware resources requirement, we elaborate a high-performance architecture and discrete-event model for each functional module. Through the hardware synthesis methodology, the RTL hardware of each functional module is generated rapidly. The synthesized circuit possesses distributed architecture, good extensibility and ease to system integration. The

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Kumar, Abhishek. "Low-Power Network on chip Architecture." Thesis, 2017. http://ethesis.nitrkl.ac.in/8855/1/2017_MT_AKumar.pdf.

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Due to rapid development in the field of technology, we are able to integrate many devices on a single chip. So the communication between these devices becomes noticeably indispensable.The network on chip (NoC) is a technology which is used for such communicate on. The fundamental component of a NoC is a router. Be that as it may, in NoC design, there is power, area, and performance trade-off in topology, buffer sizes, routing algorithms and flow control mechanisms. For the NoC, the architecture of router must be an efficient one for balancing all things in the NoC and it should have lower l

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22

Chen, Chien-Ting, and 陳建廷. "Efficient VLSI Architecture for Fresnel Transform." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/71005980707713104776.

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23

Wang, Si-hwa, and 王世華. "VLSI Architecture Designs of Grey Model." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/35563440049948740253.

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碩士<br>國立台灣工業技術學院<br>電機工程技術研究所<br>85<br>The thesis propose a hardware architecture to eliminate the bottleneck of grey model construction and prediction. To solve the problem of applying grey model in some real-time systems, we present a grey predictor architecture with 12 bits fixed-point input and optional confine for the sampled data numbers and predictive time. Fixed-point input format will simplify hardware complexity, reduce predictive time and make it easy to match with analog-digital

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Hemkumar, Nariankadu Datatreya. "A systolic VLSI architecture for complex SVD." Thesis, 1991. http://hdl.handle.net/1911/13526.

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This thesis presents a systolic algorithm for the SVD of arbitrary complex matrices, based on the cyclic Jacobi method with "parallel ordering". As a basic step in the algorithm, a two-step, two-sided unitary transformation scheme is employed to diagonalize a complex 2 $\times$ 2 matrix. The transformations are tailored to the use of CORDIC (COordinate Rotation DIgital Computer) algorithms for high speed arithmetic. The complex SVD array is modeled on the Brent-Luk-VanLoan array for real SVD. An array with O($n\sp2$) processors is required to compute the SVD of a $n \times n$ matrix in O(n log

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YANG, BO-XIONG, and 楊博雄. "A VLSI architecture for moving target detector." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/42740562487235625478.

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Wang, Yung-Ming, and 王永銘. "The Parameterized VLSI Architecture of Genetic Algorithm." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/64725730798572059077.

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碩士<br>南台科技大學<br>電子工程系<br>92<br>The genetic algorithm can find an optimal solution in many complex problems, so it has been used widely in many applications, such as image processing, fuzzy control, neural network, communication system, and layout optimization. Genetic algorithm requires very intensive computations in order to perform the optimization. Hence, a dedicated VLSI implementation for it is necessary. We propose a very flexible soft GA IP and its auxiliary software system in this paper. Every module of GA IP is developed by using Verilog hardware description language (HDL), and then i

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Dally, William James. "A VLSI Architecture for Concurrent Data Structures." Thesis, 1986. https://thesis.library.caltech.edu/1122/3/Dally_wj_1986.pdf.

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<p>Concurrent data structures simplify the development of concurrent programs by encapsulating commonly used mechanisms for synchronization and communication into data structures. This thesis develops a notation for describing concurrent data structures, presents examples of concurrent data structures, and describes an architecture to support concurrent data structures.</p> <p>Concurrent Smailtalk (CST), a derivative of Smailtalk-80 with extensions for concurrency, is developed to describe concurrent data structures. CST allows the programmer to specify objects that are distributed over the

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Lin, Tsung-Ta, and 林宗達. "The VLSI Architecture Design of JPEG2000 Encoder." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/75112936611969139902.

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碩士<br>淡江大學<br>電機工程學系碩士班<br>96<br>The amount of memory required for code-block is one of the most important issue in JPEG2000 encoder chip implementation. To overcome the drawbacks caused by the large amount of code-block memory in JPEG2000, this paper proposes a new JPEG2000 encoder architecture without code-block memory. Here we try to unify the output scanning order of the 2D-DWT (discrete wavelet transform) and the processing scanning of the EBCOT (embedded block coding with optimized truncation) and further the code-block memory can be completely eliminated. Since the code-block memory has

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Salam, Gamze Erten. "An analog VLSI architecture for stereo correspondence." Thesis, 1994. https://thesis.library.caltech.edu/4845/1/Salam_ge_1994.pdf.

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My goal in engaging in this project was to design a hardware system to solve the stereo correspondence problem in real-time. Consequently, this work describes and analyzes an algorithm for stereo correspondence, its extension to an analog VLSI architecture, and the results obtained from its hardware implementation as a chip. The first chapter, titled Introduction, describes the stereo correspondence problem. Therein, I discuss biological and psychophysical mechanisms of stereo vision, and include a brief history of ideas to date on the subject. I wrote this chapter to introduce the probl

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Sagar, V. V. V. "Lossless data compression and decompression algorithm and its hardware architecture." Thesis, 2008. http://ethesis.nitrkl.ac.in/4155/1/4.pdf.

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LZW (Lempel Ziv Welch) and AH (Adaptive Huffman) algorithms were most widely used for lossless data compression. But both of these algorithms take more memory for hardware implementation. The thesis basically discuss about the design of the two-stage hardware architecture with Parallel dictionary LZW algorithm first and Adaptive Huffman algorithm in the next stage. In this architecture, an ordered list instead of the tree based structure is used in the AH algorithm for speeding up the compression data rate. The resulting architecture shows that it not only outperforms the AH algorithm at the c

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Amod, Amit Kumar. "Architecture for SuperSpeed data communication for USB 3.0 device using FPGA." Thesis, 2013. http://ethesis.nitrkl.ac.in/4704/1/211EC2074.pdf.

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The need for very large speed data communication leads to use of USB 3.0. This can be achieved by mixing the advantage of parallel and serial data transfer. This project work provides architecture for communication between USB 3.0 device controller (Cypress CYUSB3014) and USB 3.0 host controller (TUSB7320) at a data rate of 5.0 Gbps using Altera’s Stratix IV (EP4SGX70DF29C3N) FPGA. To maintain synchronization between GPIF II and PCIe hard IP, two FIFO's are used. PLL is used to provide clock signal at various frequencies. The physical layer provides signalling technology for SuperSpeed bus. Th

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"VLSI architecture for motion estimation in underwater imaging." Universitat de Girona, 2005. http://www.tesisenxarxa.net/TDX-0404106-115821/.

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Chang, Tian-Sheuan, and 張添烜. "VLSI ARCHITECTURE DESIGN FOR BIT-LEVEL INNER PRODUCT." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/68111050957313296182.

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博士<br>國立交通大學<br>電子工程系<br>88<br>Inner product is an important building block to many DSP applications such as multimedia, wireless and communication systems. Due to the wide range of applications, the study on efficient implementations to meet different application requirements becomes an important research topic. In this dissertation, we study this topic by exploring the bit-level design space of inner product, including both programmable and non-programmable operands. For non-programmable inner product, we explore its design space by considering the constant and the numerical prope

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Tsai, Lei-Luo, and 蔡磊駱. "IMPLEMENTATION OF 2-D DCT/IDCT VLSI ARCHITECTURE." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/58937135731980105959.

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碩士<br>大同工學院<br>電機工程研究所<br>87<br>This thesis discusses the design of a combined DCT/IDCT CMOS integrated circuit for general video application. We know that the discrete cosine transform is widely used in several international standards, in this thesis, we use a low-complexity, and high-performance architecture to realize a DCT/IDCT chip. Beside, we also use some technique (tree structure) to improve the chip performance. Based on TSMC SPTM 0.6μm CMOS technology and COMPASS 0.6μm cell library, our DCT chip is implemented. It integrates about 120k transistors, and die size occupies a

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張閔盛, Min-Sheng Chang, and 張閔盛. "VLSI Architecture Design of Parallel Phase Turbo Decoder." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/9w5pyu.

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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>98<br>In this thesis, we proposed a novel parallel phase turbo decoding algorithm for VLSI architecture. Traditional sliding window turbo algorithm exchanges extrinsic information phase by phase, it will induce a long decoding latency. The proposed algorithm exchanges extrinsic information as soon as it had been calculated half the frame size, thus, it can not only eliminate (De-)Interleaver delay but also save the storage space. Besides, we modify the received data RAM to reduce the decoding time. By using this method, the decoder can reduce half frame decoding l

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Jiang, Shing-Jeh, and 江欣潔. "VLSI Architecture Design of Class-base Packet Scheduling." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/39508430212764740077.

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碩士<br>國立雲林科技大學<br>電子工程與資訊工程技術研究所<br>88<br>Meeting quality of service (QoS) requirements for various services in networks has been very challenging to network designers. Besides of increase the bandwidth of network directly, it must allocate bandwidth and bound delay to meet the requirements of each application. The traditional scheduling mechanism can not meet differentiated service requirement. We will develop the scheduler, which can provide differentiated service for each priority flow. There are two major complexities about scheduler:1)calculating time stamps and system potentia

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Yang, Chun-Chih, and 楊君智. "Design and VLSI Architecture of Reed-Solomon Decoders." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/32206248094672231312.

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碩士<br>大同工學院<br>資訊工程學系<br>84<br>Pipeline structure has been widely used to implement high speed RS decoders.There are a few structures published in the literature with the period of systemclock longer than 3 multiplication time which use symbol clocks as system clocksand pipeline structure is adopted. In this thesis, a modified multiplier and amodified pipelined structure are proposed. Both the hardware complexity and the computational delay of the proposed multiplier are less than the conve

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HONG, BAO-SAN, and 洪寶山. "VLSI architecture for the multiplier of finite fields." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/57936396793607430851.

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ZENG, ZHI-YUAN, and 曾治元. "Highly concurrent VLSI architecture for solving:linear system equations." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/58231200704267858698.

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Yeh, Ding-Kuen, and 葉丁坤. "A VLSI Architecture and Chip for Motion Estimation." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/48396914987519121041.

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碩士<br>國立臺灣科技大學<br>工程技術研究所<br>81<br>In this thesis, we present a VLSI architecture and chip for motion estimation full-search blocking-matching algorithm Motion estimation is an important technique for the video image compression systems. FSBMA is simple and has optimal solution for motion estimation, but it requires huge amount of computation. In order to satisfy the requirement of real-time image compression system, we propose a VLSI architecture for FSBMA. Such an architecture exhibits bo

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Liu, Min-Chih, and 劉旻智. "VLSI IMPLEMENTATION OF 2-D DCT/IDCT ARCHITECTURE." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/58319845538696646120.

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碩士<br>大同大學<br>電機工程學系(所)<br>96<br>The digit compress technology is concerned by people extremely. The 2-D DCT and IDCT are widely used and the most effective compression technology in image compressing. There are also a lot of new algorithms being proposed all the time, but most structure application will spend too much cost. This paper takes the short time to market and low cost as the direction in design. We make the design to be an DCT/IDCT IP under the consideration of the area and speed of the chip. Though 2-D DCT/IDCT roughly are divided into row-column decomposition (RCD) and not row-co

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Yang, Jun Zhi, and 楊君智. "Design and VLSI architecture of reed-solomon decoder." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/56659366834466043191.

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Chang, Sin-Hau, and 張信豪. "Low Area Cost VLSI Architecture for Fresnel Transform." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/38803596036245077675.

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Huang, Shao-Chieh, and 黃紹傑. "VLSI architecture design for Convolutive Blind Source Separation." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/45876328535836644899.

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碩士<br>國立中央大學<br>資訊工程研究所<br>99<br>Blind source separation (BSS) of independent sources from their convolutive mixtures is a problem in many real world applications. Therefore, we hope we can design an effective and scalable VLSI architecture for BSS. Considering the algorithm, the BSS architecture proposed by Torkkola is utilized and its learning rule is similar to least mean squares (LMS). Reducing the critical path will increase clock rate and throughput of hardware, so we apply delayed LMS (DLMS) to BSS. We proposed two VLSI architectures for DLMS. The proposed-I architecture improves the a

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CHEN, ZONG-XIN, and 陳宗信. "VLSI architecture for graylevel morphology and its application." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/39819017055076421047.

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Chien-Kuo, Lai, and 賴建國. "VLSI Architecture to Implement Computations in GF(28)." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/11665243677422088875.

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碩士<br>大同工學院<br>電機工程研究所<br>86<br>A modified parallel-in-parallel-out linear-systolic 8 × 8 power-sum circuit designed to perform AB(2)+C computations in the finite field GF(2(8)) is obtained, where A, B, and C are arbitrary elements of GF(2(8)). The architectures are constructed from 7 linear-systolic power-sum circuits. Moreover, we can use this architecture to obtain the exponentiation and division in GF(2(8)). The cycle time (i.e., clock period) of the presented architectures is only two logic gate delays plus a short routing delay. The circuit complexity of the presented circuits is reali

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Lu, Wen-Ming, and 呂文閔. "A VLSI Architecture for Multiple Motion Estimation Algorithms." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/02236946422703081754.

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碩士<br>中原大學<br>電機工程研究所<br>90<br>In this thesis, we propose a systolic array architecture for implementing multiple block-matching algorithms. This architecture has three processing modes. The first mode is the “parallel” mode. This mode can effectively reduce computational time. The second mode, the “sequential” mode, reduces the I/O rate. The final mode is the “hybrid” mode. It combines the “parallel” mode and “sequential” mode. These modes can be effectively used for realization of various block-matching algorithms, such as full search algorithm, three step search algorithm and MVQ. In additi

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Chen, Qi-Ming, and 陳祈銘. "An8x8 inverse DCT architecture and its VLSI implementation." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/91134603673445979766.

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LIN, CHING-CHUNG, and 林正中. "An Efficient VLSI Architecture of 2DDiscrete Wavelet Transform." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/56265587604933485422.

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碩士<br>中華科技大學<br>電子工程研究所在職專班<br>100<br>The discrete wavelet transform (DWT) attaches great importance on signal analysis and data compression. The signal is divided into low-frequency and high-frequency subbands after the wavelet transform. It achieves signal processing goals in accordance with the different properties of each subband. When DWT is applied to real-time multimedia processing, the speed benefit of hardware implementation must be considered. Traditionally, DWT architecture was convolution-based and needs extra large computations. In 1996, lifting-based DWT was proposed by Sweldens.

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Lian, Li-Xun, and 連禮勳. "VLSI Architecture Design for SVM-Based Speaker Verification." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/27065860051371223598.

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Abstract:

碩士<br>國立中央大學<br>資訊工程學系<br>101<br>This paper presents a VLSI chip design for support vector machine (SVM) and GMM-Supervector (Gaussian Mixture Model-Supervector) based speaker verification. In SVM-Based method, the proposed chip consists mainly of a speaker feature extraction (SFE) module, an SVM module, and a decision module. The SFE module performs autocorrelation analysis, linear predictive coefficient (LPC) extraction, and LPC to cepstrum conversion. The SVM module includes a Gaussian kernel unit and a scaling unit. The purpose of Gaussian kernel unit is to evaluate the kernel value of a t

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