Log in

Relevant bibliographies by topics / VLSI architecture / Journal articles

To see the other types of publications on this topic, follow the link: VLSI architecture.

Journal articles on the topic 'VLSI architecture'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'VLSI architecture.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

ACHARYA, TINKU, and AMAR MUKHERJEE. "HIGH-SPEED PARALLEL VLSI ARCHITECTURES FOR IMAGE DECORRELATION." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (1995): 343–65. http://dx.doi.org/10.1142/s021800149500016x.

Full text

Abstract:

We present a new high speed parallel architecture and its VLSI implementation to design a special purpose hardware for real-time lossless image compression/ decompression using a decorrelation scheme. The proposed architecture can easily be implemented using state-of-the-art VLSI technology. The hardware yields a high compression rate. A prototype 1-micron VLSI chip based on this architectural idea has been designed. The scheme is favourably comparable to the lossless JPEG standard image compression schemes. We also discuss the parallelization issues of the lossless JPEG standard still compres

APA, Harvard, Vancouver, ISO, and other styles

2

LEE, HANHO, and GERALD E. SOBELMAN. "VLSI DESIGN OF DIGIT-SERIAL FPGA ARCHITECTURE." Journal of Circuits, Systems and Computers 13, no. 01 (2004): 17–52. http://dx.doi.org/10.1142/s021812660400126x.

Full text

Abstract:

This paper presents a novel application-specific field-programmable gate array (FPGA) architecture that satisfies efficient implementation of digit-serial DSP architectures on a digit wide basis. Digit-serial DSP designs have been an effective implementation method for FPGAs. To efficiently realize a digit-serial DSP design on FPGAs, one must create an FPGA architecture optimized for those types of systems. We examine the various circuits used in digit-serial DSP designs to extract their key features that should be reflected in the new FPGA architecture. We explain the design methodology, layo

APA, Harvard, Vancouver, ISO, and other styles

3

Hicks, P. J. "Book Review: VLSI Architecture." International Journal of Electrical Engineering Education 22, no. 3 (1985): 244. http://dx.doi.org/10.1177/002072098502200314.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Hirayama, M. "VLSI oriented asynchronous architecture." ACM SIGARCH Computer Architecture News 14, no. 2 (1986): 290–96. http://dx.doi.org/10.1145/17356.17390.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

ERTEN, GAIL, and FATHI M. SALAM. "TWO CELLULAR ARCHITECTURES FOR INTEGRATED IMAGE SENSING AND PROCESSING ON A SINGLE CHIP." Journal of Circuits, Systems and Computers 08, no. 05n06 (1998): 637–59. http://dx.doi.org/10.1142/s0218126698000407.

Full text

Abstract:

Two architectures for a programmable image processor with on-chip light sensing capability are described. The first is a VLSI implementation of a cellular neural network. The second is a distributed dual-structure mutation of the first architecture. The distributed dual architecture leverages the speed of silicon against the large silicon area requirements. Moreover, the innovative integrated nature of the dual-structure design significantly reduces the bottleneck and computational overload caused by data transfer from sensory focal plane to the image processor. The paper also describes VLSI c

APA, Harvard, Vancouver, ISO, and other styles

6

Korneev, V. V., and I. E. Tarasov. "VLSI Architecture with a Configurable Pipeline." Programmnaya Ingeneria 11, no. 5 (2020): 270–76. http://dx.doi.org/10.17587/prin.11.270-276.

Full text

Abstract:

The analysis carried out in the article shows the possibility of creating a problem-oriented VLSI, fabricated according to the technological standards of 28 nm or less, for at least one family of digital signal processing problems using similar computing nodes in structure. The use of distributed arithmetic allows one to apply a technique based on performing only those multiplication steps for which non-zero digits are set in the corresponding positions of the filter coefficients. Therefore, the performance of 200 nodes executing 2 steps at 1 GHz is equivalent to approximately 80 GMAC/s/mm2 fo

APA, Harvard, Vancouver, ISO, and other styles

7

Chiper, Doru Florin. "An Improved VLSI Algorithm for an Efficient VLSI Implementation of a Type IV DCT That Allows an Efficient Incorporation of Hardware Security with a Low Overhead." Electronics 12, no. 1 (2023): 243. http://dx.doi.org/10.3390/electronics12010243.

Full text

Abstract:

This paper aims to solve one of the most challenging problems in designing VLSI chips for common goods, namely an efficient incorporation of security techniques while maintaining high performances of the VLSI implementation with a reduced hardware complexity. In this case, it is very important to maintain high performance at a low hardware complexity and the overheads introduced by the security techniques should be as low as possible. This paper proposes an improved approach based on a new VLSI algorithm for including the obfuscation technique in the VLSI implementation of one important DSP al

APA, Harvard, Vancouver, ISO, and other styles

8

Ryzhenko, Igor Nikolaevich, Oleg Vladimirovich Nepomnyaschy, Aleksandr Ivanovich Legalov, and Vladimir Viktorovich Shaidurov. "Methods for Change Parallelism in Process of High-level VLSI Synthesis." Modeling and Analysis of Information Systems 29, no. 1 (2022): 60–72. http://dx.doi.org/10.18255/1818-1015-2022-1-60-72.

Full text

Abstract:

In this paper methods for increasing the efficiency of VLSI development based on the method of architecture-independent design are proposed. The route of high-level VLSI synthesis is considered. The principle of constructing a VLSI hardware model based on the functional-flow programming paradigm is stated.The results of the development of methods and algorithms for transformation functional-parallel programs into programs in HDL languages that support the design process of digital chips are presented. The principles of assessment are considered and the classes of resources required for the ana

APA, Harvard, Vancouver, ISO, and other styles

9

Pushpalatha, P., and K. Babulu. "Design and implementation of systolic architecture based FIR filter." i-manager's Journal on Digital Signal Processing 10, no. 1 (2022): 17. http://dx.doi.org/10.26634/jdp.10.1.18852.

Full text

Abstract:

In signal processing, a filter is a device or process that removes some unwanted components or features from a signal. Digital filters are mainly divided into Infinite Impulse Response (IIR) filters and Finite Impulse Response (FIR) filters. FIR filters are mostly used in applications like image processing, communications, Digital Signal Processing (DSP) etc. One of the most used filters for designing of VLSI circuits is FIR filter. Systolic architecture is a Processing Element (PE) network that generates and passes data rhythmically through the system. The concept of systolic architecture can

APA, Harvard, Vancouver, ISO, and other styles

10

Jeevitha, M., and R. Muthaiah. "VLSI Based Combined Multiplier Architecture." Journal of Artificial Intelligence 6, no. 2 (2013): 145–53. http://dx.doi.org/10.3923/jai.2013.145.153.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Srinivas, H. R., and K. K. Parhi. "A fast VLSI adder architecture." IEEE Journal of Solid-State Circuits 27, no. 5 (1992): 761–67. http://dx.doi.org/10.1109/4.133165.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Wang, Cheng T. "VLSI architecture for device simulation." Integration 4, no. 2 (1986): 135–53. http://dx.doi.org/10.1016/s0167-9260(86)80004-9.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Stamenković, Zoran. "Physical architecture of VLSI systems." Microelectronics Reliability 37, no. 2 (1997): 369. http://dx.doi.org/10.1016/s0026-2714(97)81481-3.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Stamenković, Zoran. "Physical architecture of VLSI systems." Microelectronics Journal 27, no. 8 (1996): 806. http://dx.doi.org/10.1016/0026-2692(96)82783-2.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

G.W.A.D. "VLSI RISC architecture and organization." Microelectronics Reliability 30, no. 1 (1990): 186. http://dx.doi.org/10.1016/0026-2714(90)90031-h.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

ELGAMEL, MOHAMED A., MAGDY A. BAYOUMI, AHMED M. SHAMS, and BERTRAND ZAVIDOVIQUE. "LOW POWER FULL SEARCH BLOCK MATCHING MOTION ESTIMATION VLSI ARCHITECTURES." Journal of Circuits, Systems and Computers 13, no. 06 (2004): 1271–88. http://dx.doi.org/10.1142/s0218126604001945.

Full text

Abstract:

Power consumption is very critical for portable video applications. During compression, the motion estimation unit consumes the largest portion of power since it performs a huge amount of computation. Different low power architectures for implementing the full-search block-matching (FSBM) motion estimation are discussed. Also, architectural enhancements to further reduce the power consumed during FSBM motion estimation without sacrificing throughput or optimality are presented. The proposed approach achieves these power savings by disabling portions of the architecture that perform unnecessary

APA, Harvard, Vancouver, ISO, and other styles

17

Choi, Hyun-Jun, Young-Ho Seo, and Dong-Wook Kim. "VLSI Architecture of High Performance Huffman Codec." Journal of the Korean Institute of Information and Communication Engineering 15, no. 2 (2011): 439–46. http://dx.doi.org/10.6109/jkiice.2011.15.2.439.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Chiper, Doru Florin, and Arcadie Cracan. "An Area-Efficient Unified VLSI Architecture for Type IV DCT/DST Having an Efficient Hardware Security with Low Overheads." Electronics 12, no. 21 (2023): 4471. http://dx.doi.org/10.3390/electronics12214471.

Full text

Abstract:

This paper introduces an efficient solution for designing a unified VLSI implementation for type IV DCT/DST while solving one challenging problem in obtaining high performance VLSI chips for common goods, which is solving the security of the hardware while obtaining a VLSI implementation with high performance. The new solution uses a new systolic array algorithm for type IV DST that can allow us to obtain an efficient unified VLSI architecture with one previously designed for type IV DCT. The proposed method uses special arithmetic structures that have been called quasi-cycle convolutions that

APA, Harvard, Vancouver, ISO, and other styles

19

Prathiba, A., Suyash Vardhan Srivathshav, Ramkumar P. E., Rajkamal E., and Kanchana Bhaaskaran V. S. "Lightweight VLSI Architectures for Image Encryption Applications." International Journal of Information Security and Privacy 16, no. 1 (2022): 1–23. http://dx.doi.org/10.4018/ijisp.291700.

Full text

Abstract:

Lightweight cryptography offers significant security service in constrained environments such as wireless sensor networks and Internet of Things. The focus of this article is to construct lightweight SPN block cipher architectures with substitution box based on finite fields. The paper also details the FPGA implementation of the lightweight symmetric block cipher algorithm of SPN type with combinational S-box. Restructuring of traditional look-up-table Substitution Box (S-Box) sub-structure with a combinational logic S-box is attempted. Elementary architectures namely the basic round architect

APA, Harvard, Vancouver, ISO, and other styles

20

Et. al., Deepti Gautam,. "Resourceful Fast Discrete Hartley Transform to Replace Discrete Fourier Transform with Implementation of DHT Algorithm for VLSI Architecture." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 10 (2021): 5290–98. http://dx.doi.org/10.17762/turcomat.v12i10.5329.

Full text

Abstract:

Discrete Fourier Transform (DFT) is used in a range of digital signal processing applications, such as signal and image compression systems, filter banks, signal representation or harmonic analysis. The Discrete Hartley Transform (DHT) can be used to effectively replace the DFT when the input sequence is real. This paper introduces and applies the Discrete Hartley Transform (DHT) algorithm, which is well suited to the VLSI architecture. The purpose of using the DHT algorithm is to reduce the complexity of the VLSI architecture. With the introduction of VLSI architectures, 100,000 transistors c

APA, Harvard, Vancouver, ISO, and other styles

21

Seo, Youngho, and Dong-Wook Kim. "High-Performance VLSI Architecture for Stereo Vision." Journal of Broadcast Engineering 18, no. 5 (2013): 669–79. http://dx.doi.org/10.5909/jbe.2013.18.5.669.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Researcher. "DESIGN AND IMPLEMENTATION OF LOW POWER PIPELINED FFT ARCHITECTURE FOR DSP APPLICATION." International Journal of Advanced Research in Engineering and Technology (IJARET) 15, no. 4 (2024): 86–94. https://doi.org/10.5281/zenodo.13166453.

Full text

Abstract:

The swift advancements in signal analysis applications have heightened the need for efficient, high-performance architectures to execute complex algorithms like the Quick Fourier Transform (FFT). This study introduces a VLSI implementation of a pipelined FFT architecture customized for DSP applications, addressing challenges in real-time processing, power consumption, and resource utilization. By exploiting the parallelism of the FFT algorithm and using pipelining techniques, our design achieves high throughput and low latency with minimal area overhead and power consumption. Implemented throu

APA, Harvard, Vancouver, ISO, and other styles

23

COTOROBAI, LAURA TEODORA, and DORU FLORIN CHIPER. "An efficient algorithm and architecture for the VLSI implementation of type IV DST using short quasi-band correlation structures allowing efficient incorporation of techniques used for hardware security." Journal of Engineering Sciences and Innovation 9, no. 3 (2024): 343–54. https://doi.org/10.56958/jesi.2024.9.3.343.

Full text

Abstract:

This paper addresses a critical issue in VLSI chip design, specifically the integration of hardware security techniques. It introduces an improved algorithm for the efficient VLSI implementation of Type IV Discrete Sine Transform (DST-IV) using short quasi-band correlation structures. The proposed algorithm is restructured to facilitate the incorporation of key hardware security techniques with low overheads. This integration ensures the security and integrity of the VLSI implementation while maintaining high performance. By leveraging the regular and modular structure of the quasi-band correl

APA, Harvard, Vancouver, ISO, and other styles

24

Shi, Jiang Yi, Jie Pang, Zhi Xiong Di, Yao Hui Liu, and Yun Song Li. "High Throughput VLSI Architecture of MQ-Coder for JPEG2000." Advanced Materials Research 403-408 (November 2011): 2321–24. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.2321.

Full text

Abstract:

In this paper, a design of high throughput VLSI architecture of MQ-Coder is proposed. Usually, because the regular operation of the MQ-Coder is sequential, the coding speed will be bottlenecked at the interface between the output of the Bit-Plane coding and the input of the MQ-Coder. Therefore, the proposed MQ-Coder architecture can process two symbols for each clock cycle. The main characteristics are the prediction of index, the simplified condition of renormalization, and the partly parallel architecture in renormalization. From synthesis results of the DC tools, using the TSMC 0.18 μm tech

APA, Harvard, Vancouver, ISO, and other styles

25

Sukanya, Gundla, and T. Satya Savithri. "VLSI Architecture for Edge Detection of Leaf Images." Transactions on Engineering and Computing Sciences 13, no. 02 (2025): 134–43. https://doi.org/10.14738/tecs.1302.18612.

Full text

Abstract:

This paper proposed a new VLSI Architecture for Sobel Edge detector for Cotton and Grape leaf images. This new VLSI Architecture is tested for leaf images using Verilog HDL and Simulated and Synthesized using Xilinx Vivado tool and results shown the low power and low area, utilized less than 0.01% of LUTs and 0.13 w of power only. The same architecture is also extended for Prewitt and Laplace Edge detectors and results shown that utility of power and area is less.

APA, Harvard, Vancouver, ISO, and other styles

26

Sukanya, Gundla. "VLSI Architecture for Edge Detection of Leaf Images." Transactions on Machine Learning and Artificial Intelligence 13, no. 02 (2025): 134–43. https://doi.org/10.14738/tmlai.1302.18612.

Full text

Abstract:

This paper proposed a new VLSI Architecture for Sobel Edge detector for Cotton and Grape leaf images. This new VLSI Architecture is tested for leaf images using Verilog HDL and Simulated and Synthesized using Xilinx Vivado tool and results shown the low power and low area, utilized less than 0.01% of LUTs and 0.13 w of power only. The same architecture is also extended for Prewitt and Laplace Edge detectors and results shown that utility of power and area is less.

APA, Harvard, Vancouver, ISO, and other styles

27

Chakraborty, Anirban, and Ayan Banerjee. "A Memory Efficient, Multiplierless & Modular VLSI Architecture of 1D/2D Re-Configurable 9/7 & 5/3 DWT Filters Using Distributed Arithmetic." Journal of Circuits, Systems and Computers 29, no. 09 (2020): 2050151. http://dx.doi.org/10.1142/s0218126620501510.

Full text

Abstract:

Dedicated hardware for “Discrete Wavelet Transform” (DWT) is at high demand for real-time imaging operations in any standalone electronic devices, as DWT is being extensively utilized for most of the transform-domain imagery applications. Various DWT algorithms exist in the literature facilitating its software implementations which are generally unsuitable for real-time imaging in any stand-alone devices due to their power intensiveness and huge computation time. In this paper, a convolutional DWT-based pipelined and tunable VLSI architecture of Daubechies 9/7 and 5/3 DWT filter is presented.

APA, Harvard, Vancouver, ISO, and other styles

28

Chiper, Doru Florin, and Arcadie Cracan. "An Efficient Algorithm and Architecture for the VLSI Implementation of Integer DCT That Allows an Efficient Incorporation of the Hardware Security with a Low Overhead." Applied Sciences 13, no. 12 (2023): 6927. http://dx.doi.org/10.3390/app13126927.

Full text

Abstract:

In this paper, we propose a new hardware algorithm for an integer based discrete cosine transform (IntDCT) that was designed to allow an efficient VLSI implementation of the discrete cosine transform using the systolic array architectural paradigm. The proposed algorithm demonstrates multiple benefits specific to integer transforms with efficient hardware implementation and sufficient precision in approximating irrational transform coefficients for practical applications. The proposed integer DCT algorithm can be efficiently restructured into five regular and modular computational structures o

APA, Harvard, Vancouver, ISO, and other styles

29

Hedaoo, Priyanka, Dr U. M. Gokhale, and Prof Shweta Thakur. "VLSI Architecture for MB-OFDM Transmitter." IOSR journal of VLSI and Signal Processing 4, no. 3 (2014): 14–22. http://dx.doi.org/10.9790/4200-04321422.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Khorsheed Al-Sulaifanie, Ahmed. "VLSI Architecture for Real Time IWT." AL-Rafdain Engineering Journal (AREJ) 14, no. 3 (2006): 1–13. http://dx.doi.org/10.33899/rengj.2006.45302.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

SALEH, ALI NABI, and AHMED K. AL-SULAIFANIE. "REAL TIME VLSI IWT DENOSING ARCHITECTURE." Journal of The University of Duhok 20, no. 1 (2017): 164–74. http://dx.doi.org/10.26682/sjuod.2017.20.1.15.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Zhang, Yanjun, and S. Q. Zheng. "An Efficient Parallel VLSI Sorting Architecture." VLSI Design 11, no. 2 (2000): 137–47. http://dx.doi.org/10.1155/2000/14617.

Full text

Abstract:

We present a new parallel sorting algorithm that uses a fixed-size sorter iteratively to sort inputs of arbitrary size. A parallel sorting architecture based on this algorithm is proposed. This architecture consists of three components, linear arrays that support constant-time operations, a multilevel sorting network, and a termination detection tree, all operating concurrently in systolic processing fashion. The structure of this sorting architecture is simple and regular, highly suitable for VLSI realization. Theoretical analysis and experimental data indicate that the performance of this ar

APA, Harvard, Vancouver, ISO, and other styles

33

Leibo Liu, Ning Chen, Hongying Meng, Li Zhang, Zhihua Wang, and Hongyi Chen. "A VLSI architecture of JPEG2000 encoder." IEEE Journal of Solid-State Circuits 39, no. 11 (2004): 2032–40. http://dx.doi.org/10.1109/jssc.2004.831492.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Brown, C. I., and R. B. Yates. "VLSI architecture for sparse matrix multiplication." Electronics Letters 32, no. 10 (1996): 891. http://dx.doi.org/10.1049/el:19960606.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Cheng, H. D., H. S. Don, and L. T. Kou. "VLSI architecture for digital picture comparison." IEEE Transactions on Circuits and Systems 36, no. 10 (1989): 1326–35. http://dx.doi.org/10.1109/31.44339.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Huang, Jian, and Jooheung Lee. "Efficient VLSI architecture for video transcoding." IEEE Transactions on Consumer Electronics 55, no. 3 (2009): 1462–70. http://dx.doi.org/10.1109/tce.2009.5278014.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Wen-Jyi Hwang, Chien-Min Ou, Wen-Ming Lu, and Chun-Fu Lin. "VLSI architecture for motion vector quantization." IEEE Transactions on Consumer Electronics 49, no. 1 (2003): 237–42. http://dx.doi.org/10.1109/tce.2003.1205482.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Mason, R., W. Robertson, and D. Pincock. "An hierarchical VLSI neural network architecture." IEEE Journal of Solid-State Circuits 27, no. 1 (1992): 106–8. http://dx.doi.org/10.1109/4.109562.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Sakamura, Ken. "Architecture of the TRON VLSI CPU." IEEE Micro 7, no. 2 (1987): 17–31. http://dx.doi.org/10.1109/mm.1987.304839.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Hortensius, Peter D., Howard C. Card, and Robert D. McLeod. "A VLSI architecture for percolation simulation." Journal of Computational Physics 84, no. 1 (1989): 76–89. http://dx.doi.org/10.1016/0021-9991(89)90182-4.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Jeong, H., J. H. Park, H. Y. Ryu, J. B. Kwon, and Y. Oh. "VLSI architecture for SAR data compression." IEEE Transactions on Aerospace and Electronic Systems 38, no. 2 (2002): 427–40. http://dx.doi.org/10.1109/taes.2002.1008977.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Jong-Suk Lee and Dong Sam Ha. "FleXilicon Architecture and Its VLSI Implementation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 8 (2009): 1021–33. http://dx.doi.org/10.1109/tvlsi.2009.2017440.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

P., Bosebabu, Bhargavi A., Vijayalakshmi P., and Surabhi Jyostna Roja R. "VLSI Architecture for Zero Frequency Filter." International Journal of Advance Research and Innovation 8, no. 2 (2020): 81–86. http://dx.doi.org/10.51976/ijari.822014.

Full text

Abstract:

Now a days everyone is using mobile phones. Mobile phones play an important role in communication. While using mobile phones, people face the problem of noise signals. These noise signals are affecting the quality of speech signals. These noise signals maybe produced from the materials or sources such as echoes, crowded places, etc. For example, when we speak over the mobile phone or in any crowded place, the external noise adds up like the noise of the subway, train, car, etc. In real time to remove external noise is a very crucial task. A lot of research has been done in cancelling the backg

APA, Harvard, Vancouver, ISO, and other styles

44

Kumari, Dr K. S. Neelu, Santhosh P, Selvakumar T, and Sridhar J. "Scalable Vlsi Architecture For Deep Learning - Based Arrhythmia Identification." International Journal of Research Publication and Reviews 6, no. 5 (2025): 11147–53. https://doi.org/10.55248/gengpi.6.0525.1897.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

WAHID, KHAN, VASSIL DIMITROV, and GRAHAM JULLIEN. "VLSI ARCHITECTURES OF DAUBECHIES WAVELET TRANSFORMS USING ALGEBRAIC INTEGERS." Journal of Circuits, Systems and Computers 13, no. 06 (2004): 1251–70. http://dx.doi.org/10.1142/s0218126604001982.

Full text

Abstract:

Two-Dimensional Wavelet Transforms have proven to be highly effective tools for image analysis. In this paper, we present a VLSI implementation of four- and six-coefficient Daubechies Wavelet Transforms using an algebraic integer encoding representation for the coefficients. The Daubechies filters (DAUB4 and DAUB6) provide excellent spatial and spectral locality, properties which make it useful in image compression. In our algorithm, the algebraic integer representation of the wavelet coefficients provides error-free calculations until the final reconstruction step. This also makes the VLSI ar

APA, Harvard, Vancouver, ISO, and other styles

46

Гришанов, Н. В., А. В. Зверев, Д. Е. Ипатов та ін. "НЕЙРОМОРФНЫЙ ПРОЦЕССОР «АЛТАЙ» ДЛЯ ЭНЕРГОЭФФЕКТИВНЫХ ВЫЧИСЛЕНИЙ". NANOINDUSTRY Russia 96, № 3s (2020): 531–38. http://dx.doi.org/10.22184/1993-8578.2020.13.3s.531.538.

Full text

Abstract:

Предложена масштабируемая нейроморфная архитектура для исполнения импульсных нейронных сетей, разработан прототип СБИС с данной архитектурой. Проведены оценки энергопотребления проекта прототипа СБИС при распознавании тестовых изображений из наборов MNIST и CIFAR-10. The paper presents a scalable neuromorphic architecture for spiking neural network inference. A VLSI prototype based on this architecture has been developed. The energy consumption of the VLSI prototype project was estimated during a test image recognition from the MNIST and CIFAR-10 sets.

APA, Harvard, Vancouver, ISO, and other styles

47

Chiper, Doru Florin, and Laura-Teodora Cotorobai. "A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique." Electronics 10, no. 14 (2021): 1656. http://dx.doi.org/10.3390/electronics10141656.

Full text

Abstract:

This paper aims at solving one challenging problem in designing VLSI chips, namely, the security of the hardware, by presenting a new design approach that incorporates the obfuscation technique in the VLSI implementation of some important DSP algorithms. The proposed method introduces a new approach in obtaining a unified VLSI architecture for computing type IV discrete cosine transform (DCT-IV) and type IV discrete sine transform (DST-IV), with an efficient integration of the obfuscation technique, while maintaining low overheads. The algorithms for these two transforms were restructured in s

APA, Harvard, Vancouver, ISO, and other styles

48

Meena, Nitish, and Nilesh Parihar. "Real-Time Algorithms and Architectures for several user Channel Detection in Wireless Base Station Receivers." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 2 (2015): 82. http://dx.doi.org/10.11591/ijres.v4.i2.pp82-98.

Full text

Abstract:

In this paper presents algorithms and architecture designs that can meet real-time requirements of for several user channel estimation and detection in code-division multiple-access-based wireless base-station receivers. Entangled algorithms proposed to implement several user channel assessment and demodulation make their real-time execution difficult on current digital signal processor-based receivers. A based several user channel assessment scheme requiring matrix conversion is draft again from an demodulation perspective for a reduced intricacy, repetitive scheme with a simple fixed-point v

APA, Harvard, Vancouver, ISO, and other styles

49

Kameyama, Michitaka, and Yoshichika Fujioka. "VLSI Processor System for Robotics." Journal of Robotics and Mechatronics 8, no. 6 (1996): 496–99. http://dx.doi.org/10.20965/jrm.1996.p0496.

Full text

Abstract:

As one of the next-generation information systems, it is important to construct intelligent integrated systems that have quick response for dynamically changing environment. Therefore, it becomes essential to develop the special purpose VLSI processors which are based on the philosophy ""great reduction of the delay time."" Particularly, we call it robot electronics to develop the special purpose VLSI processors for intelligent robot control. In this article, we will review the fundamental technologies such as pipeline architecture, spacial parallel processing, reconfigurable parallel architec

APA, Harvard, Vancouver, ISO, and other styles

50

Moses, C. John, D. Selvathi, and V. M. Anne Sophia. "VLSI Architectures for Image Interpolation: A Survey." VLSI Design 2014 (May 19, 2014): 1–10. http://dx.doi.org/10.1155/2014/872501.

Full text

Abstract:

Image interpolation is a method of estimating the values at unknown points using the known data points. This procedure is used in expanding and contrasting digital images. In this survey, different types of interpolation algorithm and their hardware architecture have been analyzed and compared. They are bilinear, winscale, bi-cubic, linear convolution, extended linear, piecewise linear, adaptive bilinear, first order polynomial, and edge enhanced interpolation architectures. The algorithms are implemented for different types of field programmable gate array (FPGA) and/or by different types of

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!