Log in

Relevant bibliographies by topics / VLSI CAD / Dissertations / Theses

To see the other types of publications on this topic, follow the link: VLSI CAD.

Dissertations / Theses on the topic 'VLSI CAD'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 dissertations / theses for your research on the topic 'VLSI CAD.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.

1

Liu, Huiqun. "Circuit partitioning algorithms for CAD VLSI design /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Minato, Shin-ichi. "Binary Decision Diagrams and Their Applications for VLSI CAD." Kyoto University, 1995. http://hdl.handle.net/2433/160759.

Full text

Abstract:

本文データは平成22年度国立国会図書館の学位論文(博士)のデジタル化実施により作成された画像ファイルを基にpdf変換したものである<br>Kyoto University (京都大学)<br>0048<br>新制・課程博士<br>博士(工学)<br>甲第6015号<br>工博第1412号<br>新制||工||984(附属図書館)<br>UT51-95-D334<br>京都大学大学院工学研究科情報工学専攻<br>(主査)教授失島脩三, 教授上林彌彦, 教授石田亨<br>学位規則第4条第1項該当

APA, Harvard, Vancouver, ISO, and other styles

3

Cao, Ke. "Design for manufacturing (DFM) in submicron VLSI design." Thesis, [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-1430.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Hu, Shiyan. "Algorithmic techniques for nanometer VLSI design and manufacturing closure." Texas A&M University, 2008. http://hdl.handle.net/1969.1/85905.

Full text

Abstract:

As Very Large Scale Integration (VLSI) technology moves to the nanoscale regime, design and manufacturing closure becomes very difficult to achieve due to increasing chip and power density. Imperfections due to process, voltage and temperature variations aggravate the problem. Uncertainty in electrical characteristic of individual device and wire may cause significant performance deviations or even functional failures. These impose tremendous challenges to the continuation of Moore's law as well as the growth of semiconductor industry. Efforts are needed in both deterministic design stage and

APA, Harvard, Vancouver, ISO, and other styles

5

Waghmode, Mandar. "Buffer insertion in large circuits using look-ahead and back-off techniques." Texas A&M University, 2005. http://hdl.handle.net/1969.1/4674.

Full text

Abstract:

Buffer insertion is an essential technique for reducing interconnect delay in submicron circuits. Though it is a well researched area, there is a need for robust and effective algorithms to perform buffer insertion at the circuit level. This thesis proposes a new buffer insertion algorithm for large circuits. The algorithm finds a buffering solution for the entire circuit such that buffer cost is minimized and the timing requirements of the circuit are satisfied. The algorithm iteratively inserts buffers in the circuit improving the circuit delay step by step. At the core of this algorithm are

APA, Harvard, Vancouver, ISO, and other styles

6

Reimann, Tiago Jose. "Roteamento global de circuitos VLSI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/71269.

Full text

Abstract:

Este trabalho apresenta a implementação de um roteador global de circuitos integrados capaz de tratar os problemas de roteamento atuais, utilizando como referência para avaliação os circuitos de benchmark publicados durante as competições de roteamento global realizadas no ACM International Symposium on Physical Design 2007 e 2008. O roteador global desenvolvido utiliza como ferramenta principal a técnica de ripup and reroute associada às técnicas de roteamento monotônico e maze routing, ambas com grande histórico de uso nas ferramentas acadêmicas descritas também neste trabalho. O desenvolvim

APA, Harvard, Vancouver, ISO, and other styles

7

Johann, Marcelo de Oliveira. "Novos algoritmos para roteamento de circuitos VLSI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2001. http://hdl.handle.net/10183/2177.

Full text

Abstract:

Este trabalho apresenta novos algoritmos para o roteamento de circuitos integrados, e discute sua aplicação em sistemas de síntese de leiaute. As interconexões têm grande impacto no desempenho de circuitos em tecnologias recentes, e os algoritmos propostos visam conferir maior controle sobre sua qualidade, e maior convergência na tarefa de encontrar uma solução aceitável. De todos os problemas de roteamento, dois são de especial importância: roteamento de redes uma a uma com algoritmos de pesquisa de caminhos, e o chamado roteamento de área. Para o primeiro, procura-se desenvolver um algoritmo

APA, Harvard, Vancouver, ISO, and other styles

8

Marchioro, Gilberto Fernandes. "Silex : sistema para a integração de ferramentas de projeto de circuitos integrados." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1992. http://hdl.handle.net/10183/26381.

Full text

Abstract:

SILEX é um ambiente aberto e integrado que busca auxiliar a concepção de CIs. 0 sistema e composto por ferramentas internas (servidoras de recursos) e ferramentas do usuário (clientes de recursos). O usuário interage com o sistema SILEX através de uma interface gráfica baseada em janelas, ativando os recursos de forma padronizada e consistente. Sendo um sistema de CAD, SILEX e formado por um conjunto de módulos (ferramentas) interdependentes. Cada módulo realiza a sua função e transmite seus resultados. O usuário torna-se cliente de um conjunto de processos que concorrentemente responde as sua

APA, Harvard, Vancouver, ISO, and other styles

9

Hentschke, Renato Fernandes. "Algoritmos para o posicionamento de células em circuitos VLSI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2002. http://hdl.handle.net/10183/2598.

Full text

Abstract:

Este trabalho faz uma análise ampla sobre os algoritmos de posicionamento. Diversos são extraídos da literatura e de publicações recentes de posicionamento. Eles foram implementados para uma comparação mais precisa. Novos métodos são propostos, com resultados promissores. A maior parte dos algoritmos, ao contrário do que costuma encontrar-se na literatura, é explicada com detalhes de implementação, de forma que não fiquem questões em aberto. Isto só possível pela forte base de implementação por trás deste texto. O algorítmo de Fidduccia Mateyeses, por exemplo, é um algorítmo complexo e por ist

APA, Harvard, Vancouver, ISO, and other styles

10

GIBSON, DENNIS. "INTEGRATING BEHAVIORAL MODELING AND SIMULATION FOR MEMS COMPONENTS INTO CAD FOR VLSI." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1029435944.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Gibson, Dennis. "Integrating behavioral modeling & simulation for MEMS components into CAD for VLSI." Cincinnati, Ohio : University of Cincinnati, 2000. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=ucin1029435944.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Ziesemer, Junior Adriel Mota. "Geração automática de partes operativas de circuitos VLSI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/15530.

Full text

Abstract:

Tanto nos circuitos integrados para processamento de sinais digitais quanto em microprocessadores, a parte operativa é o núcleo onde a computação dos dados é realizada. A geração deste bloco costuma ser crítica para o desempenho global dos dispositivos. Ferramentas específicas para a geração de parte operativa costumam tirar proveito da regularidade estrutural do circuito para produzir leiautes mais densos e com melhor desempenho. Este trabalho apresenta um novo fluxo de projeto para geração de parte operativa onde foi desenvolvido um gerador automático de leiaute de células CMOS com suporte à

APA, Harvard, Vancouver, ISO, and other styles

13

Li, Zhuo. "Fast interconnect optimization." Texas A&M University, 2005. http://hdl.handle.net/1969.1/3250.

Full text

Abstract:

As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high performance designs. For the gigahertz microprocessor and multi-million gate ASIC designs it is crucial to have fast algorithms in the design automation tools for many classical problems in the field to shorten time to market of the VLSI chip. This research presents algorithmic techniques and constructive models for two such problems: (1) Fast buffer insertion for delay

APA, Harvard, Vancouver, ISO, and other styles

14

Guntzel, José Luis Almada. "Geração de circuitos utilizando matrizes de células pré-difundidas." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1993. http://hdl.handle.net/10183/28638.

Full text

Abstract:

Este trabalho propõe e avalia uma nova abordagem para projeto de circuitos dedicados utilizando matrizes pré-difundidas. A principal vantagem desta abordagem, denominada Marcela, reside na decomposição lógica do circuito a ser implementado em termos de primitivas disponíveis na matriz escolhida. Aplicando-se tal procedimento, alcança-se grande flexibilidade em termos de posicionamento e roteamento, levando a uma melhor taxa de ocupação. Primeiramente, é feito um levantamento das abordagens para pré-difundidos correntemente encontradas e uma taxonomia baseada nas características mais relevantes

APA, Harvard, Vancouver, ISO, and other styles

15

Santos, Luiz Cláudio Villar dos. "Exploiting instruction-level parallelism a constructive approach /." Eindhoven : Technische Universiteit Eindhoven, 1998. http://catalog.hathitrust.org/api/volumes/oclc/40847445.html.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Komari, Prabanjan. "A Novel Simulation Based Approach for Trace Signal Selection in Silicon Debug." University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1468512478.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Sawicki, Sandro. "Particionamento de células e pads de I/O em circuitos VLSI 3D." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/26502.

Full text

Abstract:

A etapa de particionamento em circuitos VLSI 3D é fundamental na distribuição de células e blocos para as camadas do circuito, além de auxiliar na redução da complexidade dos posicionadores. Estes, quando o particionamento é bem realizado, permitem que se atinjam soluções com menor comprimento total de fios, o que reduz a dissipação de potência e aumenta o desempenho dos circuitos. Atualmente, os algoritmos utilizados para resolver o problema de particionamento em circuitos 3D são adaptações daqueles aplicados em circuitos planares. Ou seja, o circuito é particionado como se fosse um hipergraf

APA, Harvard, Vancouver, ISO, and other styles

18

Bhattacharya, Koustav. "Architectures and algorithms for mitigation of soft errors in nanoscale VLSI circuits." [Tampa, Fla] : University of South Florida, 2009. http://purl.fcla.edu/usf/dc/et/SFE0003280.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Hentschke, Renato Fernandes. "Algorithms for wire length improvement of VLSI circuits with concern to critical paths." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/16300.

Full text

Abstract:

Esta tese objetiva propor algorítmos para a redução do tamanho dos fios em circuitos VLSI considerando elementos críticos dos circuitos. O problema é abordado em duas perspectivas diferentes: posicionamento e roteamento. Na abordagem de posicionamento, a tese explora métodos para realizar posicionamento de um tipo particular de circuito VLSI, que são conhecidos como circuitos 3D. Diferente de trabalhos anteriores, este tese aborda o problema considerando as conexões verticais (chamadas 3D-Vias) e as limitações impostas pelas mesmas. Foi realizado um fluxo completo, iniciando no tratamento de p

APA, Harvard, Vancouver, ISO, and other styles

20

Guntzel, Jose Luis Almada. "Functional timing analysis of VLSI circuits containing complex gates." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2000. http://hdl.handle.net/10183/1883.

Full text

Abstract:

Os recentes avanços experimentados pela tecnologia CMOS tem permitido a fabricação de transistores em dimensões submicrônicas, possibilitando a integração de dezenas de milhões de dispositivos numa única pastilha de silício, os quais podem ser usados na implementação de sistemas eletrônicos muito complexos. Este grande aumento na complexidade dos projetos fez surgir uma demanda por ferramentas de verificação eficientes e sobretudo que incorporassem modelos físicos e computacionais mais adequados. A verificação de timing objetiva determinar se as restrições temporais impostas ao projeto podem o

APA, Harvard, Vancouver, ISO, and other styles

21

Djigbenou, Jeannette Donan. "Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/32269.

Full text

Abstract:

Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design process, and is easier to maintain. Development of a cell library is laborious, prone to errors and even a small error on a library cell can possibly be disastrous due to repeated use of the cell in a design. In this thesis, we investigated ways to au

APA, Harvard, Vancouver, ISO, and other styles

22

Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

Full text

Abstract:

The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expen

APA, Harvard, Vancouver, ISO, and other styles

23

Vorwerk, Kristofer. "On The Engineering of a Stable Force-Directed Placer." Thesis, University of Waterloo, 2004. http://hdl.handle.net/10012/863.

Full text

Abstract:

Analytic and force-directed placement methods that simultaneously minimize wire length and spread cells are receiving renewed attention from both academia and industry. However, these methods are by no means trivial to implement---to date, published works have failed to provide sufficient engineering details to replicate results. This dissertation addresses the implementation of a generic force-directed placer entitled FDP. Specifically, this thesis provides (1) a description of efficient force computation for spreading cells, (2) an illustration of numerical instability in this

APA, Harvard, Vancouver, ISO, and other styles

24

Sundaresan, Vijay. "Architectural Synthesis Techniques for Design of Correct and Secure ICs." University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1217424117.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Mukherjee, Valmiki. "A Dual Dielectric Approach for Performance Aware Reduction of Gate Leakage in Combinational Circuits." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5255/.

Full text

Abstract:

Design of systems in the low-end nanometer domain has introduced new dimensions in power consumption and dissipation in CMOS devices. With continued and aggressive scaling, using low thickness SiO2 for the transistor gates, gate leakage due to gate oxide direct tunneling current has emerged as the major component of leakage in the CMOS circuits. Therefore, providing a solution to the issue of gate oxide leakage has become one of the key concerns in achieving low power and high performance CMOS VLSI circuits. In this thesis, a new approach is proposed involving dual dielectric of dual thickness

APA, Harvard, Vancouver, ISO, and other styles

26

Moraes, Fernando Gehm. "Synthese topologique de macro-cellules en technologie cmos." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1994. http://hdl.handle.net/10183/17853.

Full text

Abstract:

Les problèmes majeurs de la génération automatique du dessin des masques des circuits intégrés sont la dépendance vis-à-vis des règles de dessin et le dimensionnement correct des transistors. Les méthodes traditionnelles, telles que l'utilisation de cellules pré-caractérisées, manquent de flexibilité, car les portes des bibliothèques (en nombre limité) sont dessinées et dimensionnées (independarnment de l'application) pour une technologie donnée. Les méthodes de synthèse automatique du dessin des masques ont pour but de surmonter ces problèmes. Les techniques les plus couramment utilisées sont

APA, Harvard, Vancouver, ISO, and other styles

27

Knechtel, Johann. "Interconnect Planning for Physical Design of 3D Integrated Circuits." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-143635.

Full text

Abstract:

Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automati

APA, Harvard, Vancouver, ISO, and other styles

28

Katzenelson, Jacob, and Richard Zippel. "Software Structuring Principles for VLSI CAD." 1987. http://hdl.handle.net/1721.1/6052.

Full text

Abstract:

A frustrating aspect of the frequent changes to large VLSI CAD systems is that so little of the old available programs can be reused. It takes too much time and effort to find the reusable pieces and recast them for the new use. Our thesis is that such systems can be designed for reusability by designing the software as layers of problem oriented languages, which are implemented by suitably extending a "base" language. We illustrate this methodology with respect to VLSI CAD programs and a particular language layer: a language for handling networks. We present two different implem

APA, Harvard, Vancouver, ISO, and other styles

29

DING, ZHENG-WEI, and 定正偉. "Constraints modeling in VLSI CAD databases." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/13129661282539045923.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Eum, Doo-hun. "Data-structure builder for VLSI/CAD software." Thesis, 1990. http://hdl.handle.net/1957/37167.

Full text

Abstract:

Relational database systems have successfully solved many business data processing problems. The primary reason of this success is that the relational data model provides a simple, yet flexible view of data as tables. In studying VLSI/CAD data, we noticed that they are often represented in formats similar to relational tuples. Therefore, they can be stored easily in relational tables. However, it is generally agreed that conventional relational database systems are inefficient for VLSI/CAD applications, since such applications often access large amounts of data repetitively. In order to solve

APA, Harvard, Vancouver, ISO, and other styles

31

Huang, Li-da. "CAD algorithms for VLSI design and manufacturing." Thesis, 2003. http://hdl.handle.net/2152/653.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Huang, Li-da Wong D. F. Mok Aloysius Ka-Lau. "CAD algorithms for VLSI design and manufacturing." 2003. http://wwwlib.umi.com/cr/utexas/fullcit?p3119530.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Chakraborty, Ashutosh. "Mechanical stress and circuit aging aware VLSI CAD." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2459.

Full text

Abstract:

With the gradual advance of the state-of-the-art VLSI manufacturing technology into the sub-45nm regime, engineering a reliable, high performance VLSI chip with economically attractive yield in accordance with Moore's law of scaling and integration has become extremely difficult. Some of the most serious challenges that make this task difficult are: a) the delay of a transistor is strongly dependent on process induced mechanical stress around it, b) the reliability of devices is affected by several aging mechanisms like Negative Bias Temperature Instability (NBTI), hot carrier injection (HCI),

APA, Harvard, Vancouver, ISO, and other styles

34

Frost, David Frank. "A CAD tool for the prediction of VLSI interconnect reliability." Thesis, 1988. http://hdl.handle.net/10413/6887.

Full text

Abstract:

This thesis proposes a new approach to the design of reliable VLSI interconnects, based on predictive failure models embedded in a software tool for reliability analysis. A method for predicting the failure rate of complex integrated circuit interconnects subject to electromigration, is presented. This method is based on the principle of fracturing an interconnect pattern into a number of statistically independent conductor segments. Five commonly-occurring segment types are identified: straight runs, steps resulting from a discontinuity in the wafer surface, contact windows, vias and bonding

APA, Harvard, Vancouver, ISO, and other styles

35

李健泉. "A multiple level abstraction hierarchy storage system for VLSI CAD." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/39928706402195966554.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

CHEN, YU-FENG, and 陳裕豐. "A private database management system for VLSI CAD design system." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/11437273289612085684.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Vorwerk, Kristofer. "On the Use of Directed Moves for Placement in VLSI CAD." Thesis, 2009. http://hdl.handle.net/10012/4528.

Full text

Abstract:

Search-based placement methods have long been used for placing integrated circuits targeting the field programmable gate array (FPGA) and standard cell design styles. Such methods offer the potential for high-quality solutions but often come at the cost of long run-times compared to alternative methods. This dissertation examines strategies for enhancing local search heuristics---and in particular, simulated annealing---through the application of directed moves. These moves help to guide a search-based optimizer by focusing efforts on states which are most likely to yield productive improve

APA, Harvard, Vancouver, ISO, and other styles

38

Sengupta, Chaitali. "An integrated CAD framework linking VLSI layout editors and process simulators." Thesis, 1995. http://hdl.handle.net/1911/13995.

Full text

Abstract:

This thesis presents an Integrated CAD Framework which links VLSI layout editors to lithographic simulators and provides information on the simulated resolution of a feature to the circuit designer. This will help designers to design more compact circuits, as they will be able to see the effect on manufactured silicon. The Framework identifies areas in a layout (in Magic or CIF format) that are more prone to problems arising out of the photolithographic process. It then creates the corresponding inputs for closer analysis with a process simulator (Depict) and analyzes the simulator outputs to

APA, Harvard, Vancouver, ISO, and other styles

39

WANG, RU-SHENG, та 王如生. "VLSI CAD數位語音系統之設計". Thesis, 1989. http://ndltd.ncl.edu.tw/handle/71358045761636633299.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Mangassarian, Hratch. "Pseudo-Boolean satisfiability and quantified Boolean formulas in CAD for VLSI." 2008. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=772091&T=F.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Cheng, Lei. "Novel CAD techniques for new challenges in deep sub-micron VLSI design /." 2007. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3290202.

Full text

Abstract:

Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2007.<br>Source: Dissertation Abstracts International, Volume: 68-11, Section: B, page: 7424. Advisers: Martin D. F. Wong; Deming Chen. Includes bibliographical references (leaves 139-146) Available on microfilm from Pro Quest Information and Learning.

APA, Harvard, Vancouver, ISO, and other styles

42

Wrona, Włodzimierz. "Metoda modelowania układów cyfrowych VLSI w językach obiektowo-zorientowanych." Rozprawa doktorska, 1990. https://repolis.bg.polsl.pl/dlibra/docmetadata?showContent=true&id=3386.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Wrona, Włodzimierz. "Metoda modelowania układów cyfrowych VLSI w językach obiektowo-zorientowanych." Rozprawa doktorska, 1990. https://delibra.bg.polsl.pl/dlibra/docmetadata?showContent=true&id=3386.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Kumar, Akhilesh. "CAD Techniques for Robust FPGA Design Under Variability." Thesis, 2010. http://hdl.handle.net/10012/5468.

Full text

Abstract:

The imperfections in the semiconductor fabrication process and uncertainty in operating environment of VLSI circuits have emerged as critical challenges for the semiconductor industry. These are generally termed as process and environment variations, which lead to uncertainty in performance and unreliable operation of the circuits. These problems have been further aggravated in scaled nanometer technologies due to increased process variations and reduced operating voltage. Several techniques have been proposed recently for designing digital VLSI circuits under variability. However, most o

APA, Harvard, Vancouver, ISO, and other styles

45

Μακρυδάκης, Ιωάννης. "Ανάπτυξη CAD εργαλείου για τη VLSI σχεδίαση συστολικών διατάξεων επεξεργαστών για αλγόριθμους επεξεργασίας σήματος". Thesis, 2008. http://nemertes.lis.upatras.gr/jspui/handle/10889/682.

Full text

Abstract:

Στο πλαίσιο αυτής της εργασίας μελετήθηκαν οι διατάξεις επεξεργαστών και πιο συγκεκριμένα οι συστολικές διατάξεις επεξεργαστών. Επίσης αναπτύχθηκε CAD εργαλείο για την αυτόματη VLSI σχεδίαση συστολικών διατάξεων επεξεργαστών για αλγόριθμους επεξεργασίας σήματος.<br>In this book were studied the processor arrays and more concretely the systolic processor arrays. Also was developed CAD tool for the automatic VLSI designing of systolic processor arrays on signal processing algorithms.

APA, Harvard, Vancouver, ISO, and other styles

46

Ding, Duo. "CAD for nanolithography and nanophotonics." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-08-4030.

Full text

Abstract:

As the semiconductor technology roadmap further extends, the development of next generation silicon systems becomes critically challenged. On the one hand, design and manufacturing closures become much more difficult due to the widening gap between the increasing integration density and the limited manufacturing capability. As a result, manufacturability issues become more and more critically challenged in the design of reliable silicon systems. On the other hand, the continuous scaling of feature size imposes critical issues on traditional interconnect materials (Cu/Low-K dielectrics) due to

APA, Harvard, Vancouver, ISO, and other styles

47

Huang, Kuo-Fuo, and 黃國富. "A CAD Tool for Optimal Fixed-point VLSI Structure of a Floating- point Based Digital Filter Design." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/48915573216138601669.

Full text

Abstract:

碩士<br>國立中央大學<br>電機工程學系<br>86<br>One of the major tasks of a system IC designer is to determine the VLSI architecture and assign wordlength for a given DSP design.However, there is still no known good CAD tools that can help thedesigners to determine these two design issues automatically.In this thesis, we develop a knowledge-based CAD tool to assistsystem IC designers with the fixed-point implementation of a prescribeddigital filter. The tool can analyze the finite-precision behaviorfor a g

APA, Harvard, Vancouver, ISO, and other styles

48

XIAO, PEI-YONG, and 蕭培墉. "With multiple storage quad tree on the constraint graph compaction of the VLSI/CAD large-cell layout-editor." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/30069665492836556585.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Haghdad, Kian. "Parametric Yield of VLSI Systems under Variability: Analysis and Design Solutions." Thesis, 2011. http://hdl.handle.net/10012/5892.

Full text

Abstract:

Variability has become one of the vital challenges that the designers of integrated circuits encounter. variability becomes increasingly important. Imperfect manufacturing process manifest itself as variations in the design parameters. These variations and those in the operating environment of VLSI circuits result in unexpected changes in the timing, power, and reliability of the circuits. With scaling transistor dimensions, process and environmental variations become significantly important in the modern VLSI design. A smaller feature size means that the physical characteristics of a device a

APA, Harvard, Vancouver, ISO, and other styles

50

"Radiation Hardened by Design Methodologies for Soft-Error Mitigated Digital Architectures." Doctoral diss., 2017. http://hdl.handle.net/2286/R.I.45554.

Full text

Abstract:

abstract: Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation descr

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!