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Journal articles on the topic 'VLSI CAD'

Author: Grafiati

Published: 4 June 2021

Last updated: 26 July 2025

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1

Jones, J. W. "CAD for VLSI." Electronics and Power 32, no. 1 (1986): 79. http://dx.doi.org/10.1049/ep.1986.0049.

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2

ATTAOUI, Yassine, Mohamed Chentouf, Zine El Abidine Alaoui Ismaili, and Aimad Elmourabit. "Machine Learning in VLSI Design: A Comprehensive Review." Journal of Integrated Circuits and Systems 19, no. 2 (2024): 1–14. http://dx.doi.org/10.29292/jics.v19i2.826.

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State-of-the-art ML applications and aspects of AI in VLSI/CAD EDA. As VLSI chip complexity increases, driven by shrinking chip sizes and higher performance demands, manufacturing high-performance chips poses significant challenges. Recent studies have investigated the use of Artificial Intelligence and Machine Learning in VLSI CAD/EDA (Computer-Aided Design/Electronic Design Automation). Machine Learning is experiencing a rapid growth in VLSI design and is being increasingly integrated into EDA tool development due to its capacity for achieving higher accuracy in reduced runtime. This paper o

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3

Shekar, K., and Sandhya Rachamalla. "A Survey on Machine Learning Applications in VLSI CAD." International Journal of Computer Science & Engineering Survey 15, no. 5 (2024): 01–09. http://dx.doi.org/10.5121/ijcses.2024.15501.

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The incorporation of machine learning (ML) methodologies into VLSI computer-aided design (CAD) procedures is gaining prominence owing to its capacity to enhance design efficiency, forecast performance, and diminish time-tomarket. This literature overview examines the advanced machine learning techniques used at many phases of VLSI design. This review synthesizes data from current research articles, emphasizing the strengths, limits, and prospective avenues for machine learning implementations in VLSI CAD.

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4

Edwards, M. D. "Book Review: CAD for VLSI." International Journal of Electrical Engineering & Education 23, no. 2 (1986): 191–92. http://dx.doi.org/10.1177/002072098602300232.

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5

Walker, Ian. "A Smalltalk/V VLSI CAD application." Computer-Aided Engineering Journal 8, no. 2 (1991): 47. http://dx.doi.org/10.1049/cae.1991.0011.

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6

Fiebrich, Rolf-dieter. "A Supercomputer Workstation for VLSI CAD." IEEE Design & Test of Computers 3, no. 3 (1986): 31–37. http://dx.doi.org/10.1109/mdt.1986.294989.

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7

Kumar, Alok, Vijeta Kashyap, S. D. Sherlekar, et al. "Ideas: a tool for VLSI CAD." IEEE Design & Test of Computers 6, no. 5 (1989): 50–57. http://dx.doi.org/10.1109/54.43079.

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8

Batory, D. S., and Won Kim. "Modeling concepts for VLSI CAD objects." ACM Transactions on Database Systems 10, no. 3 (1985): 322–46. http://dx.doi.org/10.1145/3979.4018.

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9

Gupta, Indu, and R. K. Pandey. "CAD Tool for Modelling VLSI Designs." IETE Technical Review 20, no. 6 (2003): 541–45. http://dx.doi.org/10.1080/02564602.2003.11417113.

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10

Gupta, Rajiv, Wesley H. Cheng, Rajesh Gupta, Ido Hardonag, and Melvin A. Breuer. "An object-oriented VLSI CAD framework." Computer 22, no. 5 (1989): 28–37. http://dx.doi.org/10.1109/2.27954.

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11

York, T. A. "Book Review: VLSI CAD Tools and Applications." International Journal of Electrical Engineering & Education 25, no. 2 (1988): 184–85. http://dx.doi.org/10.1177/002072098802500225.

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12

Alpert, C. J., A. E. Caldwell, A. B. Kahng, and I. L. Markov. "Hypergraph partitioning with fixed vertices [VLSI CAD]." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19, no. 2 (2000): 267–72. http://dx.doi.org/10.1109/43.828555.

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13

Drechsler, R. "Evolutionary Algorithms for VLSI CAD [Book Review]." IEEE Transactions on Evolutionary Computation 3, no. 3 (1999): 251–53. http://dx.doi.org/10.1109/tevc.1999.788494.

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14

Young-Uk Yu. "VLSI design and CAD technology in Korea." IEEE Design & Test of Computers 6, no. 5 (1989): 29–39. http://dx.doi.org/10.1109/54.43077.

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15

Zolnikov, Vladimir, Konstantin Zolnikov, Nadezhda Ilina, and Kirill Grabovy. "Verification methods for complex-functional blocks in CAD for chips deep submicron design standards." E3S Web of Conferences 376 (2023): 01090. http://dx.doi.org/10.1051/e3sconf/202337601090.

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The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used.

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16

Szabó, K. S. B., J. M. Leask, and M. I. Elmasry. "CAD for VLSI: Symple: a symbolic layout tool for bipolar and MOS VLSI." IEE Proceedings I Solid State and Electron Devices 135, no. 2 (1988): 29. http://dx.doi.org/10.1049/ip-i-1.1988.0007.

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17

ZHAO, Qian, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, and Toshinori SUEYOSHI. "FPGA Design Framework Combined with Commercial VLSI CAD." IEICE Transactions on Information and Systems E96.D, no. 8 (2013): 1602–12. http://dx.doi.org/10.1587/transinf.e96.d.1602.

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18

Batory, D. S., and W. Kim. "Modeling concepts for VLSI CAD objects (abstract only)." ACM SIGMOD Record 14, no. 4 (1985): 446. http://dx.doi.org/10.1145/971699.320001.

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19

Darema, Frederica, and Gregory Pfister. "Multipurpose Parallelism for VLSI Cad on the RP3." IEEE Design & Test of Computers 4, no. 5 (1987): 19–27. http://dx.doi.org/10.1109/mdt.1987.295209.

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20

Wu, C. W., and P. R. Cappello. "Application-specific CAD of VLSI second-order sections." IEEE Transactions on Acoustics, Speech, and Signal Processing 36, no. 5 (1988): 813–25. http://dx.doi.org/10.1109/29.1590.

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21

Wagner, I. A., and I. Koren. "An interactive VLSI CAD tool for yield estimation." IEEE Transactions on Semiconductor Manufacturing 8, no. 2 (1995): 130–38. http://dx.doi.org/10.1109/66.382276.

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22

Du, H. C., and S. Ghanta. "A Framework for efficient IC/VLSI CAD databases." Information Sciences 48, no. 2 (1989): 195–215. http://dx.doi.org/10.1016/0020-0255(89)90018-2.

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23

Bolton, Martin. "Texts reflect growing interest in CAD for VLSI." Microprocessors and Microsystems 12, no. 2 (1988): 117. http://dx.doi.org/10.1016/0141-9331(88)90105-6.

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24

KIMURA, S. "Special Section on VLSI Design and CAD Algorithms." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 12 (2005): 3273. http://dx.doi.org/10.1093/ietfec/e88-a.12.3273.

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25

Onodera, H. "Special Section on VLSI Design and CAD Algorithms." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, no. 12 (2006): 3377. http://dx.doi.org/10.1093/ietfec/e89-a.12.3377.

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26

Matsunaga, Y. "Special Section on VLSI Design and CAD Algorithms." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E90-A, no. 12 (2007): 2649–50. http://dx.doi.org/10.1093/ietfec/e90-a.12.2649.

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27

Ishiura, N. "Special Section on VLSI Design and CAD Algorithms." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A, no. 12 (2008): 3413–14. http://dx.doi.org/10.1093/ietfec/e91-a.12.3413.

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28

Gerasimov, Yuriy, and Yaroslav Petrichkovich. "Radiation-Hardened VLSI SoC and RAM – Design Features for Bulk Silicon CMOS Technologies." Infocommunications and Radio Technologies 5, no. 4 (2022): 548–69. http://dx.doi.org/10.29039/2587-9936.2022.05.4.39.

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The effect of various types of radiation and heavy nuclear particles on VLSI fabricated using CMOS technologies for bulk silicon at a level of 250–90 nm is analyzed. Developed and certified on test crystals (TC) are constructive-topological and circuit solutions for elements of digital libraries, complex-functional RAM blocks and peripheral mixed-signal blocks for designing radiation-hardened VLSI of the “system-on-chip” (SoC) type and RAM of category RT (products with an increased level of radiation resistance). The methodology of radiation-hardened by design (RHBD) has been further developed

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29

Wang, Xiao-Dong, and Tom Chen. "Performance and Area Optimization of VLSI Systems Using Genetic Algorithms." VLSI Design 3, no. 1 (1995): 43–51. http://dx.doi.org/10.1155/1995/26912.

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A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believed within the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex. This conclusion is based on a simplified linear RC model to predict gate delays. In the proposed optimization algorithm, a nonlinear, non-RC based transistor delay model was used which resulted in a non-convex relationship between the delay and the silicon area of a VLSI chip. Genetic algorithms are better suited for discrete, non-convex, non-linear optimization problems than t

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30

Hall, J. E., D. E. Hocevar, Ping Yang, and M. J. McGraw. "SPIDER -- A CAD System for Modeling VLSI Metallization Patterns." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 6 (1987): 1023–31. http://dx.doi.org/10.1109/tcad.1987.1270343.

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31

Daniell, J., and S. W. Director. "An object oriented approach to CAD tool control (VLSI)." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 6 (1991): 698–713. http://dx.doi.org/10.1109/43.137499.

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32

Wright, G. T. "Threshold modelling of MOSFETs for CAD of CMOS-VLSI." Electronics Letters 21, no. 6 (1985): 223. http://dx.doi.org/10.1049/el:19850158.

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33

Russell, G. "Orthogonal and abstract view of CAD tools for VLSI." Computer-Aided Design 20, no. 2 (1988): 108–9. http://dx.doi.org/10.1016/0010-4485(88)90059-0.

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34

Glynn, L. "Wide and united coverage of CAD tools in VLSI." Computer-Aided Design 20, no. 1 (1988): 48. http://dx.doi.org/10.1016/0010-4485(88)90181-9.

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35

Nakamae, Koji, Katsuyoshi Miura, and Hiromu Fujioka. "VLSI testing with CAD-linked electron beam test system." Microelectronic Engineering 31, no. 1-4 (1996): 319–30. http://dx.doi.org/10.1016/0167-9317(95)00354-1.

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36

Nandy, S. K., and R. B. Panwar. "Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors." VLSI Design 1, no. 2 (1994): 127–54. http://dx.doi.org/10.1155/1994/96830.

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Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC) of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

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37

Плеханов, Л. П., А. Н. Денисов, Ю. Г. Дьяченко, Ю. А. Степченков, Д. И. Мамонов та Д. Ю. Степченков. "СИНТЕЗ САМОСИНХРОННЫХ СХЕМ В БАЗИСЕ БМК". NANOINDUSTRY Russia 96, № 3s (2020): 460–70. http://dx.doi.org/10.22184/1993-8578.2020.13.3s.460.470.

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Данный доклад посвящен разработке средств автоматизированного синтеза самосинхронных (CC) схем. Рассматриваются особенности реализации СС-схем. Предложен маршрут проектирования цифровых СС СБИС. Описана интеграция разрабатываемых средств в стандартную САПР синхронных СБИС («Ковчег»), обеспечивающая эффективное проектирование действительно СС-схем. This report is devoted to the development of software for automated synthesis of the self-timed (ST) circuits. Peculiarities of the ST circuit implementation have been discussed, and digital ST VLSI design flow has been offered. Besides, the report h

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38

Ramkumar, B., and P. Banerjee. "ProperCAD: A portable object-oriented parallel environment for VLSI CAD." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 7 (1994): 829–42. http://dx.doi.org/10.1109/43.293940.

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39

Steinberg, Louis, and Tom Mitchell. "The Redesign System: A Knowledge-Based Approach to VLSI CAD." IEEE Design & Test of Computers 2, no. 1 (1985): 45–54. http://dx.doi.org/10.1109/mdt.1985.294684.

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40

De Man, H. "Evolution of CAD tools towards third generation custom VLSI design." Revue de Physique Appliquée 22, no. 1 (1987): 31–45. http://dx.doi.org/10.1051/rphysap:0198700220103100.

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41

Wright, G. T. "Physical and CAD models for the implanted-channel VLSI MOSFET." IEEE Transactions on Electron Devices 34, no. 4 (1987): 823–33. http://dx.doi.org/10.1109/t-ed.1987.23002.

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42

Ramón, Chávez-Bracamontes, García-López Reyna Itzel, Gurrola-Navarro Marco Antonio, and Bandala-Sánchez Manuel. "VLSI Design with Alliance Free CAD Tools: an Implementation Example." Ingeniería, Investigación y Tecnología 16, no. 3 (2015): 441–52. http://dx.doi.org/10.1016/j.riit.2015.05.007.

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43

Vidyamurthy, G., and S. K. Nandy. "On the Reconfigurability of Hardware Accelerators for VLSI CAD tools." IETE Journal of Research 36, no. 3-4 (1990): 294–99. http://dx.doi.org/10.1080/03772063.1990.11436896.

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44

Antsiferova, Valentina, Ekaterina Grosheva, Anna Ivanova, and Ivanna Abrosimova. "Computer simulation of electrophysical effects in CAD chip design." E3S Web of Conferences 389 (2023): 07015. http://dx.doi.org/10.1051/e3sconf/202338907015.

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The article discusses the characteristics and functions of modern systems for computer-aided design of submicron microcircuits. The main developers of this class of systems are Cadence Design Systems, Mentor Graphics and Synopsys. The paper analyzes in sufficient detail the composition and functionality of software tools for the development of electronic equipment provided by these companies and allowing solving functionally different tasks within the framework of the VLSI design route. The electrophysical effects of the submicron level are analyzed, which include dynamic effects associated wi

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45

DENG, J., M. S. SHUR, T. A. FJELDLY, and S. BAIER. "CAD TOOLS AND OPTICAL DEVICE MODELS FOR MIXED ELECTRONIC/PHOTONIC VLSI." International Journal of High Speed Electronics and Systems 10, no. 01 (2000): 299–308. http://dx.doi.org/10.1142/s0129156400000325.

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This work addresses the issue of circuit simulation and photonic device modeling for mixed electronic/photonic VLSI. We present a basic approach to establishing the mixed electronic/photonic circuit simulator Photonic SPICE, where optical devices and interconnects are represented in terms of electrical equivalents. We also present results on the compact models of vertical-cavity surface emitting lasers (VCSELs) implemented in AIM-Spice. The VCSEL model is based on first-order rate equations that are expressed in terms of an electrical equivalent circuit. The model accounts for the VCSEL self-h

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46

Y.Priya, Mrs., and Kumar Mr. K. Santhosh. "Machine Learning Role in IC Design of VLSI." International Journal of Research 12, no. 5 (2025): 460–70. https://doi.org/10.5281/zenodo.15525593.

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AI has influenced the field of integrated circuits, this being its first application in AI. This technology replaces the traditional VLSI design methodology existing today. Automation of design developments have been implemented by replacing the time-consuming manual design’s generated by humans. This advancement would lead to massive revolution in the area of hardware computation and AI research domain. With the advent of modern chip, which are highly complex, it is a very tedious and slow process to design with humanly aids. Artificial Intelligence (AI) has been playing an increasingly

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47

Aparna, Gupta*1 Dr. Rita Jain2 &. Dr. R. P. Singh3. "PHYSICAL DESIGN, LAYOUT AND SIMULATION USING C5 PROCESS TECHNOLOGY OF 8 BIT ARITHMETIC AND LOGIC UNIT." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 5, no. 7 (2018): 510–21. https://doi.org/10.5281/zenodo.1325039.

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A critical component of the microprocessor, the core component of central processing unit, Arithmetic and Logical Unit  (ALU) comprises of the combinational logic that implements logic operations such as AND and OR, and arithmetic operations such as addition, subtraction, and multiplication. In this proposed work, a 8-bit ALU is designed, implemented and simulated using the Electric CAD and SPICE software. The proposed design is a 8-bit ALU that can perform operations like: A AND B, A OR B, A + B (addition), and A - B (subtraction) and all possible arithmetic and logical operations. Physi

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48

MEINEL, CHRISTOPH, and THORSTEN THEOBALD. "ORDERED BINARY DECISION DIAGRAMS AND THEIR SIGNIFICANCE IN COMPUTER-AIDED DESIGN OF VLSI CIRCUITS." Journal of Circuits, Systems and Computers 09, no. 03n04 (1999): 181–98. http://dx.doi.org/10.1142/s0218126699000165.

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Many problems in computer-aided design of highly integrated circuits (CAD for VLSI) can be transformed to the task of manipulating objects over finite domains. The efficiency of these operations depends substantially on the chosen data structures. In the last years, ordered binary decision diagrams (OBDDs) have proven to be a very efficient data structure in this context. Here, we give a survey on these developments and stress the deep interactions between basic research and practically relevant applied research with its immediate impact on the performance improvement of modern CAD design and

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49

Ahn, Sung H., V. Sundararajan, Charles Smith, et al. "CyberCut: An Internet-based CAD/CAM System." Journal of Computing and Information Science in Engineering 1, no. 1 (2001): 52–59. http://dx.doi.org/10.1115/1.1351811.

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“CyberCut™” is a testbed for an Internet-based CAD/CAM system. It was specifically designed to be a networked, automated system, with a seamless communication flow from a client-side designer to a server-side machining service. The creation of CyberCut required several new software modules. These include: a) a Web-based design tool in which Design-for-Manufacturing information and machining rules constrain the designer to manufacturable parts; b) a geometric representation called SIF-DSG, for unambiguous communication between the client-side designer and the server-side process planner; c) an

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50

Kurosawa, A., K. Yamada, A. Kishimoto, K. Mori, and N. Nishiguchi. "A Practical CAD System Application for Full Custom VLSI Microcomputer Chips." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 3 (1987): 364–73. http://dx.doi.org/10.1109/tcad.1987.1270281.

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