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1

1961-, Overhauser David, ed. Digital timing macromodeling for VLSI design verification. Kluwer Academic, 1995.

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2

Davie, Bruce S. Formal specification and verification in VLSI design. Edinburgh University Press, 1990.

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3

Kong, Jeong-Taek. Digital Timing Macromodeling for VLSI Design Verification. Springer US, 1995.

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4

Kong, Jeong-Taek, and David Overhauser. Digital Timing Macromodeling for VLSI Design Verification. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2321-5.

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5

Savaria, Yvon. Conception et vérification des circuits VLSI. Editions de l'Ecole polytechnique de Montréal, 1989.

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6

Hollstein, Thomas, Jaan Raik, Sergei Kostin, Anton Tšertov, Ian O'Connor, and Ricardo Reis, eds. VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-67104-8.

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7

Zheng, Jianqing. CMOS VLSI layout and verification of a SIMD computer: A thesis ... National Aeronautics and Space Administration, 1996.

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8

M, Claesen Luc J., and Interuniversity Micro-Electronics Center, eds. Formal VLSI correctness verification: Proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design. North-Holland, 1990.

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9

Munden, Richard. ASIC and FPGA verification: A guide to component modeling. Morgan Kaufmann, 2005.

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10

International Conference on VLSI Design (10th 1997 Hyderabad, India). Tenth International Conference on VLSI Design: January 4-7, 1997, Hyderabad, India. IEEE Computer Society Press, 1997.

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11

Zeljko, Zilic, ed. Verification by error modeling: Using testing techniques in hardware verification. Kluwer Academic Publishers, 2003.

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12

Bening, Lionel. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. 2nd ed. Kluwer Academic Publishers, 2001.

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13

Bening, Lionel. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. 2nd ed. Kluwer Academic Publishers, 2001.

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14

1956-, Foster Harry, ed. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. Kluwer Academic Publishers, 2000.

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15

Birtwistle, Graham, and P. A. Subrahmanyam, eds. VLSI Specification, Verification and Synthesis. Springer US, 1988. http://dx.doi.org/10.1007/978-1-4613-2007-4.

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16

Dominique, Borrione, Paul Wolfgang J. 1951-, and IFIP WG 10 5, eds. Correct hardware design and verification methods: 13th IFIP WG 10.5 advanced research working conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005 ; proceedings. Springer, 2005.

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17

VLSI design. CRC Press, 2001.

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18

Chandrasetty, Vikram Arkalgud. VLSI Design. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-1120-8.

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19

Joyce, Jeffrey. Hardware verification of VLSI regular structures. University of Cambridge, Computer Laboratory, 1987.

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20

Kamran, Eshraghian, ed. Basic VLSI design. 3rd ed. Prentice Hall, 1994.

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21

IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration (1987 Vancouver, Canada). VLSI 87: VLSI design of digital systems. North-Holland, 1988.

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22

Itoh, Kiyoo. VLSI Memory Chip Design. Springer Berlin Heidelberg, 2001.

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23

V, Kachan I., ed. Self-testing VLSI design. Elsevier, 1993.

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24

Grabinski, Hartmut. Interconnects in VLSI design. Kluwer Academic Publishers, 2000.

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25

Fabricius, Eugene D. Introduction to VLSI design. McGraw-Hill, 1990.

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26

Fabricius, Eugene D. Introduction to VLSI design. McGraw-Hill, 1990.

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27

Tsui, Frank F. LSI/VLSI testability design. McGraw-Hill, 1987.

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28

1959-, Dündar Günhan, and Öğrenci A. Selçuk, eds. Analog VLSI design automation. CRC Press, 2003.

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29

Itoh, Kiyoo. VLSI Memory Chip Design. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/978-3-662-04478-0.

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30

Rajaram, S., N. B. Balamurugan, D. Gracia Nirmala Rani, and Virendra Singh, eds. VLSI Design and Test. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-5950-7.

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31

Hörbst, Egon, Christian Müller-Schloer, and Heinz Schwärtzel. Design of VLSI Circuits. Springer Berlin Heidelberg, 1987. http://dx.doi.org/10.1007/978-3-642-95525-9.

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32

Grabinski, Hartmut, ed. Interconnects in VLSI Design. Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4349-7.

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33

Gaur, Manoj Singh, Mark Zwolinski, Vijay Laxmi, Dharmendra Boolchandani, Virendra Sing, and Adit D. Sing, eds. VLSI Design and Test. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-42024-5.

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34

Sengupta, Anirban, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, and Santosh Kumar Vishvakarma, eds. VLSI Design and Test. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9767-8.

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35

Kaushik, Brajesh Kumar, Sudeb Dasgupta, and Virendra Singh, eds. VLSI Design and Test. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7.

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36

Grabinski, Hartmut. Interconnects in VLSI Design. Springer US, 2000.

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37

Calimera, Andrea, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, and Ricardo Reis, eds. VLSI-SoC: Design Trends. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81641-4.

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38

Wolf, Wayne Hendrix. Modern VLSI design: IP-based design. 4th ed. Prentice Hall, 2008.

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39

Modern VLSI design: System-onchip design. 3rd ed. Prentice Hall PTR, 2002.

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40

Moser, Louise. Design verification of SIFT. Langley Research Center, 1987.

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41

Carter, Hamilton B., and Shankar Hemmady. Metric- Driven Design Verification. Springer US, 2007. http://dx.doi.org/10.1007/978-0-387-38152-7.

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42

Wolf, Wayne Hendrix. Modern VLSI design: System-on-chip design. 3rd ed. Prentice Hall PTR, 2002.

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43

Computer aids for VLSI design. Addison-Wesley Pub. Co., 1987.

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44

Seepold, Ralf. Reuse Techniques for VLSI Design. Springer US, 1999.

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45

M, Birtwistle G., and Subrahmanyam P. A, eds. VLSI specification, verification, and synthesis. Kluwer Academic Publishers, 1988.

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46

Formal verification : an essential toolkit for modern VLSI design. Elsevier/MK, 2015.

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47

2, Ifip Wg 10, and Wg 10.5 International Workshop on Applied Formal Methods. Formal Vlsi Correctness Verification: Vlsi Design Methods II : Proceedings of the Ifip Wg 10.2/Wg 10.5 International Workshop on Applied Formal Meth (Vlsi Design Methods, 2). North-Holland, 1990.

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48

CMOS VLSI layout and verification of a SIMD computer: A thesis ... National Aeronautics and Space Administration, 1996.

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49

(Editor), Graham Birtwistle, and P. A. Subrahmanyam (Editor), eds. VLSI Specification, Verification and Synthesis (The International Series in Engineering and Computer Science). Springer, 1987.

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50

Tenth International Conference on VLSI Design: January 4-7, 1997, Hyderabad, India. IEEE Computer Society Press, 1997.

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