Relevant bibliographies by topics / VLSI interconnect

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'VLSI interconnect'

Author: Grafiati
Published: 4 June 2021
Last updated: 10 February 2022

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Journal articles on the topic "VLSI interconnect"

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CUMMING, DAVID R. S. "Improved VLSI interconnect." International Journal of Electronics 86, no. 8 (August 1999): 957–65. http://dx.doi.org/10.1080/002072199132950.

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Karthikeyan, A., and P. S. Mallick. "Optimization Techniques for CNT Based VLSI Interconnects — A Review." Journal of Circuits, Systems and Computers 26, no. 03 (November 21, 2016): 1730002. http://dx.doi.org/10.1142/s0218126617300021.

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Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22[Formula: see text]nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.
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Poltz, J. "MODELING OF VLSI INTERCONNECT." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 13, no. 1 (January 1994): 191–94. http://dx.doi.org/10.1108/eb051872.

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Karthikeyan, A., and P. S. Mallick. "Buffer for High Performance in CNT Based VLSI Interconnects." Advanced Science Letters 24, no. 8 (August 1, 2018): 5975–81. http://dx.doi.org/10.1166/asl.2018.12230.

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Integrated circuits (IC’s) are sized for higher performance and packing density. Interconnects are major components to carry signals between transistors. Interconnect delay increases due to increase in length of interconnect. Optimization of interconnects is more essential to improve the performance of integrated circuits. Repeater insertion is an important technique used in optimizing the performance of interconnects in integrated circuits. Repeaters have to be designed to satisfy the performance constraints. In this paper we have designed a new repeater using transistors and analyzed the performance at various bias levels. The Repeater design was implemented at various technology nodes using PTM models and Bulk CMOS. Delay and power dissipation are analyzed for various voltage levels and load levels using Spice simulations. The results show that the proposed repeater has lesser delay compared to the conventional repeater with an increase of power dissipation and they are more suitable for Critical path in VLSI interconnects. They can be applicable for CNT based VLSI interconnects.
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Kumar Rai, Mayank, Rajesh Khanna, and Sankar Sarkar. "Control of tube parameters on SWCNT bundle interconnect delay and power dissipation." Microelectronics International 31, no. 1 (December 20, 2013): 24–31. http://dx.doi.org/10.1108/mi-03-2013-0016.

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Purpose – This paper aims to propose to study the control of tube parameters in terms of diameter, separation between adjacent tubes and length, on delay and power dissipation in single-walled carbon nanotube (SWCNT) bundle interconnect for VLSI circuits. Design/methodology/approach – The paper considers a distributed-RLC model of interconnect. A CMOS-inverter driving a distributed-RLC model of interconnect with load of 1 pF. A 0.1 GHz pulse of 2 ns rise time provides input to the CMOS-inverter. For SPICE simulation, predictive technology model (PTM) is used for the CMOS-driver. The performance of this setup is studied by SPICE simulation in 22 nm technology node. The results are compared with those of currently used copper interconnect. Findings – SPICE simulation results reveal that delay increases with increase in separation between tubes and diameter whereas the reverse is true for power dissipation. The authors also find that SWCNT bundle interconnects are of lower delay than copper interconnect at various lengths and higher power dissipation due to dominance of larger capacitance of tube bundle. Originality/value – The investigations show that tube parameters can control delay and this can also be utilized to decrease power dissipation in SWCNT bundle interconnects for VLSI applications.
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DEHON, ANDRÉ, FRED DRENCKHAHN, THOMAS KNIGHT, and HENRY MINSKY. "THREE-DIMENSIONAL PACKAGING FOR HIGH-PERFORMANCE INTERCONNECT IN LARGE-SCALE VLSI SYSTEMS." International Journal of High Speed Electronics and Systems 06, no. 04 (December 1995): 613–30. http://dx.doi.org/10.1142/s0129156495000225.

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The transit time through the interconnect between VLSI components can be a significant fraction of the latency in a large VLSI system. In this paper we describe a scheme for dense, three-dimensional packaging of VLSI components which reduces chip-to-chip transit latencies by reducing interconnect distances. Our packaging scheme sandwiches layers of conventional printed-circuit boards between layers of packaged components to efficiently utilize all three spatial dimensions for interconnect. We introduce the key components of our stack packaging scheme and show how they combine to provide efficient housing for a large range of large-scale VLSI systems.
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Sathyanarayanan, D., and M. Mohamed. "Implementation of VLSI interconnect design." International Journal of Advanced Technology and Engineering Exploration 5, no. 42 (May 21, 2018): 96–98. http://dx.doi.org/10.19101/ijatee.2018.542006.

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Sechler, R. F. "Interconnect design with VLSI CMOS." IBM Journal of Research and Development 39, no. 1.2 (January 1995): 23–31. http://dx.doi.org/10.1147/rd.391.0023.

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Shacham-Diamand, Yosi. "The Reliability of Aluminum/Tungsten Technology for VLSI Applications." MRS Bulletin 20, no. 11 (November 1995): 78–82. http://dx.doi.org/10.1557/s0883769400045644.

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Interconnects technology and back-end processing moved to the center stage of very large-scale integration (VLSI) technology in the mid-1980s. At that time, the critical dimensions dropped below 1 μm while the chip size and complexity increased to a level where interconnects were recognized to be a limiting factor. As dimensions decreased, the step coverage of sputtered aluminum inside contacts and via-contact holes decreased and alternative technologies were studied. The increasing cost of ownership (COO) of single-wafer Al sputtering processes also supported the search for alternative technologies, such as tungsten chemical vapor deposition (CVD) for via contacts and plugs (Figure 1). Only recently have all the W CVD process steps been optimized to lower cost without loss of reliability and/or performance. The development of cluster tool technology and multiwafer process modules also allowed reliable and cost-effective utilization of the W/Al technology.Tungsten technology for VLSI circuits became complementary to that of aluminum. Tungsten thin-film resistivity ρw = 7–8 μΩ cm is much higher than that of aluminum ρAl = 3–4 μΩ cm, introducing large W interconnect resistance-capacitance (RC) delays compared to Al. Therefore, tungsten is not favorable for high-speed global-interconnect schemes. However, tungsten is suitable for local interconnects where the impedance of the driving transistors is dominant and the RC interconnect delay is less significant. Tungsten is also suitable for contact filling, in which the via resistance is negligible. For these applications, tungsten became a dominant technology and was integrated with the aluminumalloy-based technology used for global interconnects.
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Xu, Yao, Ashok Srivastava, and Ashwani K. Sharma. "Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance." VLSI Design 2010 (February 17, 2010): 1–8. http://dx.doi.org/10.1155/2010/864165.

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Current transport and dynamic models of carbon nanotube field-effect transistors are presented. A model of single-walled carbon nanotube as interconnect is also presented and extended in modeling of single-walled carbon nanotube bundles. These models are applied in studying the performances of circuits such as the complementary carbon nanotube inverter pair and carbon nanotube as interconnect. Cadence/Spectre simulations show that carbon nanotube field-effect transistor circuits can operate at upper GHz frequencies. Carbon nanotube interconnects give smaller delay than copper interconnects used in nanometer CMOS VLSI circuits.
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Dissertations / Theses on the topic "VLSI interconnect"

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Kao, De-Yu. "VLSI interconnect synthesis /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 1998. http://wwwlib.umi.com/cr/ucsd/fullcit?p9824659.

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Liu, Bao. "VLSI interconnect synthesis and prediction /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3077807.

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Li, Zhuo. "Fast interconnect optimization." Texas A&M University, 2005. http://hdl.handle.net/1969.1/3250.

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As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high performance designs. For the gigahertz microprocessor and multi-million gate ASIC designs it is crucial to have fast algorithms in the design automation tools for many classical problems in the field to shorten time to market of the VLSI chip. This research presents algorithmic techniques and constructive models for two such problems: (1) Fast buffer insertion for delay optimization, (2) Wire sizing for delay optimization and variation minimization on non-tree networks. For the buffer insertion problem, this dissertation proposes several innovative speedup techniques for different problem formulations and the realistic requirement. For the basic buffer insertion problem, an O(n log2 n) optimal algorithm that runs much faster than the previous classical van Ginneken’s O(n2) algorithm is proposed, where n is the number of buffer positions. For modern design libraries that contain hundreds of buffers, this research also proposes an optimal algorithm in O(bn2) time for b buffer types, a significant improvement over the previous O(b2n2) algorithm by Lillis, Cheng and Lin. For nets with small numbers of sinks and large numbers of buffer positions, a simple O(mn) optimal algorithm is proposed, where m is the number of sinks. For the buffer insertion with minimum cost problem, the problem is first proved to be NP-complete. Then several optimal and approximation techniques are proposed to further speed up the buffer insertion algorithm with resource control for big industrial designs. For the wire sizing problem, we propose a systematic method to size the wires of general non-tree RC networks. The new method can be used for delay optimization and variation reduction.
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Hamilton, Kevin Clark. "Optimization of energy and throughput for pipelined VLSI interconnect." Diss., [La Jolla] : University of California, San Diego, 2010. http://wwwlib.umi.com/cr/ucsd/fullcit?p1473080.

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Thesis (M.S.)--University of California, San Diego, 2010.
Title from first page of PDF file (viewed February 17, 2010). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 22-23).
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Chiprout, Eli Carleton University Dissertation Engineering Electronics. "Moment-maching analysis of high-speed VLSI interconnect models." Ottawa, 1994.

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Yang, Xiao-Dong. "Reduced order modeling and analysis for VLSI RLC interconnect /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2000. http://wwwlib.umi.com/cr/ucsd/fullcit?p9970674.

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Bailey, James L. "A VLSI interconnect strategy for biologically inspired artificial neural networks /." Full text open access at:, 1993. http://content.ohsu.edu/u?/etd,265.

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Wei, Yuji Carleton University Dissertation Engineering Electronics. "Multilevel optimization of high speed VLSI interconnect networks by decomposition." Ottawa, 1993.

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Liu, I.-min. "Algorithms for interconnect planning and optimization in deep-submicron VLSI design /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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Chiprout, Eli Carleton University Dissertation Engineering Electrical. "Generalized moment-matching methods for interconnect analysis of high-speed VLSI systems." Ottawa, 1992.

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Books on the topic "VLSI interconnect"

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Moiseev, Konstantin, Avinoam Kolodny, and Shmuel Wimer. Multi-Net Optimization of VLSI Interconnect. New York, NY: Springer New York, 2015. http://dx.doi.org/10.1007/978-1-4614-0821-5.

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Celik, Mustafa. IC interconnect analysis. Boston: Kluwer Academic Publishers, 2002.

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Grabinski, Hartmut. Interconnects in VLSI design. Boston: Kluwer Academic Publishers, 2000.

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Grabinski, Hartmut, ed. Interconnects in VLSI Design. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4349-7.

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Grabinski, Hartmut. Interconnects in VLSI Design. Boston, MA: Springer US, 2000.

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Kaushik, Brajesh Kumar, and Manoj Kumar Majumder. Carbon Nanotube Based VLSI Interconnects. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2047-3.

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Nakhla, M. S., and Q. J. Zhang, eds. Modeling and Simulation of High Speed VLSI Interconnects. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2718-3.

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Advanced interconnects for ULSI technology. Hoboken, NJ: Wiley, 2012.

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Nakhla, M. S. Modeling and Simulation of High Speed VLSI Interconnects: A Special Issue of Analog Integrated Circuits and Signal Processing An International Journal Vol. 5, No. 1 (1994). Boston, MA: Springer US, 1994.

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Lemieux, Guy. Design of interconnection networks for programmable logic. Boston, MA: Kluwer Academic, 2003.

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Book chapters on the topic "VLSI interconnect"

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Tan, Cher-Ming, Udit Narula, and Vivek Sangwan. "Copper–Graphene Interconnect." In Graphene and VLSI Interconnects, 91–111. New York: Jenny Stanford Publishing, 2021. http://dx.doi.org/10.1201/9781003224884-5.

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Wang, J. M., and E. S. Kuh. "Recent Development in Interconnect Modeling." In Interconnects in VLSI Design, 1–23. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4349-7_1.

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Kenmei, L. B., F. Huret, E. Paleczny, P. Kennis, G. Servel, and D. Deschacht. "Input Shape Influence over Interconnect Performances." In Interconnects in VLSI Design, 71–77. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4349-7_6.

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Moiseev, Konstantin, Avinoam Kolodny, and Shmuel Wimer. "Frameworks for Interconnect Optimization." In Multi-Net Optimization of VLSI Interconnect, 35–42. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-0821-5_4.

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Palusinski, Olgierd A., Andreas C. Cangellaris, John L. Prince, Jen C. Liao, and Loizos Vakanas. "Electrical Performance of VLSI Interconnect Systems." In Electronics Packaging Forum, 67–116. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-010-9286-9_4.

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Müller, Georg, and Karl Reiß. "Considering Magnetic Interference in Board-Level Interconnect Design." In Interconnects in VLSI Design, 61–69. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4349-7_5.

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Caignet, F., S. Delmas-Ben-dhia, and E. Sicard. "Measurement of Signal Integrity within Deep Sub-Micron Interconnect." In Interconnects in VLSI Design, 49–59. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4349-7_4.

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Moiseev, Konstantin, Avinoam Kolodny, and Shmuel Wimer. "Future Directions in Interconnect Optimization." In Multi-Net Optimization of VLSI Interconnect, 221–22. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-0821-5_10.

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Moiseev, Konstantin, Avinoam Kolodny, and Shmuel Wimer. "Interconnect Optimization by Net Ordering." In Multi-Net Optimization of VLSI Interconnect, 167–94. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-0821-5_8.

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Silveira, Luís Miguel, and Mattan Kamon. "Coupled Circuit-Interconnect Modeling and Simulation." In VLSI: Integrated Systems on Silicon, 427–38. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-0-387-35311-1_35.

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Conference papers on the topic "VLSI interconnect"

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Cartuyvels, Rudi, Zsolt Tokei, Eric Beyne, and Chris Van Hoof. "Shaping interconnect technology for an interconnected society." In 2010 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA 2010). IEEE, 2010. http://dx.doi.org/10.1109/vtsa.2010.5488910.

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Ghosh, P., R. Mangaser, C. Mark, and K. Rose. "Interconnect-dominated VLSI design." In Proceedings 20th Anniversary Conference on Advanced Research in VLSI. IEEE, 1999. http://dx.doi.org/10.1109/arvlsi.1999.756042.

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Haney, Michael W., Muzammil Iqbal, and Michael J. McFadden. "Arbitrarily Configurable Optical Interconnect Fabric for Intrachip Global Communication." In ASME 2003 International Electronic Packaging Technical Conference and Exhibition. ASMEDC, 2003. http://dx.doi.org/10.1115/ipack2003-35166.

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Optical interconnections at the chip level may provide solutions to the limitations of metal interconnect technology, which is not keeping pace with the progress of device integration density. In this paper we undertake a quantitative analysis of on-chip metal interconnect performance as CMOS device technology scales into the nanometer regime. The results of this analysis motivates the use of optical interconnects as a replacement for global wires on the chip. We propose a new architecture, in which a 3-D optoelectronic Application Specific Interconnection Fabric (ASIF) is coupled to a conventional Silicon integrated circuit to alleviate the performance-limiting aspects of long metal interconnects. The overall goal of the ASIF concept is to overcome the limitations of conventional metal interconnects in a manner that can be seamlessly integrated according to current VLSI design constraints and practices.
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Yamashita and Odanaka. "Interconnect Scaling Scenario Using A Chip Level Interconnect Model." In Symposium on VLSI Technology. IEEE, 1997. http://dx.doi.org/10.1109/vlsit.1997.623691.

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Carin, L., Qiang Xu, K. J. Webb, and J. A. McClintock. "Analysis of VLSI Interconnect Structures." In MTT-S International Microwave Symposium Digest. MTT005, 1987. http://dx.doi.org/10.1109/mwsym.1987.1132488.

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Hayashi, Kishii, Keyser, and Farrell. "R-2 The Interconnect Crisis." In Symposium on VLSI Technology. IEEE, 1997. http://dx.doi.org/10.1109/vlsit.1997.623720.

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Pedram, Massoud. "Interconnect length estimation in VLSI designs." In the 2014. New York, New York, USA: ACM Press, 2014. http://dx.doi.org/10.1145/2560519.2568053.

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Singh, Hitlendra Pratap, and G. S. Virdi. "RLC modeled interconnect delay analysis for high-speed on-chip VLSI interconnects." In 2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS). IEEE, 2017. http://dx.doi.org/10.1109/icecds.2017.8389842.

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Serpanos, Dimitrios N., and Wayne Wolf. "VLSI models of network-on-chip interconnect." In 2007 IFIP International Conference on Very Large Scale Integration. IEEE, 2007. http://dx.doi.org/10.1109/vlsisoc.2007.4402475.

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Tang, Kevin T., and Eby G. Friedman. "Interconnect coupling noise in CMOS VLSI circuits." In the 1999 international symposium. New York, New York, USA: ACM Press, 1999. http://dx.doi.org/10.1145/299996.300020.

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Reports on the topic "VLSI interconnect"

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Chiang, Patrick. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing. Office of Scientific and Technical Information (OSTI), January 2014. http://dx.doi.org/10.2172/1311619.

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Uzelac, Lawrence. A Multiple Coupled Microstrip Transmission Line Model for High-Speed VLSI Interconnect Simulation. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6410.

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