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Dissertations / Theses on the topic 'VLSI interconnect'

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Published: 4 June 2021
Last updated: 10 February 2022

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1

Kao, De-Yu. "VLSI interconnect synthesis /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 1998. http://wwwlib.umi.com/cr/ucsd/fullcit?p9824659.

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2

Liu, Bao. "VLSI interconnect synthesis and prediction /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3077807.

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3

Li, Zhuo. "Fast interconnect optimization." Texas A&M University, 2005. http://hdl.handle.net/1969.1/3250.

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As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high performance designs. For the gigahertz microprocessor and multi-million gate ASIC designs it is crucial to have fast algorithms in the design automation tools for many classical problems in the field to shorten time to market of the VLSI chip. This research presents algorithmic techniques and constructive models for two such problems: (1) Fast buffer insertion for delay optimization, (2) Wire sizing for delay optimization and variation minimization on non-tree networks. For the buffer insertion problem, this dissertation proposes several innovative speedup techniques for different problem formulations and the realistic requirement. For the basic buffer insertion problem, an O(n log2 n) optimal algorithm that runs much faster than the previous classical van Ginneken’s O(n2) algorithm is proposed, where n is the number of buffer positions. For modern design libraries that contain hundreds of buffers, this research also proposes an optimal algorithm in O(bn2) time for b buffer types, a significant improvement over the previous O(b2n2) algorithm by Lillis, Cheng and Lin. For nets with small numbers of sinks and large numbers of buffer positions, a simple O(mn) optimal algorithm is proposed, where m is the number of sinks. For the buffer insertion with minimum cost problem, the problem is first proved to be NP-complete. Then several optimal and approximation techniques are proposed to further speed up the buffer insertion algorithm with resource control for big industrial designs. For the wire sizing problem, we propose a systematic method to size the wires of general non-tree RC networks. The new method can be used for delay optimization and variation reduction.
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4

Hamilton, Kevin Clark. "Optimization of energy and throughput for pipelined VLSI interconnect." Diss., [La Jolla] : University of California, San Diego, 2010. http://wwwlib.umi.com/cr/ucsd/fullcit?p1473080.

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Thesis (M.S.)--University of California, San Diego, 2010.
Title from first page of PDF file (viewed February 17, 2010). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 22-23).
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5

Chiprout, Eli Carleton University Dissertation Engineering Electronics. "Moment-maching analysis of high-speed VLSI interconnect models." Ottawa, 1994.

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6

Yang, Xiao-Dong. "Reduced order modeling and analysis for VLSI RLC interconnect /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2000. http://wwwlib.umi.com/cr/ucsd/fullcit?p9970674.

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7

Bailey, James L. "A VLSI interconnect strategy for biologically inspired artificial neural networks /." Full text open access at:, 1993. http://content.ohsu.edu/u?/etd,265.

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8

Wei, Yuji Carleton University Dissertation Engineering Electronics. "Multilevel optimization of high speed VLSI interconnect networks by decomposition." Ottawa, 1993.

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9

Liu, I.-min. "Algorithms for interconnect planning and optimization in deep-submicron VLSI design /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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10

Chiprout, Eli Carleton University Dissertation Engineering Electrical. "Generalized moment-matching methods for interconnect analysis of high-speed VLSI systems." Ottawa, 1992.

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11

Uzelac, Lawrence Stevan. "A Multiple Coupled Microstrip Transmission Line Model for High-Speed VLSI Interconnect Simulation." PDXScholar, 1991. https://pdxscholar.library.pdx.edu/open_access_etds/4526.

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A model is presented which incorporates the advantages of a mixed mode simulation to characterize transmission line behavior in multiple coupled Transmission line systems. The model is intended for use by digital circuit designers who wish to be able to obtain accurate transmission line behavior for complex digital systems for which continuous time simulation tools such as SPICE would time prohibitive. The model uses a transverse electromagnetic wave approximation to obtain solutions to the basic transmission line equations. A modal analysis technique is used to solve for the attenuation and propagation constants for the transmission lines. Modal analysis done in the frequency domain after a Fast Fourier Transform of the time-domain input signals. Boundary conditions are obtained from the Thevinized transmission line input equivalent circuit and the transmission line output load impedance. The model uses a unique solution queue system that allows n-line coupled transmission lines to be solved without resorting to large order matrix methods or the need to diagonals larger matrices using linear transformations. This solution queue system is based on the method of solution superposition. As a result, the CPU time required for the model is primarily a function of the number of transitions and not the number of lines modeled. Incorporation of the model into event driven circuit simulators such as Network C is discussed. It will be shown that the solution queue methods used in this model make it ideally suited for incorporation into a event-driven simulation network. The model presented in this thesis can be scaled to incorporate direct electromagnetic coupling between first, second, or third lines adjacent to the line transitioning. It is shown that modeling strictly adjacent line coupling is adequate for typical digital technologies. It is shown that the model accurately reproduces the transmission line behavior of systems modeled by previous authors. Example transitions on a 8-line system are reviewed. Finally, future model improvements are discussed.
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12

Chou, Mike Chuan 1969. "Fast algorithms for ill-conditioned dense matrix problems in VLSI interconnect and substrate modeling." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46180.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
Includes bibliographical references (leaves 131-135).
by Mike Chuan Chou.
Ph.D.
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13

Knechtel, Johann. "Interconnect Planning for Physical Design of 3D Integrated Circuits." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-143635.

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Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation
Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich
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14

Huang, Nick Kuan-Hsiang. "Implementation of algorithms to determine the capacitance sensitivity of interconnect parasitics in the Magic VLSI layout tool." Thesis, University of British Columbia, 2009. http://hdl.handle.net/2429/12924.

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VLSI interconnect capacitance is becoming more significant and also increasingly subject to process variation in the deep submicron regime. A new set of capacitance models is implemented in the Magic VLSI layout tool to improve the capacitance accuracy based on 2.5D capacitance models. This involves a new technology file, equations, and search algorithms. In addition, a simple technique to extract from layout the sensitivity of interconnect parasitic capacitance to linewidth process variation is proposed based on the new capacitance models and implemented in Magic. The derivative of each extracted capacitance with respect to linewidth variation in every level is obtained. Coincident edges in layout result in distinct “shrinking” and “bloating” derivatives. The derivatives therefore form a gradient that may be multiplied by a vector of the variations on each level to give the total expected deviation from nominal capacitance. The gradient allows the process sensitivity of each capacitance to be determined by simply inspecting the netlist. In the end, the impact of process variation is simulated in a crosstalk application to emphasize the necessity of process variation awareness.
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15

Anbalagan, Pranav. "Limitations and opportunities for wire length prediction in gigascale integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22670.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.
Committee Chair: Dr. Jeff Davis; Committee Member: Dr. James D. Meindl; Committee Member: Dr. Paul Kohl; Committee Member: Dr. Scott Wills; Committee Member: Dr. Sung Kyu Lim.
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16

Pamunuwa, Dinesh. "Modelling and Analysis of Interconnects for Deep Submicron Systems-on-Chip." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3659.

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The last few decades have been a very exciting period in thedevelopment of micro-electronics and brought us to the brink ofimplementing entire systems on a single chip, on a hithertounimagined scale. However an unforeseen challenge has croppedup in the form of managing wires, which have become the mainbottleneck in performance, masking the blinding speed of activedevices. A major problem is that increasingly complicatedeffects need to be modelled, but the computational complexityof any proposed model needs to be low enough to allow manyiterations in a design cycle.

This thesis addresses the issue of closed form modelling ofthe response of coupled interconnect systems. Following astrict mathematical approach, second order models for thetransfer functions of coupled RC trees based on the first andsecond moments of the impulse response are developed. The2-pole-1-zero transfer function that is the best possible fromthe available information is obtained for the signal path fromeach driver to the output in multiple aggressor systems. Thisallows the complete response to be estimated accurately bysumming up the individual waveforms. The model represents theminimum complexity for a 2-pole-1-zero estimate, for this classof circuits.

Also proposed are new techniques for the optimisation ofwires in on-chip buses. Rather than minimising the delay overeach individual wire, the configuration that maximises thetotal bandwidth over a number of parallel wires isinvestigated. It is shown from simulations that there is aunique optimal solution which does not necessarily translate tothe maximum possible number of wires, and in fact deviatesconsiderably from it when the resources available for repeatersare limited. Analytic guidelines dependent only on processparameters are derived for optimal sizing of wires andrepeaters.

Finally regular tiled architectures with a commoncommunication backplane are being proposed as being the mostefficient way to implement systems-on-chip in the deepsubmicron regime. This thesis also considers the feasibility ofimplementing a regular packet-switched network-on-chip in atypical future deep submicron technology. All major physicalissues and challenges are discussed for two differentarchitectures and important limitations are identified.

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17

Liu, Ruolong Carleton University Dissertation Engineering Electrical. "Optimization of high-speed VLSI interconnects." Ottawa, 1993.

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18

Sarvari, Reza. "Impact of size effects and anomalous skin effect on metallic wires as GSI interconnects." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/31636.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Meindl, James D.; Committee Member: Davis, Jeffrey A.; Committee Member: Gaylord, Thomas K.; Committee Member: Hess, Dennis W.; Committee Member: Peterson, Andrew F. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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19

Singhal, Rohit. "Data integrity for on-chip interconnects." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5929.

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With shrinking feature size and growing integration density in the Deep Sub- Micron (DSM) technologies, the global buses are fast becoming the "weakest-links" in VLSI design. They have large delays and are error-prone. Especially, in system-onchip (SoC) designs, where parallel interconnects run over large distances, they pose difficult research and design problems. This work presents an approach for evaluating the data carrying capacity of such wires. The method treats the delay and reliability in interconnects from an information theoretic perspective. The results point to an optimal frequency of operation for a given bus dimension for maximum data transfer rate. Moreover, this optimal frequency is higher than that achieved by present day designs which accommodate the worst case delays. This work also proposes several novel ways to approach this optimal data transfer rate in practical designs.From the analysis of signal propagation delay in long wires, it is seen that the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication theory, these "good" signals arriving early can be used to predict/correct the "few" signals that arrive late. In addition to this correction based on prediction, the approaches use coding techniques to eliminate high delay cases to generate a higher transmission rate. The work also extends communication theoretic approaches to other areas of VLSI design. Parity groups are generated based on low output delay correlation to add redundancy in combinatorial circuits. This redundancy is used to increase the frequency of operation and/or reduce the energy consumption while improving the overall reliability of the circuit.
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20

Yang, Tsung-Yi. "Free-space optoelectronic interconnects for VLSI microelectronic systems." Thesis, Heriot-Watt University, 2000. http://hdl.handle.net/10399/553.

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21

Lum, Stephen Carleton University Dissertation Engineering Electrical. "Sensitivity analysis and optimization of high-speed VLSI interconnects." Ottawa, 1991.

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22

Shenoy, Krishna V. (Krishna Vaughn). "Monolithic optoelectronic VLSI circuit design and fabrication for optical interconnects." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/10349.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
Includes bibliographical references (p. 381-398).
by Krishna V. Shenoy.
Ph.D.
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23

Li, Lena Le Carleton University Dissertation Engineering Electronics. "A moment method for statistical analysis of High speed VLSI interconnects." Ottawa, 1995.

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24

Agnihotri, Ameya Ramesh. "Combinatorial optimization techniques for VLSI placement." Diss., Online access via UMI:, 2007.

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25

Laprise, Emmanuelle. "Design and implementation of optoelectronic-VLSI chips for short reach optical interconnects." Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=32963.

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The challenges encountered while designing the silicon ASICs for three short reach optical interconnects will be described. Many of the difficulties encountered at the chip level will be analyzed. These will include how to route the large lines required to power the transceivers, how to reduce the large number of individually controlled analog signals, and how to group the transceivers when doing the top level floorplan. Silicon chip features can also be useful to meet the system-level challenges. A method that facilitates on-chip random data generation and verification will be proposed. A method that can facilitate the synchronization of two optical sub-systems, using dual-port fifos, will be analyzed. On-chip test features that facilitate pre-hybridization, post-hybridization and system testing will be analyzed. Optical scan chains are one of the test features that will be presented. Their use in performing in-system and built-in-self-tests will be contemplated.
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26

Hsu, Pochang. "A computer-aided design framework for modeling and simulation of VLSI interconnects." Diss., The University of Arizona, 1993. http://hdl.handle.net/10150/186363.

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The rising complexity of interconnect and packaging structures in VLSI systems has increased the necessity of applying modeling and simulation techniques for analysis and design. To effectively manage design data and CAD tools for modeling and simulations of electronic packaging, a framework which provides different levels of services is essential. This paper discusses a computer-aided design framework for the aforementioned purposes. A CAD framework with a five layered architecture is developed to support the analysis and design for VLSI packaging and interconnects. The first layer of the framework emphasizes the fundamental integration of CAD tools and simulation management. In the second layer of the architecture, design data representation and management are stressed. Two design databases termed the Chip Model Library and the Packaging Model Library are developed and coupled in this layer. We applied an object-oriented approach to implement libraries and encapsulate CAD tools. System level (board level) modeling and simulation are presented in the third layer of the framework. CMOS based multichip modules (MCMs) are used for our discussion. The fourth layer is for the automation of design process by coordinating different CAD tools. The highest layer in the proposed CAD framework is the level for design methodology management. A rule and frame based system is illustrated for simulation model generation of electronic packages.
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27

Xie, Dong Hui Carleton University Dissertation Engineering Electrical. "Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations." Ottawa, 1992.

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28

Liu, Yansong. "Passivity checking and enforcement in VLSI model reduction exercise." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290690.

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29

Liu, Lup Shun Nelson Carleton University Dissertation Engineering Electronics. "Sensitivity analysis and optimization of high-speed VLSI interconnects using asymptotic waveform evaluation." Ottawa, 1993.

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30

Sanaie, Ramin Carleton University Dissertation Engineering Electronics. "Fast method for frequency and time domain simulation of high-speed VLSI interconnects." Ottawa, 1994.

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31

Liu, Yansong, and 劉岩松. "Passivity checking and enforcement in VLSI model reduction exercise." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B41290690.

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32

Rolston, David Robert Cameron. "The design, layout, and characterization of VLSI optoelectronic chips for free-space optical interconnects /." Thesis, McGill University, 2000. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=36832.

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The design and testing of very-large-scale-integrated optoelectronic (VLSI-OE) microchips will be described in the context of a free-space optical backplane system. The optical backplane has the potential for providing an enormous amount of bandwidth for telecommunication switching systems and massively parallel computing machines. A free-space optical backplane uses optical design techniques to relay beams of light from the surface of one microchip to the surface of another. By using light to interconnect microchips, the problems associated with high-speed electronic interconnects are avoided. By exploiting the 2-dimensional surface area of the microchips, large numbers of parallel optical interconnections are possible using minute optoelectronic devices patterned on the surface of the chips. By using appropriate optical designs and microchip layouts, massively parallel high-bandwidth interconnects can be implemented within a volume comparable with standard electronic interconnects such as buses and backplanes.
This thesis will begin by describing a specific VLSI-OE chip architecture as well as two free-space optical designs used to interconnect VLSI-OE chips. Details of the design and layout of four separate VLSI-OE chips will then be given and the results of optical and electrical testing of these chips will follow. Finally, the topic of global synchronization will then be considered. Synchronization among many VLSI-OE chips in a multiple-node system requires special attention. A novel approach of providing synchronized clock signals to a multitude of distance points will be discussed.
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33

Cho, Jaeshin. "Effect of microstructure of aluminum alloys on the electromigration-limited reliability of VLSI interconnects." Thesis, Massachusetts Institute of Technology, 1990. http://hdl.handle.net/1721.1/13636.

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34

Hsiao, Yu-Chung Ph D. Massachusetts Institute of Technology. "FastCaplet : an efficient 3D capacitance extraction solver using instantiable basis functions for VLSI interconnects." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/62449.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 62-65).
State-of-the-art capacitance extraction methods for Integrated Circuits (IC) involve scanning 2D cross-sections, and interpolating 2D capacitance values using a table lookup approach. This approach is fast and accurate for a large percentage of IC wires. It is however quite inaccurate for full 3D structures, such as crossing wires in adjacent metal layers. For such cases electrostatic field solvers are required. Unfortunately standard field solvers are inherently very time-consuming, making them completely impractical in typical IC design flows. Even fast matrix-vector product approaches (e.g., fastmultipole or precorrected FFT) are inefficient for these structures since they have a significant computational overhead and scale linearly with the number of conductors only for much larger structures with more than several hundreds of wires. In this talk we present therefore a new 3D extraction field solver that is extremely efficient in particular for the smaller scale extraction problem involving the ten to one hundred conductors in the 3D structures that cannot be handled by the 2D scanning and table look up approach. Because of highly restrictive design rules of the recent sub-micro to nano-scale IC technologies, smooth and regular charge distributions extracted from simple model structures can be stored beforehand as "templates" and instantiated and stretched to fit practical complicated cases as basis function building blocks. This "template-instantiated" strategy largely reduces the number of unknowns and computational time without additional overhead. Given that all basis functions are obtained by the same very few stretched templates, Galerkin coefficients can be readily computed from a mixture of analytical, numerical and table lookup approaches. Furthermore, given the low accuracy (i.e., 3%-5%) required by IC extraction and the specific aspect ratios and separations of wires on ICs, we have observed in our numerical experimentations that edge and corner charge singularities do not need to be included in our templates, hence reducing the complexity of our solver even further.
by Yu-Chung Hsiao.
S.M.
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35

Longworth, Hai Pham. "Microstructural modification of thin films and its relation to the electromigration-limited reliability of VLSI interconnects." Thesis, Massachusetts Institute of Technology, 1992. http://hdl.handle.net/1721.1/13114.

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36

Cho, Minki. "Design methodology to characterize and compensate for process and temperature variation in digital systems." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50148.

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The main objective of this dissertation is to investigate a design methodology that can characterize and compensate for process and temperature variation. First, a design methodology is discussed to handle process variation in low-power memory for image processing application. This is followed by a design technique to characterize and recover TSV-defect-induced signal degradation in a 3D integrated circuit. For thermal variation, the spatiotemporal power migration is proposed as a methodology to handle thermal issues in digital systems both during the test and normal operation. The power migration continuously distributes the generated heat in space and time to control chip temperature. To enable this approach a unique method is developed, and verified through hardware for post-fabrication characterization of thermal system and prediction of transient variation in chip temperature. The inverse temperature dependence in a digital logic is characterized through hardware to help better thermal management in wide operating voltage design.
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37

Strehle, Steffen. "Cu(Ag)-Legierungsschichten als Werkstoff für Leiterbahnen höchstintegrierter Schaltkreise." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2007. http://nbn-resolving.de/urn:nbn:de:swb:14-1175691002696-74744.

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Die vorliegende Arbeit verfolgt das Ziel, Cu(Ag)-Dünnschichten als potentiellen Werkstoff für Leiterbahnen in der Mikroelektronik zu untersuchen. Für die Beurteilung dieses Materialsystems wurden vier Schwerpunkte bezüglich der Schichtcharakterisierung definiert: Herstellung, Gefüge, thermomechanische Eigenschaften, Elektromigrationsresistenz. Grundlage sämtlicher Untersuchungen ist eine geeignete Probenpräparation. In Anlehnung an Technologien, die zur Zeit bei der Herstellung von reinen Cu-Leiterbahnen Anwendung finden, erfolgte die Beschichtung der Cu(Ag)-Schichten (Dicke bis 1 µm) galvanisch aus einem schwefelsauren Elektrolyten unter Additiveinsatz auf thermisch oxidierten Siliziumwafern. Hierbei war nicht nur die Abscheidung von ganzflächigen Dünnschichten, sondern auch die Beschichtung auf strukturierte Substrate von Interesse. Die erzeugten Schichtproben werden in ihren Gefügeeigenschaften, vergleichend zu reinen Kupferschichten, charakterisiert. Hierzu zählen Korngrößen und -orientierungen, thermisches Gefügeverhalten, Einbau, Verteilung und Segregation von Silber und Fremdstoffen sowie die elektrischen Eigenschaften. Von grundsätzlicher Bedeutung für das Elektromigrationsverhalten und damit für die Zuverlässigkeit und das Leistungsvermögen sind die thermomechanischen Eigenschaften. Diese werden an ausgedehnten Schichten mit der Substratkrümmungsmessung bis zu Temperaturen von 500°C beschrieben. Die Diskussion des mechanischen Schichtverhaltens umfasst sowohl thermische als auch temporale Charakteristika. Die Untersuchungen geben einen Einblick in die wirkenden Mechanismen des Stofftransports und des Spannungsabbaus. Den Abschluss der Arbeit stellen erste Experimente zum Elektromigrationsverhalten der Cu(Ag)-Dünnschichten dar. Den Kern dieser Analysen bilden Messungen an sog. Blech-Strukturen (Materialdriftexperimente). Hierbei werden geeignete Technologien für die mikrotechnologische Herstellung von derartigen Cu(Ag)-Strukturen vorgestellt. Anhand erster Messungen wird das Elektromigrationsverhalten von Cu(Ag)-Metallisierungen in seinen Grundcharakteristika beschrieben.
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38

Strehle, Steffen. "Cu(Ag)-Legierungsschichten als Werkstoff für Leiterbahnen höchstintegrierter Schaltkreise: Herstellung, Gefüge, thermomechanische Eigenschaften, Elektromigrationsresistenz." Doctoral thesis, Technische Universität Dresden, 2006. https://tud.qucosa.de/id/qucosa%3A24916.

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Die vorliegende Arbeit verfolgt das Ziel, Cu(Ag)-Dünnschichten als potentiellen Werkstoff für Leiterbahnen in der Mikroelektronik zu untersuchen. Für die Beurteilung dieses Materialsystems wurden vier Schwerpunkte bezüglich der Schichtcharakterisierung definiert: Herstellung, Gefüge, thermomechanische Eigenschaften, Elektromigrationsresistenz. Grundlage sämtlicher Untersuchungen ist eine geeignete Probenpräparation. In Anlehnung an Technologien, die zur Zeit bei der Herstellung von reinen Cu-Leiterbahnen Anwendung finden, erfolgte die Beschichtung der Cu(Ag)-Schichten (Dicke bis 1 µm) galvanisch aus einem schwefelsauren Elektrolyten unter Additiveinsatz auf thermisch oxidierten Siliziumwafern. Hierbei war nicht nur die Abscheidung von ganzflächigen Dünnschichten, sondern auch die Beschichtung auf strukturierte Substrate von Interesse. Die erzeugten Schichtproben werden in ihren Gefügeeigenschaften, vergleichend zu reinen Kupferschichten, charakterisiert. Hierzu zählen Korngrößen und -orientierungen, thermisches Gefügeverhalten, Einbau, Verteilung und Segregation von Silber und Fremdstoffen sowie die elektrischen Eigenschaften. Von grundsätzlicher Bedeutung für das Elektromigrationsverhalten und damit für die Zuverlässigkeit und das Leistungsvermögen sind die thermomechanischen Eigenschaften. Diese werden an ausgedehnten Schichten mit der Substratkrümmungsmessung bis zu Temperaturen von 500°C beschrieben. Die Diskussion des mechanischen Schichtverhaltens umfasst sowohl thermische als auch temporale Charakteristika. Die Untersuchungen geben einen Einblick in die wirkenden Mechanismen des Stofftransports und des Spannungsabbaus. Den Abschluss der Arbeit stellen erste Experimente zum Elektromigrationsverhalten der Cu(Ag)-Dünnschichten dar. Den Kern dieser Analysen bilden Messungen an sog. Blech-Strukturen (Materialdriftexperimente). Hierbei werden geeignete Technologien für die mikrotechnologische Herstellung von derartigen Cu(Ag)-Strukturen vorgestellt. Anhand erster Messungen wird das Elektromigrationsverhalten von Cu(Ag)-Metallisierungen in seinen Grundcharakteristika beschrieben.
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39

Ahmed, Mohammad Abrar. "Early Layout Design Exploration in TSV-based 3D Integrated Circuits." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3617.

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Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise. We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects. This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circuits considering the interconnect density on individual device layers. The floorplanning tool uses TSV locations and delay, non-uniform interconnect density across multiple stacked device layers to assess and optimize the buffer count, delay, and interconnect power dissipation in a design. It is shown that the impact of non-uniform interconnect density, across the stacked device layers, should not be ignored, as its contribution to the performance of the 3D interconnects is consequential. A wire capacitance-aware buffer insertion scheme is presented that determines the optimal distance between adjacent buffers on the individual device layers for nonuniform wire density between stacked device layers. The proposed approach also considers TSV location on a 3D wire to optimize the buffer insertion around TSVs. For 3D designs with uniform wire density across stacked device layers, we propose a TSV-aware buffer insertion approach that appropriately models the TSV RC delay impact on interconnect delay to determine the optimum interval between adjacent buffers for individual 3D nets. Moreover, our floorplanning tool help achieve 3D layouts with superior performance by incorporating the impact of nonuniform density on the delay, power and coupling noise in the interconnects during floorplanning.
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40

Kalargaris, Charalampos. "Design methodologies and tools for vertically integrated circuits." Thesis, University of Manchester, 2017. https://www.research.manchester.ac.uk/portal/en/theses/design-methodologies-and-tools-for-vertically-integrated-circuits(63c9c674-566a-44e5-b6b6-8a277b1adf08).html.

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Vertical integration technologies, such as three-dimensional integration and interposers, are technologies that support high integration densities while offering shorter interconnect lengths as compared to planar integration and other packaging technologies. To exploit these advantages, however, several challenges lay across the designing, manufacturing and testing stages of integrated systems. Considering the high complexity of modern microelectronic devices and the diverse features of vertical integration technologies, this thesis sheds light on the circuit design process. New methodologies and tools are offered in order to assess and improve traditional objectives in circuit design, such as performance, power, and area for vertically integrated circuits. Interconnects on different interposer materials are investigated, demonstrating the several trade-offs between power, performance, area, and crosstalk. A backend design flow is proposed to capture the performance and power gains from the introduction of the third dimension. Emphasis is also placed on the power consumption of modern circuits due to the immense growth of battery-operated devices in the last fifteen years. Therefore, the effect of scaling the operating voltage in three-dimensional circuits is investigated as it is one of the most efficient techniques for reducing power while considering the performance of the circuit. Furthermore, a solution to eliminate timing penalties from the usage of voltage scaling technique at finer circuits granularities is also presented in this thesis.
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41

Chou, Wen-Hsiang, and 周文祥. "VLSI Interconnect Capacitance Characterization." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/88843524230529460450.

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碩士
元智大學
資訊工程學系
92
In the ultra deep sub micron (UDSM) designs, the electrical properties of the conducting wires have become increasingly important so that they play an important role in maintaining signal integrity (SI). SI problem manifests itself in various ways. The crosstalk due to wire coupling, IR drop on supply and grounded bus etc. are main sources of SI problems. Crosstalk can either cause signal delay variation that may lead to timing violations or unintended glitches that may lead to functional failures. Hence, the coupling capacitance is an important parameter for SI. In this thesis, we will study how capacitance is varying with geometry dimension and topological structure of wires. We experiments with two different structures, the structures including dummy metals and the structures not including dummy metals. We observed that the total and coupling capacitance are not much influenced by the distribution of the dummy metal on top and bottom layers when metal density is larger than 30%. This is also trace for the non-dummy metal structures. Many rules such as this one are derived from our experimental results. They are very suitable for being used in fast full-chip interconnect capacitance extractions.
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42

Zhang, Yilin 1986. "Interconnect optimizations for nanometer VLSI design." Thesis, 2014. http://hdl.handle.net/2152/26040.

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As the semiconductor technology scales into deeper sub-micron domain, billions of transistors can be used on a single system-on-chip (SOC) makes interconnection optimization more important roughly for two reasons. First, congestion, power, timing in routing and buffering requirements make inter- connection optimization more and more challenging. Second, gate delay get- ting shorter while the RC delay gets longer due to scaling. Study of interconnection construction and optimization algorithms in real industry flows and designs ends up with interesting findings. One used to be overlooked but very important and practical problem is how to utilize over- the-block routing resources intelligently. Routing over large IP blocks needs special attention as there is almost no way to insert buffers inside hard IP blocks, which can lead to unsolvable slew/timing violations. In current design flows we have seen, the routing resources over the IP blocks were either dealt as routing blockages leading to a significant waste, or simply treated in the same way as outside-the-block routing resources, which would violate the slew constraints and thus fail buffering. To handle that, this work proposes a novel buffering-aware over-the- block rectilinear Steiner minimum tree (BOB-RSMT) algorithm which helps reclaim the “wasted” over-the-block routing resources while meeting user-specified slew constraints. Proposed algorithm incrementally and efficiently migrates initial tree structures with buffering-awareness to meet slew constraints while minimizing wire-length. Moreover, due to the fact that timing optimization is important for the VLSI design, in this work, timing-driven over-the-block rectilinear Steiner tree (TOB-RST) is also studied to optimize critical paths. This proposed TOB-RST algorithm can be used in routing or post-routing stage to provide high-quality topologies to help close timing. Then a follow-up problem emerges: how to accomplish the whole routing with over-the-block routing resources used properly. Utilizing over-the- block routing resources could dramatically improve the routing solution, yet require special attention, since the slew, affected by different RC on different metal layers, must be constrained by buffering and is easily violated. Moreover, even of all nets are slew-legalized, the routing solution could still suffer from heavy congestion problem. A new global router, BOB-Router, is to solve the over-the-block global routing problem through minimizing overflows, wire-length and via count simultaneously without violating slew constraints. Based on my completed works, BOB-RSMT and BOB-Router tremendously improve the overall routing and buffering quality. Experimental results show that proposed over-the-block rectilinear Steiner tree construction and routing completely satisfies the slew constraints and significantly outperforms the obstacle-avoiding rectilinear Steiner tree construction and routing in terms of wire-length, via count and overflows.
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43

Tseng, Wenliang, and 曾文亮. "Test and Analysis of VLSI Interconnect systems." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/34638520387274416684.

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博士
國立中央大學
電機工程研究所
95
This thesis is a comprehensive works of interconnect models in VLSI system. The relative works are suitable to explore the influence of interconnect models on high-speed digital signal. For basic models, the wired-logic is used to propose an efficient interconnect BIST methodology to deal with the tri-state driver contention problem. It also improves the fault coverage and makes pattern reuse possible for SoC system. Simulation results verify the mathematical analysis and reassure the feasibility the methodology. For quasi-TEM models, two tasks focus on the development of the gen-eral-purpose passive transmission line macromodel for a circuit simulation environ-ment. The first task is in order to solve the accuracy problem of model order reduction for ladder networks of distributed transmission lines. Base on that, this work proposes a new criterion to be able to minimize the number of ladder sections to ensure the ac-curacy. The pole-residue pairs of admittance matrix for the finite and infinite sections of ladder networks are required to address the criterion. However, the challenge is numerical computation of CPU cost. Therefore, this work proposes compact closed forms to overcome the difficulty. The valid examples delineate the feasibility of the proposed criterion. The other task is model order reduction problem for mixed dis-tributed transmission line/RLC component network system. A novel technique based on Krylov-subspace algorithm is proposed to obtain reduced macromodel. The com-plex network can transform into a linear time-delay system using DEPACT technique. A key feature of the proposed technique is using a unified formulation to preserve passivity. The mathematical derivation proof and simulation results approve the vali-dation of the proposed technique. Moreover, this technique is also extended to solve the H-infinite model order reduction problem in control system. Two theorems are proposed to deal with H-infinite norm bound and passivity problems. Based on the theorems, the re-duced system is obtained from the feasible solutions of simple linear matrix inequali-ties. Therefore, the proposed technique provides an efficient, accurate and passive re-duced system to application in control system.
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44

"Interconnect planning in physical design of VLSI." Thesis, 2006. http://library.cuhk.edu.hk/record=b6074151.

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For the congestion issue, we found that the existing congestion models will very often over-estimate the congestion at the densely routed regions because real routers will perform rip-up and re-route operations and route the nets with detour to avoid overflow. We propose a 3-step approach that is designed to tackle this problem. It can simulate the global routing, detailed routing and rip-up and re-route process in the real routing procedure. Results show that the prediction accuracy can be improved by 30%. In addition, we have also implemented a routability-driven floorplanner with our congestion model. Results show that the number of un-routable wires can be reduced if the number of overflow tiles can be reduced during floorplanning. Then we studied and developed two post-processing steps to be applied on an interconnect optimized floorplan or placement to further reduce the total wirelength or area. For the wirelength issue, we presented an elegant solution to the cell flipping problem. We presented a detailed study of this cell flipping problem in a placement result to reduce interconnect length. We find the optimal flipping of the cells by formulating the cell flipping problem as a mixed integer linear programming problem to give the shortest total wirelength. In order to reduce the runtime, we proposed a cell orientation fixing step to fix the orientations of some cells. Results show that we can obtain optimal result by solving the mixed integer linear programming problem of the remaining variables directly or the problem can be solved by linear programming such that we can still obtain a result very close to the optimal solution with a much shorter runtime. For area reduction on an interconnect optimized floorplan, we proposed a new approach called deadspace utilization to reduce the total area of an interconnect optimized floorplan by making use of the shape flexibility of some modules. Results show that we can apply this deadspace utilization technique to reduce the area and wirelength of the original floorplan further, subject to the constraint of maintaining the routability and congestion of the original floorplan.
We have studied several interconnect-related optimization problems in floor-planning and placement of VLSI circuits in details. When the number of small logic gates is large in a circuit design, good netlist designs may still result in poor layouts because of various interconnect problems. Most of the problems cannot be fixed manually today because of the incomprehensible circuit complexity. Design automation techniques on interconnect issues in physical design of VLSI circuits becomes indispensable. Recently, congestion minimization and wirelength optimization are two hot topics in interconnect planning.
Sham Chiu Wing.
"March 2006."
Adviser: Young Fung Yu.
Source: Dissertation Abstracts International, Volume: 67-11, Section: B, page: 6634.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2006.
Includes bibliographical references (p. 106-115).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstracts in English and Chinese.
School code: 1307.
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45

Tsai, Jung-Tai. "VlSI Interconnect Optimization Considering Non-uniform Metal Stacks." Thesis, 2013. http://hdl.handle.net/1969.1/151263.

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With the advances in process technology, comes the domination of interconnect in the overall propagation delay in modern VLSI designs. Hence, interconnect synthesis techniques, such as buffer insertion, wire sizing and layer assignment play critical roles in the successful timing closure for EDA tools. In this thesis, while our aim is to satisfy timing constraints, accounting for the overhead caused by these optimization techniques is of another primary concern. We utilized a Lagrangian relaxation method to minimize the usage of buffers and metal resources to meet the timing constraints. Compared with the previous work that extended traditional Van Ginneken’s algorithm, which allows for bumping up the wire from thin to thick given significant delay improvement, our approach achieved around 25% reduction in buffer + wire capacitance under the same timing budget.
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46

Hsu, Li-hsuan, and 許禮璿. "Study on residual stress of VLSI interconnect structures." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/44862646840071659826.

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碩士
國立成功大學
光電科學與工程研究所
97
Electroplated Cu films with different plating conditions are characterized to study the residual stress during annealing. An improved copper (Cu) process with strategy plating current was used to stabilize the residual stress and suppress the void formation. Grain growth during the process induces residual stress in the film. The Cu grain size is inverse proportional to the amplitude of the plating current in the electroplated process, and the plating current dominates the density of the grain boundary due to the aggregation of Cu grain. Therefore the elimination of the grain boundaries happens in the first thermal cycle and generates a tensile residual stress. The electroplated process by the improved strategy plating current was presented to produce various grain sizes to enhance the interface packing density of the Cu film. This result leads to a higher ensity of the grain boundaries and is helpful to the grain growth only by the effect of Cu self-annealing. The residual stress keeps a stable value without the thermal treatment. This strategy plating method presents a reliable Cu interconnect process without considering the change in the residual stress.
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47

Chy-Hui, Hong. "Interconnect Delay Bound Generator for VLSI Physical Design Synthesis." 2000. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611304167.

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48

Zeng, Jun-Kuei, and 曾俊貴. "VLSI Interconnect Delay and Slew Metrics Using Probability Distribution." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/14476069157913153510.

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博士
臺灣大學
電機工程學研究所
98
As integrated circuit process technology is changing into the ultra deep submicron era, the complex interconnection topology and metal resistance shielding effects problems are very serious, resulting in very stiff interconnection structure. As inaccurate delay on stiff interconnect sinks creates a situation where decisions on when to evaluate by statistical static time analysis are not cluster distribution, we cannot roughly classify the interconnect into near-end, middle-end, and far-end. Although several delay metrics have been proposed, they are inefficient and difficult to implement. Hence, we propose several new delay metrics for interconnection based on probability distribution. Our metrics are efficient, easy to implement, and can precisely label inaccurate sinks and efficiently calibrate them; the overall standard deviation and error mean are smaller than in previous works.
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49

Cheng, Yan-Pin, and 鄭彥彬. "Overshoot Control for Two Coupled Interconnect in VLSI System." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/19555012956126800230.

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碩士
長庚大學
電機工程研究所
86
In designing high performance interconnect in high-density integrated circuits, one design criterion is to avoid voltage ringings and false logic switchings. In this thesis, based on the parameters of the two coupled RLC interconnects, several systematic design methods will be investigated to avoid the voltage ringing phenomena. Simulation results will be performed to demonstrate the feasibility of these methods.
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50

Hong, Chy-Hui, and 洪旗徽. "Interconnect Delay Bound Generator for VLSI Physical Design Synthesis." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/57972351684588043282.

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碩士
元智大學
資訊工程研究所
88
Though the net-length bound driven placement has long been questioned by many designers about its feasibility, it is worth revisiting this approach given that net length bounds can be adapted for the progress of the placement process. In response to an attempt to develop an interconnect length driven standard cell placer (ILDPer) by a colleague in our laboratory, this thesis proposes to develop a net delay (length) bound generator to support its development. The past research has been focused more on generating bound for each net without considering the influence of false paths. To consider the interconnect RC effect, our bound generator will compute for each source-sink pair a delay bound with exclusion of static false paths. Several strategies of net weight assignment and the limitation of the maximum and minimum delay bounds are employed to make the delay bound more reasonable. The bound generator which is integrated into the ILDPer can dynamically generate, upon a request by the ILDPer, a new set of delay bound based on current partial placement. As time goes by, the partial placement will provide more accurate cell position such that the new set of net delay bounds is easier to satisfy. Some MCNC benchmark circuits are used to evaluate the efficiency and correctness. The experimental results show the employment of using delay bounds to influence the movement of cells is viable. The longest path delays are improved up to 32% when compared to those obtained by Cadence Silicon Ensemble.
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