Journal articles: 'VLSI interconnect'

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CUMMING, DAVID R. S. "Improved VLSI interconnect." International Journal of Electronics 86, no. 8 (August 1999): 957–65. http://dx.doi.org/10.1080/002072199132950.

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Karthikeyan, A., and P. S. Mallick. "Optimization Techniques for CNT Based VLSI Interconnects — A Review." Journal of Circuits, Systems and Computers 26, no. 03 (November 21, 2016): 1730002. http://dx.doi.org/10.1142/s0218126617300021.

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Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22[Formula: see text]nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a detailed discussion on the techniques and approaches of past, present and future relevant for interconnects of VLSI circuits.

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Poltz, J. "MODELING OF VLSI INTERCONNECT." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 13, no. 1 (January 1994): 191–94. http://dx.doi.org/10.1108/eb051872.

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Karthikeyan, A., and P. S. Mallick. "Buffer for High Performance in CNT Based VLSI Interconnects." Advanced Science Letters 24, no. 8 (August 1, 2018): 5975–81. http://dx.doi.org/10.1166/asl.2018.12230.

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Integrated circuits (IC’s) are sized for higher performance and packing density. Interconnects are major components to carry signals between transistors. Interconnect delay increases due to increase in length of interconnect. Optimization of interconnects is more essential to improve the performance of integrated circuits. Repeater insertion is an important technique used in optimizing the performance of interconnects in integrated circuits. Repeaters have to be designed to satisfy the performance constraints. In this paper we have designed a new repeater using transistors and analyzed the performance at various bias levels. The Repeater design was implemented at various technology nodes using PTM models and Bulk CMOS. Delay and power dissipation are analyzed for various voltage levels and load levels using Spice simulations. The results show that the proposed repeater has lesser delay compared to the conventional repeater with an increase of power dissipation and they are more suitable for Critical path in VLSI interconnects. They can be applicable for CNT based VLSI interconnects.

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Kumar Rai, Mayank, Rajesh Khanna, and Sankar Sarkar. "Control of tube parameters on SWCNT bundle interconnect delay and power dissipation." Microelectronics International 31, no. 1 (December 20, 2013): 24–31. http://dx.doi.org/10.1108/mi-03-2013-0016.

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Purpose – This paper aims to propose to study the control of tube parameters in terms of diameter, separation between adjacent tubes and length, on delay and power dissipation in single-walled carbon nanotube (SWCNT) bundle interconnect for VLSI circuits. Design/methodology/approach – The paper considers a distributed-RLC model of interconnect. A CMOS-inverter driving a distributed-RLC model of interconnect with load of 1 pF. A 0.1 GHz pulse of 2 ns rise time provides input to the CMOS-inverter. For SPICE simulation, predictive technology model (PTM) is used for the CMOS-driver. The performance of this setup is studied by SPICE simulation in 22 nm technology node. The results are compared with those of currently used copper interconnect. Findings – SPICE simulation results reveal that delay increases with increase in separation between tubes and diameter whereas the reverse is true for power dissipation. The authors also find that SWCNT bundle interconnects are of lower delay than copper interconnect at various lengths and higher power dissipation due to dominance of larger capacitance of tube bundle. Originality/value – The investigations show that tube parameters can control delay and this can also be utilized to decrease power dissipation in SWCNT bundle interconnects for VLSI applications.

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DEHON, ANDRÉ, FRED DRENCKHAHN, THOMAS KNIGHT, and HENRY MINSKY. "THREE-DIMENSIONAL PACKAGING FOR HIGH-PERFORMANCE INTERCONNECT IN LARGE-SCALE VLSI SYSTEMS." International Journal of High Speed Electronics and Systems 06, no. 04 (December 1995): 613–30. http://dx.doi.org/10.1142/s0129156495000225.

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The transit time through the interconnect between VLSI components can be a significant fraction of the latency in a large VLSI system. In this paper we describe a scheme for dense, three-dimensional packaging of VLSI components which reduces chip-to-chip transit latencies by reducing interconnect distances. Our packaging scheme sandwiches layers of conventional printed-circuit boards between layers of packaged components to efficiently utilize all three spatial dimensions for interconnect. We introduce the key components of our stack packaging scheme and show how they combine to provide efficient housing for a large range of large-scale VLSI systems.

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Sathyanarayanan, D., and M. Mohamed. "Implementation of VLSI interconnect design." International Journal of Advanced Technology and Engineering Exploration 5, no. 42 (May 21, 2018): 96–98. http://dx.doi.org/10.19101/ijatee.2018.542006.

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Sechler, R. F. "Interconnect design with VLSI CMOS." IBM Journal of Research and Development 39, no. 1.2 (January 1995): 23–31. http://dx.doi.org/10.1147/rd.391.0023.

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Shacham-Diamand, Yosi. "The Reliability of Aluminum/Tungsten Technology for VLSI Applications." MRS Bulletin 20, no. 11 (November 1995): 78–82. http://dx.doi.org/10.1557/s0883769400045644.

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Interconnects technology and back-end processing moved to the center stage of very large-scale integration (VLSI) technology in the mid-1980s. At that time, the critical dimensions dropped below 1 μm while the chip size and complexity increased to a level where interconnects were recognized to be a limiting factor. As dimensions decreased, the step coverage of sputtered aluminum inside contacts and via-contact holes decreased and alternative technologies were studied. The increasing cost of ownership (COO) of single-wafer Al sputtering processes also supported the search for alternative technologies, such as tungsten chemical vapor deposition (CVD) for via contacts and plugs (Figure 1). Only recently have all the W CVD process steps been optimized to lower cost without loss of reliability and/or performance. The development of cluster tool technology and multiwafer process modules also allowed reliable and cost-effective utilization of the W/Al technology.Tungsten technology for VLSI circuits became complementary to that of aluminum. Tungsten thin-film resistivity ρw = 7–8 μΩ cm is much higher than that of aluminum ρAl = 3–4 μΩ cm, introducing large W interconnect resistance-capacitance (RC) delays compared to Al. Therefore, tungsten is not favorable for high-speed global-interconnect schemes. However, tungsten is suitable for local interconnects where the impedance of the driving transistors is dominant and the RC interconnect delay is less significant. Tungsten is also suitable for contact filling, in which the via resistance is negligible. For these applications, tungsten became a dominant technology and was integrated with the aluminumalloy-based technology used for global interconnects.

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Xu, Yao, Ashok Srivastava, and Ashwani K. Sharma. "Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance." VLSI Design 2010 (February 17, 2010): 1–8. http://dx.doi.org/10.1155/2010/864165.

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Current transport and dynamic models of carbon nanotube field-effect transistors are presented. A model of single-walled carbon nanotube as interconnect is also presented and extended in modeling of single-walled carbon nanotube bundles. These models are applied in studying the performances of circuits such as the complementary carbon nanotube inverter pair and carbon nanotube as interconnect. Cadence/Spectre simulations show that carbon nanotube field-effect transistor circuits can operate at upper GHz frequencies. Carbon nanotube interconnects give smaller delay than copper interconnects used in nanometer CMOS VLSI circuits.

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Cong, Jason, Lei He, Cheng-Kok Koh, and Patrick H. Madden. "Performance optimization of VLSI interconnect layout." Integration 21, no. 1-2 (November 1996): 1–94. http://dx.doi.org/10.1016/s0167-9260(96)00008-9.

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Anand, M. B., H. Shibata, and M. Kakumu. "Multiobjective optimization of VLSI interconnect parameters." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, no. 12 (1998): 1252–61. http://dx.doi.org/10.1109/43.736565.

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Anand, M. B., H. Shibata, and M. Kakumu. "Optimization study of VLSI interconnect parameters." IEEE Transactions on Electron Devices 47, no. 1 (2000): 178–86. http://dx.doi.org/10.1109/16.817584.

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14

Tsong-Ming Chen and A. M. Yassine. "Electrical noise and VLSI interconnect reliability." IEEE Transactions on Electron Devices 41, no. 11 (1994): 2165–72. http://dx.doi.org/10.1109/16.333837.

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Thomas, Michael E. "Manufacturing considerations for VLSI interconnect systems." Materials Chemistry and Physics 41, no. 3 (August 1995): 167–72. http://dx.doi.org/10.1016/0254-0584(95)01510-8.

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KAVICHARAN, M., N. S. MURTHY, and N. BHEEMA RAO. "EFFICIENT DELAY AND CROSSTALK ESTIMATION MODELS FOR CURRENT-MODE HIGH SPEED INTERCONNECTS UNDER RAMP INPUT." Journal of Circuits, Systems and Computers 23, no. 06 (May 14, 2014): 1450082. http://dx.doi.org/10.1142/s0218126614500820.

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In this paper, closed-form models for the computation of finite ramp responses of current-mode resistance inductance capacitance (RLC) interconnects in VLSI circuits are presented. These models are based on extended Eudes model and Scaling and Squaring algorithm which allow numerical estimation of delay in lossy very large scale integration (VLSI) interconnects. The existing Eudes model for interconnect transfer function approximation is extended to higher-order and then Scaling and Squaring method is applied for further improving the accuracy of delay estimation. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit inductances and load capacitances. The estimated 50% delay values are compared with HSPICE W-element model. The worst case errors observed in the estimated delay values are 14.3% for Eudes model and 2% for extended Eudes model while the proposed Scaling and Squaring based model with 1% error is in very good agreement with HSPICE for line lengths 0.1–0.5 cm. The estimated crosstalk induced delay values of proposed model maximum error percentage is nearly half of the extended Eudes model. For both single and three coupled interconnect lines, the proposed model is in good agreement with HSPICE.

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Smy, T., S. K. Dew, and M. J. Brett. "Simulation of Microstructure and Surface Profiles of Thin Films for VLSI Metallization." MRS Bulletin 20, no. 11 (November 1995): 65–69. http://dx.doi.org/10.1557/s0883769400045619.

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A crucial step in the manufacture of very large-scale integration (VLSI) integrated circuits is the fabrication of reliable, low-resistance metal interconnects between semiconductor devices. The fabrication of these interconnects is generally performed by depositing a blanket metal film and then patterning it by lithographic and etching techniques. The primary means of depositing thin metal films for VLSI interconnects are sputtering and chemical vapor deposition (CVD).The creation of reliable interconnects is, however, complicated by a number of issues. In order to obtain low contact resistance, to inhibit reactions with the silicon, and to provide good adhesion to both Si and SiO2, contact, barrier, and adhesion layers are generally deposited prior to the deposition of the low-resistance metal film that forms the bulk of the interconnect. If these layers are to provide an effective barrier to diffusion of the interconnection metal to the silicon, they must be deposited in a uniform, homogeneous form. It is also necessary that the primary interconnect material have as high step coverage as is possible in order to reduce current crowding, local heating effects, and electromigration. Unfortunately, as VLSI circuit densities have increased, the fabrication of interconnects requires high aspect-ratio contact cuts, and relatively severe local topographies can result. These factors make it difficult to deposit films with good step and bottom coverage.In addition to these concerns with the film surface profile, another factor is becoming increasingly significant. Both sputtering and CVD produce thin films with characteristic microstructures. This microstructure consists of columns or grains separated by grain boundaries and voids.

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18

Kaushik, B. K., S. Sarkar, R. P. Agarwal, and R. C. Joshi. "Voltage scaling – a novel approach for crosstalk reduction in global VLSI interconnects." Microelectronics International 24, no. 1 (January 2, 2007): 40–45. http://dx.doi.org/10.1108/13565360710725937.

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PurposeTo analyze the effect of voltage scaling on crosstalk.Design/methodology/approachVoltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus, a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product. Therefore, their lies an optimized supply voltage where‐in power dissipation and propagation delay can be optimized. Many of the previous researches have discussed about power dissipation and propagation delay only with voltage scaling. This paper for first time shows the effect on crosstalk in voltage scaled interconnects. In this paper, we primarily study the noise for an input signal having transition time of 50 ps. The simulations are run for interconnect length of 2 and 4 mm. These parameters are varied for four different cases of stimulations to aggressor and victim lines viz. VA (input at aggressor node A) and VB (input at victim node B) switching in same direction; VA is switching and VB at static low; VA and VB are switching in opposite direction; VA is switching and VB at static high.FindingsIt is quite encouraging to observe that irrespective of interconnect length and technology node used, an optimized voltage scaling reduces normalized crosstalk level.Originality/valueVoltage scaling can be effectively used for crosstalk reduction by the new era VLSI interconnect designers. This paper shows simulation results for crosstalk reduction in different nano‐sized CMOS driven RLC‐modeled interconnects.

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Adams, A. C., R. S. Bentson, W. J. Bertram, H. J. Levinstein, W. Q. McKnight, Jacques J. Rubin, and B. A. ter Haar. "High Density Interconnect for Advanced VLSI Packaging." Defect and Diffusion Forum 59 (January 1991): 129–36. http://dx.doi.org/10.4028/www.scientific.net/ddf.59.129.

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Kameyama, Shuichi. "VLSI Board Test. Interconnect and Delay Test." Journal of SHM 11, no. 2 (1995): 24–28. http://dx.doi.org/10.5104/jiep1993.11.2_24.

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Ciesielski, M. J. "Layer assignment for VLSI interconnect delay minimization." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 8, no. 6 (June 1989): 702–7. http://dx.doi.org/10.1109/43.31525.

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Seok-Yoon Kim, N. Gopal, and L. T. Pillage. "Time-domain macromodels for VLSI interconnect analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 10 (1994): 1257–70. http://dx.doi.org/10.1109/43.317469.

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Tang, T. E., Che-Chia Wei, R. A. Haken, T. C. Holloway, L. R. Hite, and T. G. W. Blake. "Titanium nitride local interconnect technology for VLSI." IEEE Transactions on Electron Devices 34, no. 3 (March 1987): 682–88. http://dx.doi.org/10.1109/t-ed.1987.22980.

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Burghartz, J. N., K. A. Jenkins, and M. Soyuer. "Multilevel-spiral inductors using VLSI interconnect technology." IEEE Electron Device Letters 17, no. 9 (September 1996): 428–30. http://dx.doi.org/10.1109/55.536282.

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Poltz, Juliusz. "Optimizing VLSI interconnect model for SPICE simulation." Analog Integrated Circuits and Signal Processing 5, no. 1 (January 1994): 87–94. http://dx.doi.org/10.1007/bf01673909.

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Wang, Jia, Lin Liu, Yuchen Zhou, and Shiyan Hu. "Buffering Carbon Nanotube Interconnects Considering Inductive Effects." Journal of Circuits, Systems and Computers 25, no. 08 (May 17, 2016): 1650093. http://dx.doi.org/10.1142/s0218126616500936.

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While copper interconnect scaling is approaching its fundamental physical limit, increasing wire resistivity and delay have greatly limited the circuit miniaturization. The emerging carbon nanotube (CNT) interconnects, especially single-walled CNTs (SWCNTs) bundle interconnects, have become a promising replacement material. Nevertheless, physical design optimization techniques are still needed to allow them achieving the desired performances. While the preliminary conference version of this work [L. Liu, Y. Zhou and S. Hu, Proc. IEEE Computer Society Annual Symp. on VLSI (ISVLSI), 2014] designs the first timing driven buffer insertion technique for SWCNT interconnects, it only considers resistive and capacitive effects but not inductive effects. Although inductance could be negligible for prevailing CNT-based circuit designs, it becomes important when designing ultra-high performance chips in the future. Thus, this paper considers buffering inductive bundled SWCNTs interconnects through developing a dynamic programming algorithm for buffer insertion using the RLC tree delay model. Our experiments demonstrate that bundled SWCNTs interconnect-based buffering can effectively reduce the delay by over [Formula: see text] when inductive effects are considered. With the same timing constraint, bundled SWCNTs interconnect-based buffering can save over 20% buffer area compared to copper interconnect based buffering, while still running about [Formula: see text] faster.

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Kahng, Andrew B., Sudhakar Muddu, and Egino Sarto. "Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs." VLSI Design 10, no. 1 (January 1, 1999): 21–34. http://dx.doi.org/10.1155/1999/38974.

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Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We address four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters Should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30% in current technologies.

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Abbasi, Ruby. "Reduction of Transmission Line Losses Using VLSI Interconnect." Procedia Engineering 30 (2012): 10–19. http://dx.doi.org/10.1016/j.proeng.2012.01.828.

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Mehri, Milad, Reza Sarvari, Mohammad Hossein Mazaheri Kouhani, and Zahra Shariati. "VLSI interconnect issues in definitive and stochastic environments." Microelectronics Journal 46, no. 5 (May 2015): 351–61. http://dx.doi.org/10.1016/j.mejo.2015.02.004.

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Awano, Yuji, Shintaro Sato, Mizuhisa Nihei, Tadashi Sakai, Yutaka Ohno, and Takashi Mizutani. "Carbon Nanotubes for VLSI: Interconnect and Transistor Applications." Proceedings of the IEEE 98, no. 12 (December 2010): 2015–31. http://dx.doi.org/10.1109/jproc.2010.2068030.

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Frost, D. F., and K. F. Poole. "RELIANT: a reliability analysis tool for VLSI interconnect." IEEE Journal of Solid-State Circuits 24, no. 2 (April 1989): 458–62. http://dx.doi.org/10.1109/4.18608.

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32

Bradley, E., and P. K. L. Yu. "Proposed Modulator for Global VLSI Optical Interconnect Network." Japanese Journal of Applied Physics 26, Part 2, No. 6 (June 20, 1987): L971—L973. http://dx.doi.org/10.1143/jjap.26.l971.

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Wimer, Shmuel, Konstantin Moiseev, and Avinoam Kolodny. "On VLSI interconnect optimization and linear ordering problem." Optimization and Engineering 12, no. 4 (November 27, 2010): 603–9. http://dx.doi.org/10.1007/s11081-010-9128-9.

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Kobeda, E., N. J. Mazzeo, J. P. Gambino, H. Ng, G. L. Patton, J. D. Warnock, S. Basavaiah, J. F. White, and J. D. Cressler. "Fabrication of Tungsten Local Interconnect for VLSI Bipolar Technology." Journal of The Electrochemical Society 140, no. 10 (October 1, 1993): 3007–13. http://dx.doi.org/10.1149/1.2220948.

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Shyh-Chyi Wong, Gwo-Yann Lee, and Dye-Jyun Ma. "Modeling of interconnect capacitance, delay, and crosstalk in VLSI." IEEE Transactions on Semiconductor Manufacturing 13, no. 1 (2000): 108–11. http://dx.doi.org/10.1109/66.827350.

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Simunic, T., J. W. Rozenblit, and J. R. Brews. "VLSI interconnect design automation using quantitative and symbolic techniques." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B 19, no. 4 (1996): 803–12. http://dx.doi.org/10.1109/96.544372.

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Amin, Abu Bony, and Muhammad Sana Ullah. "Mathematical Framework of Tetramorphic MWCNT Configuration for VLSI Interconnect." IEEE Transactions on Nanotechnology 19 (2020): 749–59. http://dx.doi.org/10.1109/tnano.2020.3026609.

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Massengill, Lloyd W., and Neal Bengtson. "RSIM: A circuit simulation program for VLSI interconnect networks." SIMULATION 52, no. 2 (February 1989): 68–77. http://dx.doi.org/10.1177/003754978905200204.

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Ling-zhi, Liu, Gong Shu, and Rong Meng-tian. "Crosstalk model and estimation formula for VLSI interconnect wires." Wuhan University Journal of Natural Sciences 7, no. 3 (September 2002): 333–37. http://dx.doi.org/10.1007/bf02912153.

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R. Murthy, A. S., and Sridhar T. "Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 1 (April 1, 2018): 27. http://dx.doi.org/10.11591/ijeecs.v10.i1.pp27-36.

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<p>In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and power distribution to multi-core architectures is also posing a challenge to power distribution networks in the integrated circuits. Clock distribution networks for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. Therefore, this paper introduce low swing signaling schemes to decrease delay and power consumption. A comparative study presented of low voltage signaling schemes in terms of delay, power consumption and power delay product. Here, we have presented a power efficient signaling topology for driving the clocks to higher interconnect lengths.</p>

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Jain, Neeraj, A. K. Aggarwal, and P. K. Chaudhary. "Carbon Nanotubes: Good Candidate for VLSI Interconnects." Applied Mechanics and Materials 378 (August 2013): 165–71. http://dx.doi.org/10.4028/www.scientific.net/amm.378.165.

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Carbon nanotubes are being seen as a promising new class of electronic materials owing to the change in their properties with chirality and geometry of the nanotube. They are being considered for future VLSI applications due to their superior conductance and inductance properties which are important parameters while considering any material for an interconnect or via applications.In this paper, we report the variation in electrical and thermal conductance as well as inductance of a CNT with its geometrical features using a diameter dependent model. Also the dependence of conductance and inductance of a CNT on the type of nanotubes, tube length and tube diameter has been studied. As we know that at nanometre scale, the electrical and thermal transport properties of the components become extremely important as regards the functioning of the device and it is difficult to accurately measure these properties, therefore predictions using modeling and simulation play an important role in providing a guideline for design and fabrication of CNT interconnects and understanding the working of various other CNT based devices.

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Mohamed Yousuff, C., V. Mohamed Yousuf Hasan, and M. R. Khan Galib. "A Survey Addressing on High Performance On-Chip VLSI Interconnect." International Journal of Electronics and Telecommunications 59, no. 3 (September 1, 2013): 307–12. http://dx.doi.org/10.2478/eletel-2013-0037.

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Abstract With the rapid increase in transmission speeds of communication systems, the demand for very high-speed lowpower VLSI circuits is on the rise. Although the performance of CMOS technologies improves notably with scaling, conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of these applications. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, power and delay optimization and also comparative analysis of various techniques for high speed design have been discussed.

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SARASWAT, KRISHNA C., CHI ON CHUI, PAWAN KAPUR, TEJAS KRISHNAMOHAN, AMMAR NAYFEH, ALI K. OKYAY, and ROHIT S. SHENOY. "PERFORMANCE LIMITATIONS OF Si CMOS AND ALTERNATIVES FOR NANOELECTRONICS." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 175–92. http://dx.doi.org/10.1142/s0129156406003606.

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It is believed that below the 65-nm node although the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Examples of novel device structures being investigated are double gate or surround gate MOS and examples of novel materials are high mobility channel materials like strained Si and Ge , high-k gate dielectrics and metal gate electrodes. Continuous scaling of VLSI circuits can pose significant problems for interconnects. We show that resistance of interconnect wires in light of scaling induced increase in electron surface scattering, fractional cross section area occupied by the high resistivity barrier and realistic interconnect operation temperature will lead to a significant rise in the effective resistivity of Cu . As a result both power and delay of these interconnects is likely to rise significantly in the future. In the light of various metal interconnect limitations, alternate solutions need to be pursued. We focus on two such solutions, optical interconnects and three-dimensional (3-D) ICs with multiple active Si layers. Heterogeneous integration of the new structures and materials on Si may take us to sub-20 nm regime, but will require new fabrication technology solutions that are generally compatible with current and forecasted installed Si manufacturing.

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SHIN, YOUNGSOO, and JUNGHYUP LEE. "POWER ANALYSIS OF VLSI INTERCONNECT WITH RLC TREE MODELS AND MODEL REDUCTION." Journal of Circuits, Systems and Computers 15, no. 03 (June 2006): 399–408. http://dx.doi.org/10.1142/s0218126606003180.

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The lumped capacitance model, which ignores the existence of wire resistance, has been traditionally used to estimate the charging and discharging power consumption of CMOS circuits. We show that this model is not correct by pointing out that MOSFETs consume only part of the energy supplied by the source. During this study, it was revealed that about 20% of the power is consumed in the wire resistance of the buffered global interconnect, when the interconnect is modeled with RC tree networks. The percentage goes up to 30 when RLC model is used indicating the importance of inductance in interconnect model for power estimation. For RLC networks, we propose a compact yet very accurate power estimation method based on a model reduction technique.

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Kar, R., V. Maheshwari, Ashis K. Mal, and A. K. Bhattacharjee. "Delay Analysis on-chip VLSI Interconnect using Gamma Distribution Function." International Journal of Computer Applications 1, no. 3 (February 25, 2010): 77–80. http://dx.doi.org/10.5120/81-176.

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Venkatavara, D., and Suresh Jaganathan. "Performance Optimization of Nonlinear VLSI Interconnect Circuit using Schmitt Trigger." International Journal of Computer Applications 173, no. 4 (September 15, 2017): 14–17. http://dx.doi.org/10.5120/ijca2017915284.

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Louis, D., A. Beverina, C. Arvet, E. Lajoinie, C. Peyne, D. Holmes, and D. Maloney. "Cleaning status on low-k dielectric in advanced VLSI interconnect:." Microelectronic Engineering 57-58 (September 2001): 621–27. http://dx.doi.org/10.1016/s0167-9317(01)00548-2.

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Arora, N. D., K. V. Raol, R. Schumann, and L. M. Richardson. "Modeling and extraction of interconnect capacitances for multilayer VLSI circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 15, no. 1 (1996): 58–67. http://dx.doi.org/10.1109/43.486272.

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Yuji Wei, Qi-Jun Zhang, and M. Nakhla. "Multilevel optimization of high speed VLSI interconnect networks by decomposition." IEEE Transactions on Microwave Theory and Techniques 42, no. 9 (1994): 1638–50. http://dx.doi.org/10.1109/22.310557.

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Eo, Y., and W. R. Eisenstadt. "High-speed VLSI interconnect modeling based on S-parameter measurements." IEEE Transactions on Components, Hybrids, and Manufacturing Technology 16, no. 5 (1993): 555–62. http://dx.doi.org/10.1109/33.239889.

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Journal articles on the topic 'VLSI interconnect'

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