Relevant bibliographies by topics / VLSI Layouts

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'VLSI Layouts'

Author: Grafiati
Published: 3 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "VLSI Layouts"

1

Nandy, S. K. "Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment." VLSI Design 1, no. 2 (1994): 155–67. http://dx.doi.org/10.1155/1994/54126.

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In this paper we provide a distributed solution to perform Design Rule Checking (DRC) of a layout by exploiting either spatial independence or layer independence in layout data. We show that the former approach to DRC can result in reasonable speedup only for large layouts, whereas, the latter approach shows a better performance for smaller layouts. We also provide an algorithm to optimally partition a layout and a scheme to allocate DRC tasks to idle processors in a Distributed Computing Environment (DCE) to attain load balancing.
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Agrawal, Akash, and Prosenjit Gupta. "Incremental analysis of large VLSI Layouts." Integration 42, no. 2 (2009): 203–16. http://dx.doi.org/10.1016/j.vlsi.2008.06.005.

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TAMASSIA, ROBERTO, IOANNIS G. TOLLIS, and JEFFREY SCOTT VITTER. "A Parallel Algorithm for Planar Orthogonal Grid Drawings." Parallel Processing Letters 10, no. 01 (2000): 141–50. http://dx.doi.org/10.1142/s0129626400000147.

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In this paper we consider the problem of constructing planar orthogonal grid drawings (or more simply, layouts) of graphs, with the goal of minimizing the number of bends along the edges. We present optimal parallel algorithms that construct graph layouts with O(n) maximum edge length, O(n2) area, and at most 2n+4 bends (for biconnected graphs) and 2.4n+2 bends (for simply connected graphs). All three of these quality measures for the layouts are optimal in the worst case for biconnected graphs. The algorithm runs on a CREW PRAM in O( log n) time with n/ log n processors, thus achieving optima
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Kurdahi, F. J., and A. C. Parker. "Techniques for area estimation of VLSI layouts." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 8, no. 1 (1989): 81–92. http://dx.doi.org/10.1109/43.21821.

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Krishnan, M. S., and J. P. Hayes. "A normalized-area measure for VLSI layouts." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, no. 3 (1988): 411–19. http://dx.doi.org/10.1109/43.3174.

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Moreira, D. de A., and L. T. Walczowski. "Using software agents to generate VLSI layouts." IEEE Expert 12, no. 6 (1997): 26–32. http://dx.doi.org/10.1109/64.642958.

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Wang, Lih-Yang, Yen-Tai Lai, Bin-Da Liu, and Tin-Chung Chang. "Performance-directed compaction for VLSI symbolic layouts." Computer-Aided Design 27, no. 1 (1995): 65–74. http://dx.doi.org/10.1016/0010-4485(95)90754-4.

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Fernandez, A., and K. Efe. "Efficient VLSI layouts for homogeneous product networks." IEEE Transactions on Computers 46, no. 10 (1997): 1070–82. http://dx.doi.org/10.1109/12.628392.

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Patel, A., A. Kusalik, and C. McCrosky. "Area-efficient VLSI layouts for binary hypercubes." IEEE Transactions on Computers 49, no. 2 (2000): 160–69. http://dx.doi.org/10.1109/12.833112.

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P, Umamaheswari, and Suneel Kumar Asileti. "EXPLORING QUANTUM COMPUTING ALGORITHMS FOR OPTIMIZING VLSI CIRCUIT DESIGN AND FABRICATION PROCESSES." ICTACT Journal on Microelectronics 10, no. 4 (2025): 1938–44. https://doi.org/10.21917/ijme.2025.0331.

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The growing complexity of Very Large Scale Integration (VLSI) circuit designs has significantly increased the demand for innovative approaches to enhance design efficiency and fabrication accuracy. Traditional computational methods face limitations in terms of scalability and optimization for complex VLSI systems. The advent of quantum computing presents a promising paradigm shift, offering exponential speedup in solving computationally intensive problems such as optimization, simulation, and data analysis in VLSI design and fabrication. This research investigates the potential of quantum comp
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Dissertations / Theses on the topic "VLSI Layouts"

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Swisher, Joel V. "Circuit recognition of VLSI layouts." Thesis, Monterey, California. Naval Postgraduate School, 1989. http://hdl.handle.net/10945/25736.

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Al-Mahmood, Saiyid Jami Islah Ahmad. "A distributed design rule checker for VLSI layouts." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-11012008-063423/.

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Bamji, Cyrus S. "Graph-based representations and coupled verification of VLSI schematics and layouts." Thesis, Massachusetts Institute of Technology, 1989. http://hdl.handle.net/1721.1/13999.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1990.<br>Includes bibliographical references (leaves 193-196).<br>by Cyrus S. Bamji.<br>Ph.D.
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Yao, Bo. "Physical planning of VLSI layout /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2005. http://wwwlib.umi.com/cr/ucsd/fullcit?p3189794.

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Sprague, Alan P. "Problems in VLSI layout design /." The Ohio State University, 1988. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487597424138645.

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Jangkrajarng, Nuttorn. "Analog/RF VLSI layout generation : layout retargeting via symbolic template /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6084.

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Cloutier, Jocelyn. "Layout automatique orienté de circuits CMOS VLSI /." [S.l.] : [s.n.], 1990. http://library.epfl.ch/theses/?nr=875.

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Griffin, Glenn. "Intelligent circuit recognition for VLSI layout verification." Master's thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-04272010-020102/.

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Wu, Di. "Layout optimization in ultra deep submicron VLSI design." Texas A&M University, 2005. http://hdl.handle.net/1969.1/3759.

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As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several deep submicron problems (eg. coupling capacitance, antenna effect and delay variation) and propose optimization techniques to mitigate these DSM effects in the place-and-route stage of VLSI physical design. The place-and-route stage of physical design can be further divided into several steps: (1) Placement, (2) Global routing, (3) Layer assignment, (4) Track assignment, a
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Finney, Andrew Martin. "The application of graph algorithms to VLSI layout." Thesis, Brunel University, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.235887.

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Books on the topic "VLSI Layouts"

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Swisher, Joel V. Circuit recognition of VLSI layouts. Naval Postgraduate School, 1989.

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Berlin, Technische Universität, ed. Bounds for linear VLSI layout problems: Schranken für lineare VLSI-Layout-Probleme. [s.n.], 1993.

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Lu, Bing, Ding-Zhu Du, and Sachin S. Sapatnekar, eds. Layout Optimization in VLSI Design. Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3415-7.

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Majid, Sarrafzadeh, and Lee D. T, eds. Algorithmic aspects of VLSI layout. World Scientific, 1993.

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Bing, Lu. Layout optimizations in VLSI designs. Kluwer Academic Publishers, 2001.

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Bing, Lu, Du Dingzhu, and Sapatnekar Sachin S. 1967-, eds. Layout optimizations in VLSI design. Kluwer Academic Publishers, 2001.

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1930-, Hu T. C., Kuh Ernest S, and Institute of Electrical and Electronics Engineers., eds. VLSI circuit layout: Theory and design. Institute of Electrical and Electronics Engineers, 1985.

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Wong, D. F. Algorithmic aspects of VLSI circuit layout. Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1987.

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Ravikumār, C. P. Parallel methods for VLSI layout design. Ablex, 1996.

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Solworth, J. GENERIC: a programming language for VLSI layout and layout manipulation. Courant Institute of Mathematical Sciences, New York University, 1987.

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Book chapters on the topic "VLSI Layouts"

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Moiseev, Konstantin, Avinoam Kolodny, and Shmuel Wimer. "Multi-net Sizing and Spacing in General Layouts." In Multi-Net Optimization of VLSI Interconnect. Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-0821-5_7.

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Pineda de Gyvez, J., and J. A. G. Jess. "Systematic Extraction of Critical Areas From IC Layouts." In Defect and Fault Tolerance in VLSI Systems. Springer US, 1990. http://dx.doi.org/10.1007/978-1-4757-9957-6_4.

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Sherlekar, Deepak D. "Optimality of gauge and degree-sensitive VLSI layouts of planar graphs." In Advances in Computing and Information — ICCI '90. Springer Berlin Heidelberg, 1990. http://dx.doi.org/10.1007/3-540-53504-7_109.

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Khatri, Sunil P., Robert K. Brayton, and Alberto L. Sangiovanni-Vincentelli. "VLSI Layout Fabrics." In Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics. Springer US, 2001. http://dx.doi.org/10.1007/978-1-4615-1477-0_3.

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Bhargava, Cherry, and Gaurav Mani Khanal. "CMOS Design and Layout." In Advanced VLSI Technology. River Publishers, 2022. http://dx.doi.org/10.1201/9781003337065-2.

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Otten, Ralph. "Layout Compilation." In Design Systems for VLSI Circuits. Springer Netherlands, 1987. http://dx.doi.org/10.1007/978-94-009-3649-2_13.

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Hörbst, Egon, Christian Müller-Schloer, and Heinz Schwärtzel. "Layout Design Methods." In Design of VLSI Circuits. Springer Berlin Heidelberg, 1987. http://dx.doi.org/10.1007/978-3-642-95525-9_3.

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Bhuvaneswari, M. C., and M. Jagadeeswari. "Circuit Partitioning for VLSI Layout." In Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems. Springer India, 2014. http://dx.doi.org/10.1007/978-81-322-1958-3_3.

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Moiseev, Konstantin, Avinoam Kolodny, and Shmuel Wimer. "Layout Migration." In Multi-Net Optimization of VLSI Interconnect. Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-0821-5_9.

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Trimberger, Stephen M. "Plotting Layout." In An Introduction to CAD for VLSI. Springer US, 1987. http://dx.doi.org/10.1007/978-1-4613-1993-1_4.

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Conference papers on the topic "VLSI Layouts"

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Mou, Zhiping, Kun Ren, Dawei Gao, and Shibin Xu. "Pattern Match in VLSI Layout with Window Dance." In 2024 2nd International Symposium of Electronics Design Automation (ISEDA). IEEE, 2024. http://dx.doi.org/10.1109/iseda62518.2024.10617563.

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Schnecke, V. "Genetic design of VLSI-layouts." In 1st International Conference on Genetic Algorithms in Engineering Systems: Innovations and Applications (GALESIA). IEE, 1995. http://dx.doi.org/10.1049/cp:19951087.

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Chi-Hsiang Yeh, E. A. Varvarigos, and B. Parhami. "Efficient VLSI layouts of hypercubic networks." In Proceedings. Frontiers '99. Seventh Symposium on the Frontiers of Massively Parallel Computation. IEEE, 1999. http://dx.doi.org/10.1109/fmpc.1999.750589.

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Dao, Joseph, Nobu Matsumoto, Tsuneo Hamai, Chusei Ogawa, and Shojiro Mori. "A compaction method for full chip VLSI layouts." In the 30th international. ACM Press, 1993. http://dx.doi.org/10.1145/157485.164953.

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Kumar, Yokesh, and Prosenjit Gupta. "Reducing EPL Alignment Errors for Large VLSI Layouts." In 8th International Symposium on Quality Electronic Design (ISQED'07). IEEE, 2007. http://dx.doi.org/10.1109/isqed.2007.135.

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Saraogi, Eshan, Giriraj Singh Chouhan, Dipesh Panchal, Manish I. Patel, and Ruchi Gajjar. "CNN based Design Rule Checker for VLSI Layouts." In 2021 IEEE 2nd International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC). IEEE, 2021. http://dx.doi.org/10.1109/aespc52704.2021.9708453.

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Salodkar, Nitin, Subramanian Rajagopalan, Sambuddha Bhattacharya, and Shabbir Batterywala. "2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids." In 2015 28th International Conference on VLSI Design (VLSID). IEEE, 2015. http://dx.doi.org/10.1109/vlsid.2015.37.

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Ghosh, Jyotirmoy, Siddhartha Mukhopadhyay, Amit Patra, Barry Culpepper, and Tawen Mei. "A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts." In 21st International Conference on VLSI Design (VLSID 2008). IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.87.

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Thenappan, M., Arasu T. Senthil, K. M. Sreekanth, and Ramesh S. Guzar. "An Overlap Removal Algorithm for Macrocell Placement in VLSI Layouts." In 2007 International Conference on Computing: Theory and Applications (ICCTA'07). IEEE, 2007. http://dx.doi.org/10.1109/iccta.2007.30.

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Leiserson, C. E., and F. M. Maley. "Algorithms for routing and testing routability of planar VLSI layouts." In the seventeenth annual ACM symposium. ACM Press, 1985. http://dx.doi.org/10.1145/22145.22153.

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Reports on the topic "VLSI Layouts"

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Chuang, Wei-Tong. Timing and Area Optimization for VLSI Circuit and Layout. Defense Technical Information Center, 1994. http://dx.doi.org/10.21236/ada281081.

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Solomon, Jeff, and Mark Horowitz. Using Texture Mapping With Mipmapping to Render a VLSI Layout. Defense Technical Information Center, 2001. http://dx.doi.org/10.21236/ada419603.

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Robinson, David. Automatic Synthesis of VLSI Layout for Analog Continuous-time Filters. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.6789.

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