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Books on the topic 'VLSI Layouts'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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1

Swisher, Joel V. Circuit recognition of VLSI layouts. Naval Postgraduate School, 1989.

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2

Berlin, Technische Universität, ed. Bounds for linear VLSI layout problems: Schranken für lineare VLSI-Layout-Probleme. [s.n.], 1993.

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3

Lu, Bing, Ding-Zhu Du, and Sachin S. Sapatnekar, eds. Layout Optimization in VLSI Design. Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3415-7.

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4

Majid, Sarrafzadeh, and Lee D. T, eds. Algorithmic aspects of VLSI layout. World Scientific, 1993.

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5

Bing, Lu. Layout optimizations in VLSI designs. Kluwer Academic Publishers, 2001.

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6

Bing, Lu, Du Dingzhu, and Sapatnekar Sachin S. 1967-, eds. Layout optimizations in VLSI design. Kluwer Academic Publishers, 2001.

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7

1930-, Hu T. C., Kuh Ernest S, and Institute of Electrical and Electronics Engineers., eds. VLSI circuit layout: Theory and design. Institute of Electrical and Electronics Engineers, 1985.

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8

Wong, D. F. Algorithmic aspects of VLSI circuit layout. Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1987.

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9

Ravikumār, C. P. Parallel methods for VLSI layout design. Ablex, 1996.

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10

Solworth, J. GENERIC: a programming language for VLSI layout and layout manipulation. Courant Institute of Mathematical Sciences, New York University, 1987.

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11

Hill, Dwight, Don Shugard, John Fishburn, and Kurt Keutzer. Algorithms and Techniques for VLSI Layout Synthesis. Springer US, 1988. http://dx.doi.org/10.1007/978-1-4613-1707-4.

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12

Hill, Dwight. Algorithms and Techniques for VLSI Layout Synthesis. Springer US, 1988.

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13

D, Hill Dwight, and American Telephone and Telegraph Company., eds. Algorithms and techniques for VLSI layout synthesis. Kluwer Academic Publishers, 1989.

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14

M, Rudnick Elizabeth, ed. Genetic algorithms for VLSI design, layout & test automation. Prentice Hall PTR, 1999.

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15

Finney, Andrew Martin. The application of graph algorithms to VLSI layout. Brunel University, 1989.

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16

Uyemura, John P. Chip design for submicron VLSI: CMOS layout and simulation. Thomson, 2004.

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17

Khatri, Sunil P., Robert K. Brayton, and Alberto L. Sangiovanni-Vincentelli. Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics. Springer US, 2001. http://dx.doi.org/10.1007/978-1-4615-1477-0.

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18

Khatri, Sunil P. Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics. Springer US, 2001.

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19

Khatri, Sunil P. Cross-talk noise immune VLSI design using regular layout fabrics. Kluwer Academic, 2001.

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20

King, Brayton Robert, and Sangiovanni-Vincentelli Alberto, eds. Cross-talk noise immune VLSI design using regular layout fabrics. Kluwer Academic, 2001.

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21

Zheng, Jianqing. CMOS VLSI layout and verification of a SIMD computer: A thesis ... National Aeronautics and Space Administration, 1996.

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22

Bushnell, Michael L. Design automation: Automated full-custom VLSI layout using the ULYSSES design environment. Academic Press, 1988.

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23

Sarrafzadeh, Majid. Modern placement techniques. Kluwer Academic, 2003.

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24

Bryant, Robert Louis. Three-track VLSI layouts in polynomial time. 1987.

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25

Paths, flows, and VLSI-layout. Springer-Verlag, 1990.

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26

Sarrafzadeh, M., and D. T. Lee. Algorithmic Aspects of VLSI Layout. WORLD SCIENTIFIC, 1993. http://dx.doi.org/10.1142/2105.

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27

Algorithmic Aspects of VLSI Layout. World Scientific Publishing Co Pte Ltd, 1993.

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28

Algorithmic Aspects of VLSI Layout. World Scientific Publishing Co Pte Ltd, 1993.

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29

Du, Ding-Zhu, Bing Lu, and S. Sapatnekar. Layout Optimization in VLSI Design. Springer, 2010.

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30

Lu, Bing Bing, S. Sapatnekar, and Ding-Zhu Ding-Zhu Du. Layout Optimization in VLSI Design. Springer London, Limited, 2013.

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31

Parallel methods for VLSI layout design. Ablex Pub., 1996.

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32

Generic: A Programming Language for VLSI Layout and Layout Manipulation. Creative Media Partners, LLC, 2023.

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33

Generic: A Programming Language for VLSI Layout and Layout Manipulation. Creative Media Partners, LLC, 2023.

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34

Zhu, Qing K. Interconnect RC and Layout Extraction for VLSI. Trafford Publishing, 2002.

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35

Algorithms and Techniques for VLSI Layout Synthesis. Springer, 2011.

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36

Rowan, George S. Efficient heuristics for multi-stack VLSI layout. 1987.

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37

Rudnick, Elizabeth, and Pinaki Mazumder. Genetic Algorithms for Vlsi Design, Layout & Test Automation. Prentice Hall PTR, 1998.

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38

Rudnick, Elizabeth, and Pinaki Mazumder. Genetic Algorithms for Vlsi Design, Layout & Test Automation. Prentice Hall PTR, 1998.

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39

Uyemura, John P. Chip Design for Submicron VLSI: CMOS Layout and Simulation. CL, 2005.

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40

Uyemura, John P. Chip Design for Submicron VLSI: CMOS Layout and Simulation. Thomson-Engineering, 2005.

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41

(Editor), Bing Lu, Ding-Zhu Du (Editor), and S. Sapatnekar (Editor), eds. Layout Optimization in VLSI Design (Network Theory and Applications). Springer, 2001.

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42

Chip design for submicron VLSI: CMOS layout and simulation. Thomson/Nelson, 2006.

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43

Brayton, Robert K., Alberto L. Sangiovanni-Vincentelli, and Sunil P. Khatri. Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics. Springer, 2001.

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44

CMOS VLSI layout and verification of a SIMD computer: A thesis ... National Aeronautics and Space Administration, 1996.

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45

Ravikumar, C. P. Parallel Methods for VLSI Layout Design: (Computer Engineering and Computer Science). Ablex Publishing, 1995.

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46

Bushnell, Michael L. Design automation: Automated full-custom VLSI layout using theULYSSES design environment. Academic, 1988.

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47

Hu, Te Chiang. Vlsi Circuit Layout: Theory and Design (Ieee Press Selected Reprint Series). Ieee, 1985.

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48

Bushnell, Michael. Design Automation: Automated Full-Custom VLSI Layout Using the ULYSSES Design Environment. Elsevier Science & Technology Books, 2012.

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49

Li, Wanhao. Automatic generation of flexible CMOS cells for general cell VLSI layout systems. 1987.

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50

Keutzer, Kurt, Dwight Hill, Don Shugard, and John Fishburn. Algorithms and Techniques for VLSI Layout Synthesis (The International Series in Engineering and Computer Science). Springer, 1988.

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