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Journal articles on the topic 'VLSI Layouts'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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1

Nandy, S. K. "Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment." VLSI Design 1, no. 2 (1994): 155–67. http://dx.doi.org/10.1155/1994/54126.

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In this paper we provide a distributed solution to perform Design Rule Checking (DRC) of a layout by exploiting either spatial independence or layer independence in layout data. We show that the former approach to DRC can result in reasonable speedup only for large layouts, whereas, the latter approach shows a better performance for smaller layouts. We also provide an algorithm to optimally partition a layout and a scheme to allocate DRC tasks to idle processors in a Distributed Computing Environment (DCE) to attain load balancing.

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2

Agrawal, Akash, and Prosenjit Gupta. "Incremental analysis of large VLSI Layouts." Integration 42, no. 2 (2009): 203–16. http://dx.doi.org/10.1016/j.vlsi.2008.06.005.

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3

TAMASSIA, ROBERTO, IOANNIS G. TOLLIS, and JEFFREY SCOTT VITTER. "A Parallel Algorithm for Planar Orthogonal Grid Drawings." Parallel Processing Letters 10, no. 01 (2000): 141–50. http://dx.doi.org/10.1142/s0129626400000147.

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In this paper we consider the problem of constructing planar orthogonal grid drawings (or more simply, layouts) of graphs, with the goal of minimizing the number of bends along the edges. We present optimal parallel algorithms that construct graph layouts with O(n) maximum edge length, O(n2) area, and at most 2n+4 bends (for biconnected graphs) and 2.4n+2 bends (for simply connected graphs). All three of these quality measures for the layouts are optimal in the worst case for biconnected graphs. The algorithm runs on a CREW PRAM in O( log n) time with n/ log n processors, thus achieving optima

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4

Kurdahi, F. J., and A. C. Parker. "Techniques for area estimation of VLSI layouts." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 8, no. 1 (1989): 81–92. http://dx.doi.org/10.1109/43.21821.

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5

Krishnan, M. S., and J. P. Hayes. "A normalized-area measure for VLSI layouts." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, no. 3 (1988): 411–19. http://dx.doi.org/10.1109/43.3174.

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6

Moreira, D. de A., and L. T. Walczowski. "Using software agents to generate VLSI layouts." IEEE Expert 12, no. 6 (1997): 26–32. http://dx.doi.org/10.1109/64.642958.

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7

Wang, Lih-Yang, Yen-Tai Lai, Bin-Da Liu, and Tin-Chung Chang. "Performance-directed compaction for VLSI symbolic layouts." Computer-Aided Design 27, no. 1 (1995): 65–74. http://dx.doi.org/10.1016/0010-4485(95)90754-4.

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8

Fernandez, A., and K. Efe. "Efficient VLSI layouts for homogeneous product networks." IEEE Transactions on Computers 46, no. 10 (1997): 1070–82. http://dx.doi.org/10.1109/12.628392.

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9

Patel, A., A. Kusalik, and C. McCrosky. "Area-efficient VLSI layouts for binary hypercubes." IEEE Transactions on Computers 49, no. 2 (2000): 160–69. http://dx.doi.org/10.1109/12.833112.

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10

P, Umamaheswari, and Suneel Kumar Asileti. "EXPLORING QUANTUM COMPUTING ALGORITHMS FOR OPTIMIZING VLSI CIRCUIT DESIGN AND FABRICATION PROCESSES." ICTACT Journal on Microelectronics 10, no. 4 (2025): 1938–44. https://doi.org/10.21917/ijme.2025.0331.

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The growing complexity of Very Large Scale Integration (VLSI) circuit designs has significantly increased the demand for innovative approaches to enhance design efficiency and fabrication accuracy. Traditional computational methods face limitations in terms of scalability and optimization for complex VLSI systems. The advent of quantum computing presents a promising paradigm shift, offering exponential speedup in solving computationally intensive problems such as optimization, simulation, and data analysis in VLSI design and fabrication. This research investigates the potential of quantum comp

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11

Nandy, S. K., and R. B. Panwar. "Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors." VLSI Design 1, no. 2 (1994): 127–54. http://dx.doi.org/10.1155/1994/96830.

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Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC) of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

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12

BHATTACHARYA, S., S. KIRANI, and W. T. TSAI. "QUADTREE LAYOUTS AND I/O BANDWIDTH." Parallel Processing Letters 05, no. 02 (1995): 231–40. http://dx.doi.org/10.1142/s0129626495000217.

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Quadtree data structure, popular in 2-D applications, has not been studied in the context of VLSI embedding. This paper proposes two generic layout strategies for quadtree layout. Layout attributes are derived with primary focus on area-I/O trade-off. We demonstrate a simple layout mixing strategy to obtain improved boundary I/O characteristics. This is followed by development of a recursive layout mixing strategy which yields an order of improvement.

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13

Mehta, D. P., and G. Blust. "Corner stitching for simple rectilinear shapes [VLSI layouts]." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, no. 2 (1997): 186–98. http://dx.doi.org/10.1109/43.573833.

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14

Linhares, A. "Synthesizing a predatory search strategy for VLSI layouts." IEEE Transactions on Evolutionary Computation 3, no. 2 (1999): 147–52. http://dx.doi.org/10.1109/4235.771168.

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15

Shun-Lin Su, C. H. Barry, and Chi-Yuan Lo. "A space-efficient short-finding algorithm [VLSI layouts]." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 8 (1994): 1065–68. http://dx.doi.org/10.1109/43.298043.

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16

Kodandapani, K. L., and Edward McGrath. "A Wirelist Compare Program for Verifying VLSI Layouts." IEEE Design & Test of Computers 3, no. 3 (1986): 46–51. http://dx.doi.org/10.1109/mdt.1986.294992.

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17

Ahuja, Narendra. "Efficient planar embedding of trees for VLSI layouts." Computer Vision, Graphics, and Image Processing 34, no. 2 (1986): 189–203. http://dx.doi.org/10.1016/s0734-189x(86)80058-5.

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18

Aboelaze, Mokhtar A., and Benjamin W. Wah. "Complexities of layouts in three-dimensional VLSI circuits." Information Sciences 55, no. 1-3 (1991): 167–88. http://dx.doi.org/10.1016/0020-0255(91)90012-j.

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19

Bhasin, Inderpreet, and Joseph G. Tront. "Block-Level Logic Extraction from CMOS VLSI Layouts." VLSI Design 1, no. 3 (1994): 243–59. http://dx.doi.org/10.1155/1994/67035.

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This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level description of a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to that of a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors, resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be used to identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to the circuit hierarchy. Basic gates

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20

Yeh, Chi-Hsiang, and Behrooz Parhami. "VLSI layouts of complete graphs and star graphs." Information Processing Letters 68, no. 1 (1998): 39–45. http://dx.doi.org/10.1016/s0020-0190(98)00133-1.

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21

Bhatt, Sandeep N., and Stavros S. Cosmadakis. "The complexity of minimizing wire lengths in VLSI layouts." Information Processing Letters 25, no. 4 (1987): 263–67. http://dx.doi.org/10.1016/0020-0190(87)90173-6.

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22

Al-Khalili, A. J., D. Al-Khalili, and K. Ammar. "An algorithm for polygon conversion to boxes for VLSI layouts." Integration 6, no. 3 (1988): 291–308. http://dx.doi.org/10.1016/0167-9260(88)90004-1.

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23

Sýkora, Ondrej, and Imrich Vrt'o. "On VLSI layouts of the star graph and related networks." Integration 17, no. 1 (1994): 83–93. http://dx.doi.org/10.1016/0167-9260(94)90021-3.

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24

Jin-Fuw Lee. "A new framework of design rules for compaction of VLSI layouts." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, no. 11 (1988): 1195–204. http://dx.doi.org/10.1109/43.9189.

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25

de Sá, Vinícius G. P., Celina M. H. de Figueiredo, Guilherme D. da Fonseca, and Raphael Machado. "Complexity dichotomy on degree-constrained VLSI layouts with unit-length edges." Electronic Notes in Discrete Mathematics 36 (August 2010): 391–98. http://dx.doi.org/10.1016/j.endm.2010.05.050.

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26

HUANG, Y. M., and M. SARRAFZADEH. "A PARALLEL ALGORITHM FOR MINIMUM DUAL-COVER WITH APPLICATION TO CMOS LAYOUT." Journal of Circuits, Systems and Computers 01, no. 02 (1991): 177–204. http://dx.doi.org/10.1142/s0218126691000045.

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In a pair of planar graphs (G, Gd), with Gd being the dual graph of G, a sequence of distinct edges is a dual-Euler trail if it is a trail both in G and in Gd. A set of disjoint dual-Euler trails that simultaneously cover G and Gd is called a dual-cover. We present an O( log n) time and O(n) processors algorithm, in PRAM model, based on the graph separator theory, for obtaining a minimum cardinality dual-cover in a pair of series-parallel graphs (G, Gd), where n is the total number of edges. We employ the proposed algorithm to obtain a minimum-area VLSI layout of CMOS functional cells. Our alg

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27

M G Srinivasa and Bhavana M S. "Performance Analysis of 6T, 8T and 10T SRAM Cell in 45nm Technology." International Journal of Engineering and Advanced Technology 13, no. 5 (2024): 12–16. http://dx.doi.org/10.35940/ijeat.e4447.13050624.

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The rise of portable battery-powered devices has emphasized the significance of low power IC design. Embedded SRAM units have become indispensable elements within contemporary SOCs due to their substantial footprint. In research circles, SRAM is highly regarded as a semiconductor memory type, highlighting its crucial role in the VLSI sector. In this paper, 6T, 8T and 10T SRAM cells design is estimated for power consumption and delay. This proposed work presents the schematic, simulation of analysis of 6T, 8T and 10T SRAM cells at 45 nm technology. The Cadence Virtuoso software is utilized for

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28

M, G. Srinivasa. "Performance Analysis of 6T, 8T and 10T SRAM Cell in 45nm Technology." International Journal of Engineering and Advanced Technology (IJEAT) 13, no. 5 (2024): 12–16. https://doi.org/10.35940/ijeat.E4447.13050624.

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<strong>Abstract:</strong> The rise of portable battery-powered devices has emphasized the significance of low power IC design. Embedded SRAM units have become indispensable elements within contemporary SOCs due to their substantial footprint. In research circles, SRAM is highly regarded as a semiconductor memory type, highlighting its crucial role in the VLSI sector. In this paper, 6T, 8T and 10T SRAM cells design is estimated for power consumption and delay. This proposed work presents the schematic, simulation of analysis of 6T, 8T and 10T SRAM cells at 45 nm technology. The Cadence Virtuos

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29

UTTRAPHAN, Chessda, Nasir SHAIKH-HUSIN, and Mohamed KHALIL-HANI. "An optimized buffer insertion algorithm with delay-power constraints for VLSI layouts." TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 25 (2017): 844–61. http://dx.doi.org/10.3906/elk-1411-129.

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30

Chen, H. F. S., and D. T. Lee. "A faster algorithm for rubber-band equivalent transformation for planar VLSI layouts." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 15, no. 2 (1996): 217–27. http://dx.doi.org/10.1109/43.486667.

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31

Sengupta, C., J. R. Cavallaro, W. L. Wilson, and F. K. Tittel. "Automated evaluation of critical features in VLSI layouts based on photolithographic simulations." IEEE Transactions on Semiconductor Manufacturing 10, no. 4 (1997): 482–94. http://dx.doi.org/10.1109/66.641490.

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32

Schmeck, Hartmut. "On the maximum edge length in VLSI layouts of complete binary trees." Information Processing Letters 23, no. 1 (1986): 19–23. http://dx.doi.org/10.1016/0020-0190(86)90124-9.

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33

Lopez, Mario A., and Dinesh P. Mehta. "Efficient decomposition of polygons into L-shapes with application to VLSI layouts." ACM Transactions on Design Automation of Electronic Systems 1, no. 3 (1996): 371–95. http://dx.doi.org/10.1145/234860.234865.

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34

ARTISHCHEV-ZAPOLOTSKY, MARIA, YEFIM DINITZ, SHIMON EVEN, and VLADIMIR YANOVSKY. "LAYOUT OF AN ARBITRARY PERMUTATION IN A MINIMAL RIGHT TRIANGLE AREA." Journal of Interconnection Networks 08, no. 02 (2007): 101–18. http://dx.doi.org/10.1142/s0219265907001928.

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In VLSI layout of interconnection networks, routing two-point nets in some restricted area is one of the central operations. The main aim is usually minimization of the layout area, while reducing the number of wire bends is also very useful. In this paper, we consider connecting a set of N inputs on a line to a set of N outputs on a perpendicular line inside a right triangle shaped area, where the order of the outputs is a given permutation of the order of the corresponding inputs. Such triangles were used, for example, by Dinitz, Even, and Artishchev-Zapolotsky for an optimal layout of the B

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35

Tyagi, Akhilesh. "Statistical Module Level Area and Delay Estimation." VLSI Design 5, no. 2 (1997): 141–53. http://dx.doi.org/10.1155/1997/78238.

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The increasing complexity of VLSI design process has led to an increasing use of layout synthesis systems. For many components of a high-level synthesis system such as module generators and module generator development environments, an accurate model of area and delay for the layouts generated by a layout synthesis system is extremely desirable. We have experimented with a statistical model for area and delay of function modules. This model is surprisingly accurate for a standard cell based layout synthesis systemૼVPNR. The area of adder and shifter modules can be modeled to with in 5% accurac

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36

Ho, K. C., and S. B. K. Vrudhula. "Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 10 (1994): 1201–22. http://dx.doi.org/10.1109/43.317463.

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37

Nandy, S. K., and L. M. Patnaik. "Linear time geometrical design rule checker based on quadtree representation of VLSI mask layouts." Computer-Aided Design 18, no. 7 (1986): 380–88. http://dx.doi.org/10.1016/0010-4485(86)90225-3.

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38

Gannett, J. W. "SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layouts." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9, no. 6 (1990): 669–74. http://dx.doi.org/10.1109/43.55197.

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39

Abbas, Rezaei, Mostafaee Abed, Mahdi Karkhanehchi Mohammad, and Muhammad Jamshidi Seyed. "Design of QCA Full Adders without Wire Crossing." Boson Journal of Modern Physics 2, no. 2 (2015): 90–96. https://doi.org/10.5281/zenodo.3969483.

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In the scale of nanometer, Quantum-dot Cellular Automata (QCA) is a new technology, which utilizes the QCA cells in order to design and implement logical circuits. QCA makes it possible for us to design in Nano scale. Furthermore, in comparison to CMOS technology, it has highly low consumption power. Thus, in the future, QCA technology will be a powerful rival for VLSI. This paper presents two new and optimized QCA designs for Full adder. In comparison to the previous designs, all of the QCA Full adders presented in this paper are relatively optimized. In addition, they are implemented without

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40

Mukherjee, Chiradeep, Saradindu Panda, Asish K. Mukhopadhyay, and Bansibadan Maji. "Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata." Nanoscience & Nanotechnology-Asia 10, no. 4 (2020): 534–47. http://dx.doi.org/10.2174/2210681209666190412142207.

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Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliab

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41

Wolf, Wayne. "Complexity Issues in VLSI—Optimal Layouts for the Shuffle-Exchange Graph and Other Networks (Frank Thomson Leighton)." SIAM Review 28, no. 2 (1986): 287–88. http://dx.doi.org/10.1137/1028099.

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42

Wang, Wei, M. N. S. Swamy, M. O. Ahmad, and Yuke Wang. "A Parallel Residue-to-binary Converter for the Moduli Set {2m−1,220m+1,221m+1,…,22km+1}." VLSI Design 14, no. 2 (2002): 183–91. http://dx.doi.org/10.1080/10655140290010097.

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In this paper, a high-speed parallel residue-to-binary converter is proposed for a recently introduced moduli set Sk={2m−1,220m+1,221m+1,…,22km+1} for a general value of k. The proposed converter uses simple cyclic shift and concatenation operations and does not require any multiplier. Individual converters for the cases of k=0 and k=1 are derived from the general architecture and compared with those existing in the literature. The converter for S0 is twice as fast requiring only one-half of the hardware, while that of S1 is three times as fast, but requiring only 60% of the hardware, as compa

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43

Saha, Indranil, Bhargab B. Bhattacharya, Sheng Zhang, and Sharad C. Seth. "Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid." Fundamenta Informaticae 89, no. 2-3 (2008): 331–44. https://doi.org/10.3233/fun-2008-892-308.

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Double-tree-scan (DTS) is a new scan-path architecture that is deemed to be suitable for low-power testing of VLSI circuits. A full DTS resembles two complete k-level (k > 0) binary trees whose leaf nodes are merged pair-wise, and thus consists of exactly N _{k} = 3 × 2 ^{k} − 2 nodes. In this paper, the problem of planar straight-line embedding of a "double-tree graph" on a rectangular grid is investigated and an O(N _{k} ) time algorithm for drawing it, is described. The embedding requires at most 2N _{k} grid points, with an aspect ratio lying between 1 and �. Next, techniques of embeddi

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44

PICQUENDAR, MARC, ARNOLD L. ROSENBERG, and VITTORIO SCARANO. "A COST-EFFECTIVE STREAMLINING OF THE DIOGENES DESIGN METHODOLOGY." Parallel Processing Letters 05, no. 03 (1995): 513–24. http://dx.doi.org/10.1142/s0129626495000461.

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The original DIOGENES design methodology produces fault-tolerant layouts of VLSI processor arrays by designing an array's interconnection network as a (possibly large) number of (re)configurable bundles of wires, each bundle being organized as either a stack or a queue. The benefits of DIOGENES often come only at high cost, in terms of both configuration hardware and algorithmic cost of configuration. In this paper, we improve the original methodology in a way that simultaneously: streamlines the design process; produces more cost-effective layouts; can be augmented to allow efficient dynamic

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45

V, Vani, and G. R. Prasad. "An Improved Augmented Line Segment based Algorithm for the Generation of Rectilinear Steiner Minimum Tree." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 3 (2017): 1262. http://dx.doi.org/10.11591/ijece.v7i3.pp1262-1267.

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An improved Augmented Line Segment Based (ALSB) algorithm for the construction of Rectilinear Steiner Minimum Tree using augmented line segments is proposed. The proposed algorithm works by incrementally increasing the length of line segments drawn from all the points in four directions. The edges are incrementally added to the tree when two line segments intersect. The reduction in cost is obtained by postponing the addition of the edge into the tree when both the edges (upper and lower L-shaped layouts) are of same length or there is no overlap. The improvement is focused on reduction of the

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46

Bourbakis, Nikolaos G., and M. Mortazavi. "A VLSI DESIGN DESIGN-SYNTHESIS METHODOLOGY AT THE TRANSISTOR LAYOUT LEVEL." Journal of Integrated Design and Process Science: Transactions of the SDPS, Official Journal of the Society for Design and Process Science 9, no. 3 (2005): 63–85. http://dx.doi.org/10.3233/jid-2005-9306.

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This paper presents a VLSI design synthesis methodology based on the Geometria language. Geometria is a context-free language, which has the ability of floorplanning, compaction and automated synthesis of functional blocks at various levels of a VLSI integration, starting from the transistor level. The Geometria methodology used in this paper deals with the design synthesis of VLSI circuit layout. More specifically it accepts various user's inputs such as stick diagram, circuit schematics, Boolean expression, netlists, or natural language text expressions, and produces automatically the desira

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47

Froleyks, B., B. Korte, and H. J. Prömel. "Routing in VLSI-layout." Acta Mathematicae Applicatae Sinica 7, no. 1 (1991): 53–66. http://dx.doi.org/10.1007/bf02080203.

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48

HUANG, KE, and JIE WU. "AREA EFFICIENT LAYOUT OF BALANCED HYPERCUBES." International Journal of High Speed Electronics and Systems 06, no. 04 (1995): 631–45. http://dx.doi.org/10.1142/s0129156495000237.

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As a multicomputer structure, the balanced hypercube is a variant of the standard hypercube for multicomputers, with desirable properties of strong connectivity, regularity, and symmetry. This structure is a special type of load balanced graph designed to tolerate processor failure. In balanced hypercubes, each processor has a backup (matching) processor that shares the same set of neighboring nodes. Therefore, tasks that run on a faulty processor can be reactivated in the backup processor to provide efficient system reconfiguration. In this paper, we study the implementation of balanced hyper

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49

Stoliar, P., I. Akita, O. Schneegans, M. Hioki, and M. J. Rozenberg. "A spiking neuron implemented in VLSI." Journal of Physics Communications 6, no. 2 (2022): 021001. http://dx.doi.org/10.1088/2399-6528/ac4e2a.

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Abstract A VLSI implementation of a Silicon-Controlled Rectifier (SCR)-based Neuron that has the functionality of the leaky-integrate and fire model (LIF) of spiking neurons is introduced. The silicon-controlled rectifier is not straightforward to efficiently migrate to VLSI. Therefore, we propose a MOS transistor-based circuit that provides the same functionality as the SCR. The results of this work are based on Spice simulation using open libraries and on VLSI layout and post layout simulations for a 65 nm CMOS process.

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50

Manuel, Paul, Kalim Qureshi, Albert William, and Albert Muthumalai. "VLSI layout of Benes networks." Journal of Discrete Mathematical Sciences and Cryptography 10, no. 4 (2007): 461–72. http://dx.doi.org/10.1080/09720529.2007.10698132.

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